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Rev | Author | Line No. | Line |
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1964 | serge | 1 | /* |
2 | * pci.h |
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3 | * |
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4 | * PCI defines and function prototypes |
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5 | * Copyright 1994, Drew Eckhardt |
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6 | * Copyright 1997--1999 Martin Mares |
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7 | * |
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8 | * For more information, please consult the following manuals (look at |
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9 | * http://www.pcisig.com/ for how to get them): |
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10 | * |
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11 | * PCI BIOS Specification |
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12 | * PCI Local Bus Specification |
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13 | * PCI to PCI Bridge Specification |
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14 | * PCI System Design Guide |
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15 | */ |
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1970 | serge | 16 | #ifndef LINUX_PCI_H |
17 | #define LINUX_PCI_H |
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18 | |||
3031 | serge | 19 | #include |
1408 | serge | 20 | #include |
2161 | serge | 21 | #include |
22 | #include |
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1408 | serge | 23 | |
1628 | serge | 24 | |
2161 | serge | 25 | #define PCI_CFG_SPACE_SIZE 256 |
26 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
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1970 | serge | 27 | |
2161 | serge | 28 | |
1408 | serge | 29 | #define PCI_ANY_ID (~0) |
30 | |||
31 | |||
32 | #define PCI_CLASS_NOT_DEFINED 0x0000 |
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33 | #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
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34 | |||
35 | #define PCI_BASE_CLASS_STORAGE 0x01 |
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36 | #define PCI_CLASS_STORAGE_SCSI 0x0100 |
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37 | #define PCI_CLASS_STORAGE_IDE 0x0101 |
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38 | #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
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39 | #define PCI_CLASS_STORAGE_IPI 0x0103 |
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40 | #define PCI_CLASS_STORAGE_RAID 0x0104 |
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41 | #define PCI_CLASS_STORAGE_SATA 0x0106 |
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42 | #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
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43 | #define PCI_CLASS_STORAGE_SAS 0x0107 |
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44 | #define PCI_CLASS_STORAGE_OTHER 0x0180 |
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45 | |||
46 | #define PCI_BASE_CLASS_NETWORK 0x02 |
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47 | #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
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48 | #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
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49 | #define PCI_CLASS_NETWORK_FDDI 0x0202 |
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50 | #define PCI_CLASS_NETWORK_ATM 0x0203 |
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51 | #define PCI_CLASS_NETWORK_OTHER 0x0280 |
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52 | |||
53 | #define PCI_BASE_CLASS_DISPLAY 0x03 |
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54 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
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55 | #define PCI_CLASS_DISPLAY_XGA 0x0301 |
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56 | #define PCI_CLASS_DISPLAY_3D 0x0302 |
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57 | #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
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58 | |||
59 | #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
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60 | #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
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61 | #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
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62 | #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
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63 | #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
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64 | |||
65 | #define PCI_BASE_CLASS_MEMORY 0x05 |
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66 | #define PCI_CLASS_MEMORY_RAM 0x0500 |
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67 | #define PCI_CLASS_MEMORY_FLASH 0x0501 |
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68 | #define PCI_CLASS_MEMORY_OTHER 0x0580 |
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69 | |||
70 | #define PCI_BASE_CLASS_BRIDGE 0x06 |
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71 | #define PCI_CLASS_BRIDGE_HOST 0x0600 |
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72 | #define PCI_CLASS_BRIDGE_ISA 0x0601 |
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73 | #define PCI_CLASS_BRIDGE_EISA 0x0602 |
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74 | #define PCI_CLASS_BRIDGE_MC 0x0603 |
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75 | #define PCI_CLASS_BRIDGE_PCI 0x0604 |
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76 | #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
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77 | #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
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78 | #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
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79 | #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
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80 | #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
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81 | |||
82 | #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
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83 | #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
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84 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
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85 | #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
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86 | #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
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87 | #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
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88 | |||
89 | #define PCI_BASE_CLASS_SYSTEM 0x08 |
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90 | #define PCI_CLASS_SYSTEM_PIC 0x0800 |
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91 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
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92 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
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93 | #define PCI_CLASS_SYSTEM_DMA 0x0801 |
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94 | #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
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95 | #define PCI_CLASS_SYSTEM_RTC 0x0803 |
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96 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
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97 | #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
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98 | #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
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99 | |||
100 | #define PCI_BASE_CLASS_INPUT 0x09 |
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101 | #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
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102 | #define PCI_CLASS_INPUT_PEN 0x0901 |
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103 | #define PCI_CLASS_INPUT_MOUSE 0x0902 |
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104 | #define PCI_CLASS_INPUT_SCANNER 0x0903 |
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105 | #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
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106 | #define PCI_CLASS_INPUT_OTHER 0x0980 |
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107 | |||
108 | #define PCI_BASE_CLASS_DOCKING 0x0a |
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109 | #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
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110 | #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
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111 | |||
112 | #define PCI_BASE_CLASS_PROCESSOR 0x0b |
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113 | #define PCI_CLASS_PROCESSOR_386 0x0b00 |
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114 | #define PCI_CLASS_PROCESSOR_486 0x0b01 |
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115 | #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
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116 | #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
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117 | #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
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118 | #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
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119 | #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
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120 | |||
121 | #define PCI_BASE_CLASS_SERIAL 0x0c |
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122 | #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
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123 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
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124 | #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
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125 | #define PCI_CLASS_SERIAL_SSA 0x0c02 |
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126 | #define PCI_CLASS_SERIAL_USB 0x0c03 |
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127 | #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
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128 | #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
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129 | #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
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130 | #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
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131 | #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
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132 | |||
133 | #define PCI_BASE_CLASS_WIRELESS 0x0d |
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134 | #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
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135 | #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
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136 | |||
137 | #define PCI_BASE_CLASS_INTELLIGENT 0x0e |
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138 | #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
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139 | |||
140 | #define PCI_BASE_CLASS_SATELLITE 0x0f |
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141 | #define PCI_CLASS_SATELLITE_TV 0x0f00 |
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142 | #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
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143 | #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
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144 | #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
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145 | |||
146 | #define PCI_BASE_CLASS_CRYPT 0x10 |
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147 | #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
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148 | #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
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149 | #define PCI_CLASS_CRYPT_OTHER 0x1080 |
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150 | |||
151 | #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
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152 | #define PCI_CLASS_SP_DPIO 0x1100 |
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153 | #define PCI_CLASS_SP_OTHER 0x1180 |
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154 | |||
155 | #define PCI_CLASS_OTHERS 0xff |
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156 | |||
157 | |||
158 | |||
1964 | serge | 159 | |
160 | |||
1408 | serge | 161 | #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
162 | #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
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163 | |||
164 | #define PCI_MAP_IS64BITMEM(b) \ |
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165 | (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
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166 | |||
167 | #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
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168 | #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
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169 | #define PCIGETMEMORY64(b) \ |
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170 | (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
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171 | |||
172 | #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
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173 | |||
174 | #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
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175 | |||
176 | #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
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177 | #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
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178 | |||
179 | #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
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180 | |||
181 | |||
182 | #ifndef PCI_DOM_MASK |
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183 | # define PCI_DOM_MASK 0x0ffu |
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184 | #endif |
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185 | #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
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186 | |||
187 | #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
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188 | (((d) & 0x00001fu) << 11) | \ |
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189 | (((f) & 0x000007u) << 8)) |
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190 | |||
191 | #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
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192 | #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
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193 | #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
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194 | #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
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195 | |||
2161 | serge | 196 | /* |
197 | * The PCI interface treats multi-function devices as independent |
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198 | * devices. The slot/function address of each device is encoded |
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199 | * in a single byte as follows: |
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200 | * |
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201 | * 7:3 = slot |
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202 | * 2:0 = function |
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203 | */ |
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1408 | serge | 204 | #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
205 | #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
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206 | #define PCI_FUNC(devfn) ((devfn) & 0x07) |
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207 | |||
208 | |||
209 | |||
210 | typedef unsigned int PCITAG; |
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211 | |||
212 | extern inline PCITAG |
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213 | pciTag(int busnum, int devnum, int funcnum) |
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214 | { |
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215 | return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
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216 | } |
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217 | |||
2161 | serge | 218 | /* pci_slot represents a physical slot */ |
219 | struct pci_slot { |
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220 | struct pci_bus *bus; /* The bus this slot is on */ |
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221 | struct list_head list; /* node in list of slots on this bus */ |
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222 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
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223 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
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224 | }; |
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1627 | serge | 225 | |
2161 | serge | 226 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
227 | enum pci_mmap_state { |
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228 | pci_mmap_io, |
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229 | pci_mmap_mem |
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1964 | serge | 230 | }; |
231 | |||
2161 | serge | 232 | /* This defines the direction arg to the DMA mapping routines. */ |
233 | #define PCI_DMA_BIDIRECTIONAL 0 |
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234 | #define PCI_DMA_TODEVICE 1 |
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235 | #define PCI_DMA_FROMDEVICE 2 |
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236 | #define PCI_DMA_NONE 3 |
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237 | |||
1408 | serge | 238 | /* |
2161 | serge | 239 | * For PCI devices, the region numbers are assigned this way: |
1627 | serge | 240 | */ |
2161 | serge | 241 | enum { |
242 | /* #0-5: standard PCI resources */ |
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243 | PCI_STD_RESOURCES, |
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244 | PCI_STD_RESOURCE_END = 5, |
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1627 | serge | 245 | |
2161 | serge | 246 | /* #6: expansion ROM resource */ |
247 | PCI_ROM_RESOURCE, |
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1627 | serge | 248 | |
2161 | serge | 249 | /* device specific resources */ |
250 | #ifdef CONFIG_PCI_IOV |
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251 | PCI_IOV_RESOURCES, |
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252 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
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253 | #endif |
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1627 | serge | 254 | |
2161 | serge | 255 | /* resources assigned to buses behind the bridge */ |
256 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
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1627 | serge | 257 | |
2161 | serge | 258 | PCI_BRIDGE_RESOURCES, |
259 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
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260 | PCI_BRIDGE_RESOURCE_NUM - 1, |
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1627 | serge | 261 | |
2161 | serge | 262 | /* total resources associated with a PCI device */ |
263 | PCI_NUM_RESOURCES, |
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1627 | serge | 264 | |
2161 | serge | 265 | /* preserve this for compatibility */ |
3747 | Serge | 266 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
2161 | serge | 267 | }; |
1627 | serge | 268 | |
2161 | serge | 269 | typedef int __bitwise pci_power_t; |
1627 | serge | 270 | |
2161 | serge | 271 | #define PCI_D0 ((pci_power_t __force) 0) |
272 | #define PCI_D1 ((pci_power_t __force) 1) |
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273 | #define PCI_D2 ((pci_power_t __force) 2) |
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274 | #define PCI_D3hot ((pci_power_t __force) 3) |
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275 | #define PCI_D3cold ((pci_power_t __force) 4) |
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276 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
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277 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
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3031 | serge | 278 | |
279 | /* Remember to update this when the list above changes! */ |
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280 | extern const char *pci_power_names[]; |
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281 | |||
282 | static inline const char *pci_power_name(pci_power_t state) |
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283 | { |
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284 | return pci_power_names[1 + (int) state]; |
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285 | } |
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286 | |||
287 | #define PCI_PM_D2_DELAY 200 |
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288 | #define PCI_PM_D3_WAIT 10 |
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289 | #define PCI_PM_D3COLD_WAIT 100 |
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290 | #define PCI_PM_BUS_WAIT 50 |
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291 | |||
2161 | serge | 292 | /** The pci_channel state describes connectivity between the CPU and |
293 | * the pci device. If some PCI bus between here and the pci device |
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294 | * has crashed or locked up, this info is reflected here. |
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295 | */ |
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296 | typedef unsigned int __bitwise pci_channel_state_t; |
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1964 | serge | 297 | |
2161 | serge | 298 | enum pci_channel_state { |
299 | /* I/O channel is in normal state */ |
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300 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
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1964 | serge | 301 | |
2161 | serge | 302 | /* I/O to channel is blocked */ |
303 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
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1964 | serge | 304 | |
2161 | serge | 305 | /* PCI card is dead */ |
306 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
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307 | }; |
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308 | typedef unsigned short __bitwise pci_bus_flags_t; |
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309 | enum pci_bus_flags { |
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310 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
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311 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
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312 | }; |
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1964 | serge | 313 | |
2161 | serge | 314 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
315 | enum pci_bus_speed { |
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316 | PCI_SPEED_33MHz = 0x00, |
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317 | PCI_SPEED_66MHz = 0x01, |
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318 | PCI_SPEED_66MHz_PCIX = 0x02, |
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319 | PCI_SPEED_100MHz_PCIX = 0x03, |
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320 | PCI_SPEED_133MHz_PCIX = 0x04, |
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321 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, |
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322 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, |
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323 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, |
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324 | PCI_SPEED_66MHz_PCIX_266 = 0x09, |
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325 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, |
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326 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, |
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327 | AGP_UNKNOWN = 0x0c, |
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328 | AGP_1X = 0x0d, |
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329 | AGP_2X = 0x0e, |
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330 | AGP_4X = 0x0f, |
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331 | AGP_8X = 0x10, |
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332 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
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333 | PCI_SPEED_100MHz_PCIX_533 = 0x12, |
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334 | PCI_SPEED_133MHz_PCIX_533 = 0x13, |
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335 | PCIE_SPEED_2_5GT = 0x14, |
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336 | PCIE_SPEED_5_0GT = 0x15, |
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337 | PCIE_SPEED_8_0GT = 0x16, |
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338 | PCI_SPEED_UNKNOWN = 0xff, |
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339 | }; |
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1408 | serge | 340 | |
341 | /* |
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342 | * The pci_dev structure is used to describe PCI devices. |
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343 | */ |
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344 | struct pci_dev { |
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2161 | serge | 345 | struct list_head bus_list; /* node in per-bus list */ |
346 | struct pci_bus *bus; /* bus this device is on */ |
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347 | struct pci_bus *subordinate; /* bus this device bridges to */ |
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1408 | serge | 348 | |
2161 | serge | 349 | void *sysdata; /* hook for sys-specific extension */ |
1408 | serge | 350 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
2161 | serge | 351 | struct pci_slot *slot; /* Physical slot this device is in */ |
352 | u32_t busnr; |
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353 | unsigned int devfn; /* encoded device & function index */ |
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354 | unsigned short vendor; |
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355 | unsigned short device; |
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356 | unsigned short subsystem_vendor; |
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357 | unsigned short subsystem_device; |
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358 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
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359 | u8 revision; /* PCI revision, low byte of class word */ |
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360 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
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361 | u8 pcie_cap; /* PCI-E capability offset */ |
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3031 | serge | 362 | u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ |
2161 | serge | 363 | u8 rom_base_reg; /* which config register controls the ROM */ |
364 | u8 pin; /* which interrupt pin this device uses */ |
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3031 | serge | 365 | u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ |
1408 | serge | 366 | |
367 | // struct pci_driver *driver; /* which driver has allocated this device */ |
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1964 | serge | 368 | uint64_t dma_mask; /* Mask of the bits of bus address this |
1408 | serge | 369 | device implements. Normally this is |
370 | 0xffffffff. You only need to change |
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371 | this if your device has broken DMA |
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372 | or supports 64-bit transfers. */ |
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373 | |||
374 | // struct device_dma_parameters dma_parms; |
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375 | |||
2161 | serge | 376 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
377 | this is D0-D3, D0 being fully functional, |
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378 | and D3 being off. */ |
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3747 | Serge | 379 | u8 pm_cap; /* PM capability offset */ |
1408 | serge | 380 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
381 | can be generated */ |
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2161 | serge | 382 | unsigned int pme_interrupt:1; |
3031 | serge | 383 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
1408 | serge | 384 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
385 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
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3031 | serge | 386 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
387 | unsigned int no_d3cold:1; /* D3cold is forbidden */ |
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388 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
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2161 | serge | 389 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
390 | decoding during bar sizing */ |
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391 | unsigned int wakeup_prepared:1; |
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3031 | serge | 392 | unsigned int runtime_d3cold:1; /* whether go through runtime |
393 | D3cold, not set for devices |
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394 | powered on/off by the |
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395 | corresponding bridge */ |
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2161 | serge | 396 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
3031 | serge | 397 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
1408 | serge | 398 | |
3031 | serge | 399 | #ifdef CONFIG_PCIEASPM |
400 | struct pcie_link_state *link_state; /* ASPM link state. */ |
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401 | #endif |
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2161 | serge | 402 | |
403 | pci_channel_state_t error_state; /* current connectivity state */ |
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1430 | serge | 404 | struct device dev; /* Generic device interface */ |
3747 | Serge | 405 | |
2161 | serge | 406 | int cfg_size; /* Size of configuration space */ |
1408 | serge | 407 | |
408 | /* |
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409 | * Instead of touching interrupt line and base address registers |
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410 | * directly, use the values stored here. They might be different! |
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411 | */ |
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412 | unsigned int irq; |
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413 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
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414 | |||
415 | /* These fields are used by common fixups */ |
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416 | unsigned int transparent:1; /* Transparent PCI bridge */ |
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417 | unsigned int multifunction:1;/* Part of multi-function device */ |
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418 | /* keep track of device state */ |
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419 | unsigned int is_added:1; |
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420 | unsigned int is_busmaster:1; /* device is busmaster */ |
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421 | unsigned int no_msi:1; /* device may not use msi */ |
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3031 | serge | 422 | unsigned int block_cfg_access:1; /* config space access is blocked */ |
1408 | serge | 423 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
424 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
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425 | unsigned int msi_enabled:1; |
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426 | unsigned int msix_enabled:1; |
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2161 | serge | 427 | unsigned int ari_enabled:1; /* ARI forwarding */ |
1408 | serge | 428 | unsigned int is_managed:1; |
2161 | serge | 429 | unsigned int is_pcie:1; /* Obsolete. Will be removed. |
430 | Use pci_is_pcie() instead */ |
||
431 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
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1408 | serge | 432 | unsigned int state_saved:1; |
433 | unsigned int is_physfn:1; |
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434 | unsigned int is_virtfn:1; |
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2161 | serge | 435 | unsigned int reset_fn:1; |
436 | unsigned int is_hotplug_bridge:1; |
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3031 | serge | 437 | unsigned int __aer_firmware_first_valid:1; |
438 | unsigned int __aer_firmware_first:1; |
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439 | unsigned int broken_intx_masking:1; |
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440 | unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
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441 | // pci_dev_flags_t dev_flags; |
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442 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
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1408 | serge | 443 | |
3031 | serge | 444 | |
445 | |||
1408 | serge | 446 | }; |
447 | |||
448 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
||
449 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
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450 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
||
451 | #define pci_resource_len(dev,bar) \ |
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452 | ((pci_resource_start((dev), (bar)) == 0 && \ |
||
453 | pci_resource_end((dev), (bar)) == \ |
||
454 | pci_resource_start((dev), (bar))) ? 0 : \ |
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455 | \ |
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456 | (pci_resource_end((dev), (bar)) - \ |
||
457 | pci_resource_start((dev), (bar)) + 1)) |
||
458 | |||
459 | |||
2161 | serge | 460 | struct pci_bus { |
461 | struct list_head node; /* node in list of buses */ |
||
462 | struct pci_bus *parent; /* parent bus this bridge is on */ |
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463 | struct list_head children; /* list of child buses */ |
||
464 | struct list_head devices; /* list of devices on this bus */ |
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465 | struct pci_dev *self; /* bridge device as seen by parent */ |
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466 | struct list_head slots; /* list of slots on this bus */ |
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467 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
||
468 | struct list_head resources; /* address space routed to this bus */ |
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3031 | serge | 469 | struct resource busn_res; /* bus numbers routed to this bus */ |
1964 | serge | 470 | |
2161 | serge | 471 | struct pci_ops *ops; /* configuration access functions */ |
472 | void *sysdata; /* hook for sys-specific extension */ |
||
473 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
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1964 | serge | 474 | |
2161 | serge | 475 | unsigned char number; /* bus number */ |
476 | unsigned char primary; /* number of primary bridge */ |
||
477 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
||
478 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
||
479 | |||
480 | char name[48]; |
||
481 | |||
482 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ |
||
483 | pci_bus_flags_t bus_flags; /* Inherited by child busses */ |
||
484 | struct device *bridge; |
||
485 | struct device dev; |
||
486 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
||
487 | struct bin_attribute *legacy_mem; /* legacy mem */ |
||
488 | unsigned int is_added:1; |
||
489 | }; |
||
490 | |||
491 | |||
492 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
||
493 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
||
494 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
||
495 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
||
496 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
||
497 | |||
498 | |||
499 | /* Low-level architecture-dependent routines */ |
||
500 | |||
501 | struct pci_sysdata { |
||
502 | int domain; /* PCI domain */ |
||
503 | int node; /* NUMA node */ |
||
504 | }; |
||
505 | |||
506 | |||
507 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
||
508 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
||
509 | |||
510 | /* |
||
511 | * Returns true if the pci bus is root (behind host-pci bridge), |
||
512 | * false otherwise |
||
513 | */ |
||
514 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
||
515 | { |
||
516 | return !(pbus->parent); |
||
517 | } |
||
518 | |||
519 | struct pci_bus * |
||
520 | pci_find_next_bus(const struct pci_bus *from); |
||
521 | |||
522 | |||
523 | /* |
||
524 | * Error values that may be returned by PCI functions. |
||
525 | */ |
||
526 | #define PCIBIOS_SUCCESSFUL 0x00 |
||
527 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
||
528 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
||
529 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
||
530 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
||
531 | #define PCIBIOS_SET_FAILED 0x88 |
||
532 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
||
533 | |||
534 | /* Low-level architecture-dependent routines */ |
||
535 | |||
536 | struct pci_ops { |
||
537 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
||
538 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
||
539 | }; |
||
540 | |||
541 | |||
542 | enum pci_bar_type { |
||
543 | pci_bar_unknown, /* Standard PCI BAR probe */ |
||
544 | pci_bar_io, /* An io port BAR */ |
||
545 | pci_bar_mem32, /* A 32-bit memory BAR */ |
||
546 | pci_bar_mem64, /* A 64-bit memory BAR */ |
||
547 | }; |
||
548 | |||
549 | /* |
||
550 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), |
||
551 | * a PCI domain is defined to be a set of PCI busses which share |
||
552 | * configuration space. |
||
553 | */ |
||
554 | #ifdef CONFIG_PCI_DOMAINS |
||
555 | extern int pci_domains_supported; |
||
556 | #else |
||
557 | enum { pci_domains_supported = 0 }; |
||
558 | static inline int pci_domain_nr(struct pci_bus *bus) |
||
559 | { |
||
560 | return 0; |
||
561 | } |
||
562 | |||
563 | static inline int pci_proc_domain(struct pci_bus *bus) |
||
564 | { |
||
565 | return 0; |
||
566 | } |
||
567 | #endif /* CONFIG_PCI_DOMAINS */ |
||
568 | |||
569 | /** |
||
570 | * pci_pcie_cap - get the saved PCIe capability offset |
||
571 | * @dev: PCI device |
||
572 | * |
||
573 | * PCIe capability offset is calculated at PCI device initialization |
||
574 | * time and saved in the data structure. This function returns saved |
||
575 | * PCIe capability offset. Using this instead of pci_find_capability() |
||
576 | * reduces unnecessary search in the PCI configuration space. If you |
||
577 | * need to calculate PCIe capability offset from raw device for some |
||
578 | * reasons, please use pci_find_capability() instead. |
||
579 | */ |
||
580 | static inline int pci_pcie_cap(struct pci_dev *dev) |
||
581 | { |
||
582 | return dev->pcie_cap; |
||
583 | } |
||
584 | |||
585 | /** |
||
586 | * pci_is_pcie - check if the PCI device is PCI Express capable |
||
587 | * @dev: PCI device |
||
588 | * |
||
589 | * Retrun true if the PCI device is PCI Express capable, false otherwise. |
||
590 | */ |
||
591 | static inline bool pci_is_pcie(struct pci_dev *dev) |
||
592 | { |
||
593 | return !!pci_pcie_cap(dev); |
||
594 | } |
||
595 | |||
3031 | serge | 596 | /** |
597 | * pci_pcie_type - get the PCIe device/port type |
||
598 | * @dev: PCI device |
||
599 | */ |
||
600 | static inline int pci_pcie_type(const struct pci_dev *dev) |
||
601 | { |
||
602 | return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; |
||
603 | } |
||
604 | |||
605 | |||
2161 | serge | 606 | static inline int pci_iov_init(struct pci_dev *dev) |
607 | { |
||
608 | return -ENODEV; |
||
609 | } |
||
610 | static inline void pci_iov_release(struct pci_dev *dev) |
||
611 | |||
612 | {} |
||
613 | |||
614 | static inline int pci_iov_resource_bar(struct pci_dev *dev, int resno, |
||
615 | enum pci_bar_type *type) |
||
616 | { |
||
617 | return 0; |
||
618 | } |
||
619 | static inline void pci_restore_iov_state(struct pci_dev *dev) |
||
620 | { |
||
621 | } |
||
622 | static inline int pci_iov_bus_range(struct pci_bus *bus) |
||
623 | { |
||
624 | return 0; |
||
625 | } |
||
626 | |||
627 | static inline int pci_enable_ats(struct pci_dev *dev, int ps) |
||
628 | { |
||
629 | return -ENODEV; |
||
630 | } |
||
631 | static inline void pci_disable_ats(struct pci_dev *dev) |
||
632 | { |
||
633 | } |
||
634 | static inline int pci_ats_queue_depth(struct pci_dev *dev) |
||
635 | { |
||
636 | return -ENODEV; |
||
637 | } |
||
638 | static inline int pci_ats_enabled(struct pci_dev *dev) |
||
639 | { |
||
640 | return 0; |
||
641 | } |
||
642 | |||
643 | int pci_setup_device(struct pci_dev *dev); |
||
644 | int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, |
||
645 | struct resource *res, unsigned int reg); |
||
646 | int pci_resource_bar(struct pci_dev *dev, int resno, |
||
647 | enum pci_bar_type *type); |
||
648 | int pci_bus_add_child(struct pci_bus *bus); |
||
649 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
||
650 | |||
651 | |||
1408 | serge | 652 | typedef struct |
653 | { |
||
654 | struct list_head link; |
||
655 | struct pci_dev pci_dev; |
||
656 | }pci_dev_t; |
||
657 | |||
658 | int enum_pci_devices(void); |
||
659 | |||
2967 | Serge | 660 | const struct pci_device_id* |
661 | find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist); |
||
1408 | serge | 662 | |
663 | #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) |
||
664 | |||
3391 | Serge | 665 | #define pci_set_dma_mask(a, b) 0 |
666 | #define pci_set_consistent_dma_mask(a, b) |
||
1408 | serge | 667 | |
2967 | Serge | 668 | struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); |
669 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
||
1408 | serge | 670 | |
2967 | Serge | 671 | void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size); |
672 | |||
1964 | serge | 673 | #define pci_name(x) "radeon" |
1631 | serge | 674 | |
1408 | serge | 675 | #endif //__PCI__H__(n))-1)) |
676 | |||
677 |