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Rev | Author | Line No. | Line |
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1964 | serge | 1 | /* |
2 | * pci.h |
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3 | * |
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4 | * PCI defines and function prototypes |
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5 | * Copyright 1994, Drew Eckhardt |
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6 | * Copyright 1997--1999 Martin Mares |
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7 | * |
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8 | * For more information, please consult the following manuals (look at |
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9 | * http://www.pcisig.com/ for how to get them): |
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10 | * |
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11 | * PCI BIOS Specification |
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12 | * PCI Local Bus Specification |
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13 | * PCI to PCI Bridge Specification |
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14 | * PCI System Design Guide |
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15 | */ |
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1970 | serge | 16 | #ifndef LINUX_PCI_H |
17 | #define LINUX_PCI_H |
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18 | |||
6102 | serge | 19 | |
20 | #include |
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21 | |||
3031 | serge | 22 | #include |
6102 | serge | 23 | #include |
24 | #include |
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5270 | serge | 25 | #include |
26 | #include |
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27 | #include |
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6102 | serge | 28 | #include |
5270 | serge | 29 | #include |
6082 | serge | 30 | #include |
6102 | serge | 31 | #include |
32 | #include |
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33 | #include |
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1628 | serge | 34 | |
6102 | serge | 35 | #include |
36 | #include |
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9493 | turbocat | 37 | |
38 | #ifdef HAVE_ACPICA |
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39 | #include |
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40 | #endif |
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41 | |||
2161 | serge | 42 | /* |
43 | * The PCI interface treats multi-function devices as independent |
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44 | * devices. The slot/function address of each device is encoded |
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45 | * in a single byte as follows: |
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46 | * |
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47 | * 7:3 = slot |
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48 | * 2:0 = function |
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6082 | serge | 49 | * |
50 | * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h. |
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51 | * In the interest of not exposing interfaces to user-space unnecessarily, |
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52 | * the following kernel-only defines are being added here. |
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2161 | serge | 53 | */ |
6102 | serge | 54 | #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) |
55 | /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ |
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56 | #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) |
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1408 | serge | 57 | |
9493 | turbocat | 58 | #define PCI_CFG_SPACE_SIZE 256 |
59 | #define PCI_CFG_SPACE_EXP_SIZE 4096 |
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60 | |||
61 | enum pci_bar_type { |
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62 | pci_bar_unknown, /* Standard PCI BAR probe */ |
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63 | pci_bar_io, /* An io port BAR */ |
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64 | pci_bar_mem32, /* A 32-bit memory BAR */ |
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65 | pci_bar_mem64, /* A 64-bit memory BAR */ |
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66 | }; |
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67 | |||
2161 | serge | 68 | /* pci_slot represents a physical slot */ |
69 | struct pci_slot { |
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70 | struct pci_bus *bus; /* The bus this slot is on */ |
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71 | struct list_head list; /* node in list of slots on this bus */ |
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72 | struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ |
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73 | unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ |
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6102 | serge | 74 | struct kobject kobj; |
2161 | serge | 75 | }; |
1627 | serge | 76 | |
6934 | serge | 77 | static inline const char *pci_slot_name(const struct pci_slot *slot) |
78 | { |
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79 | return kobject_name(&slot->kobj); |
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80 | } |
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81 | |||
2161 | serge | 82 | /* File state for mmap()s on /proc/bus/pci/X/Y */ |
83 | enum pci_mmap_state { |
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84 | pci_mmap_io, |
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85 | pci_mmap_mem |
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1964 | serge | 86 | }; |
87 | |||
2161 | serge | 88 | /* This defines the direction arg to the DMA mapping routines. */ |
89 | #define PCI_DMA_BIDIRECTIONAL 0 |
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90 | #define PCI_DMA_TODEVICE 1 |
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91 | #define PCI_DMA_FROMDEVICE 2 |
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92 | #define PCI_DMA_NONE 3 |
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93 | |||
1408 | serge | 94 | /* |
2161 | serge | 95 | * For PCI devices, the region numbers are assigned this way: |
1627 | serge | 96 | */ |
2161 | serge | 97 | enum { |
6102 | serge | 98 | /* #0-5: standard PCI resources */ |
99 | PCI_STD_RESOURCES, |
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100 | PCI_STD_RESOURCE_END = 5, |
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1627 | serge | 101 | |
6102 | serge | 102 | /* #6: expansion ROM resource */ |
103 | PCI_ROM_RESOURCE, |
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1627 | serge | 104 | |
6102 | serge | 105 | /* device specific resources */ |
2161 | serge | 106 | #ifdef CONFIG_PCI_IOV |
6102 | serge | 107 | PCI_IOV_RESOURCES, |
108 | PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, |
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2161 | serge | 109 | #endif |
1627 | serge | 110 | |
6102 | serge | 111 | /* resources assigned to buses behind the bridge */ |
2161 | serge | 112 | #define PCI_BRIDGE_RESOURCE_NUM 4 |
1627 | serge | 113 | |
6102 | serge | 114 | PCI_BRIDGE_RESOURCES, |
115 | PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + |
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116 | PCI_BRIDGE_RESOURCE_NUM - 1, |
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1627 | serge | 117 | |
6102 | serge | 118 | /* total resources associated with a PCI device */ |
119 | PCI_NUM_RESOURCES, |
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1627 | serge | 120 | |
6102 | serge | 121 | /* preserve this for compatibility */ |
3747 | Serge | 122 | DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, |
2161 | serge | 123 | }; |
1627 | serge | 124 | |
2161 | serge | 125 | typedef int __bitwise pci_power_t; |
1627 | serge | 126 | |
2161 | serge | 127 | #define PCI_D0 ((pci_power_t __force) 0) |
128 | #define PCI_D1 ((pci_power_t __force) 1) |
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129 | #define PCI_D2 ((pci_power_t __force) 2) |
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130 | #define PCI_D3hot ((pci_power_t __force) 3) |
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131 | #define PCI_D3cold ((pci_power_t __force) 4) |
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132 | #define PCI_UNKNOWN ((pci_power_t __force) 5) |
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133 | #define PCI_POWER_ERROR ((pci_power_t __force) -1) |
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3031 | serge | 134 | |
135 | /* Remember to update this when the list above changes! */ |
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136 | extern const char *pci_power_names[]; |
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137 | |||
138 | static inline const char *pci_power_name(pci_power_t state) |
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139 | { |
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140 | return pci_power_names[1 + (int) state]; |
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141 | } |
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142 | |||
143 | #define PCI_PM_D2_DELAY 200 |
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144 | #define PCI_PM_D3_WAIT 10 |
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145 | #define PCI_PM_D3COLD_WAIT 100 |
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146 | #define PCI_PM_BUS_WAIT 50 |
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147 | |||
2161 | serge | 148 | /** The pci_channel state describes connectivity between the CPU and |
149 | * the pci device. If some PCI bus between here and the pci device |
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150 | * has crashed or locked up, this info is reflected here. |
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151 | */ |
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152 | typedef unsigned int __bitwise pci_channel_state_t; |
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1964 | serge | 153 | |
2161 | serge | 154 | enum pci_channel_state { |
155 | /* I/O channel is in normal state */ |
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156 | pci_channel_io_normal = (__force pci_channel_state_t) 1, |
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1964 | serge | 157 | |
2161 | serge | 158 | /* I/O to channel is blocked */ |
159 | pci_channel_io_frozen = (__force pci_channel_state_t) 2, |
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1964 | serge | 160 | |
2161 | serge | 161 | /* PCI card is dead */ |
162 | pci_channel_io_perm_failure = (__force pci_channel_state_t) 3, |
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163 | }; |
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6102 | serge | 164 | |
165 | typedef unsigned int __bitwise pcie_reset_state_t; |
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166 | |||
167 | enum pcie_reset_state { |
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168 | /* Reset is NOT asserted (Use to deassert reset) */ |
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169 | pcie_deassert_reset = (__force pcie_reset_state_t) 1, |
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170 | |||
171 | /* Use #PERST to reset PCIe device */ |
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172 | pcie_warm_reset = (__force pcie_reset_state_t) 2, |
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173 | |||
174 | /* Use PCIe Hot Reset to reset device */ |
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175 | pcie_hot_reset = (__force pcie_reset_state_t) 3 |
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176 | }; |
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177 | |||
178 | typedef unsigned short __bitwise pci_dev_flags_t; |
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179 | enum pci_dev_flags { |
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180 | /* INTX_DISABLE in PCI_COMMAND register disables MSI |
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181 | * generation too. |
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182 | */ |
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183 | PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), |
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184 | /* Device configuration is irrevocably lost if disabled into D3 */ |
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185 | PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), |
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186 | /* Provide indication device is assigned by a Virtual Machine Manager */ |
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187 | PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2), |
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188 | /* Flag for quirk use to store if quirk-specific ACS is enabled */ |
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189 | PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3), |
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190 | /* Flag to indicate the device uses dma_alias_devfn */ |
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191 | PCI_DEV_FLAGS_DMA_ALIAS_DEVFN = (__force pci_dev_flags_t) (1 << 4), |
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192 | /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */ |
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193 | PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5), |
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194 | /* Do not use bus resets for device */ |
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195 | PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6), |
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196 | /* Do not use PM reset even if device advertises NoSoftRst- */ |
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197 | PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), |
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198 | /* Get VPD from function 0 VPD */ |
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199 | PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), |
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200 | }; |
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201 | |||
202 | enum pci_irq_reroute_variant { |
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203 | INTEL_IRQ_REROUTE_VARIANT = 1, |
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204 | MAX_IRQ_REROUTE_VARIANTS = 3 |
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205 | }; |
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206 | |||
2161 | serge | 207 | typedef unsigned short __bitwise pci_bus_flags_t; |
208 | enum pci_bus_flags { |
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6102 | serge | 209 | PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1, |
210 | PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2, |
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2161 | serge | 211 | }; |
1964 | serge | 212 | |
5270 | serge | 213 | /* These values come from the PCI Express Spec */ |
214 | enum pcie_link_width { |
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215 | PCIE_LNK_WIDTH_RESRV = 0x00, |
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216 | PCIE_LNK_X1 = 0x01, |
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217 | PCIE_LNK_X2 = 0x02, |
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218 | PCIE_LNK_X4 = 0x04, |
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219 | PCIE_LNK_X8 = 0x08, |
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220 | PCIE_LNK_X12 = 0x0C, |
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221 | PCIE_LNK_X16 = 0x10, |
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222 | PCIE_LNK_X32 = 0x20, |
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223 | PCIE_LNK_WIDTH_UNKNOWN = 0xFF, |
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224 | }; |
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225 | |||
2161 | serge | 226 | /* Based on the PCI Hotplug Spec, but some values are made up by us */ |
227 | enum pci_bus_speed { |
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228 | PCI_SPEED_33MHz = 0x00, |
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229 | PCI_SPEED_66MHz = 0x01, |
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230 | PCI_SPEED_66MHz_PCIX = 0x02, |
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231 | PCI_SPEED_100MHz_PCIX = 0x03, |
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232 | PCI_SPEED_133MHz_PCIX = 0x04, |
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233 | PCI_SPEED_66MHz_PCIX_ECC = 0x05, |
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234 | PCI_SPEED_100MHz_PCIX_ECC = 0x06, |
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235 | PCI_SPEED_133MHz_PCIX_ECC = 0x07, |
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236 | PCI_SPEED_66MHz_PCIX_266 = 0x09, |
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237 | PCI_SPEED_100MHz_PCIX_266 = 0x0a, |
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238 | PCI_SPEED_133MHz_PCIX_266 = 0x0b, |
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239 | AGP_UNKNOWN = 0x0c, |
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240 | AGP_1X = 0x0d, |
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241 | AGP_2X = 0x0e, |
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242 | AGP_4X = 0x0f, |
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243 | AGP_8X = 0x10, |
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244 | PCI_SPEED_66MHz_PCIX_533 = 0x11, |
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245 | PCI_SPEED_100MHz_PCIX_533 = 0x12, |
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246 | PCI_SPEED_133MHz_PCIX_533 = 0x13, |
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247 | PCIE_SPEED_2_5GT = 0x14, |
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248 | PCIE_SPEED_5_0GT = 0x15, |
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249 | PCIE_SPEED_8_0GT = 0x16, |
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250 | PCI_SPEED_UNKNOWN = 0xff, |
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251 | }; |
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1408 | serge | 252 | |
5270 | serge | 253 | struct pci_cap_saved_data { |
254 | u16 cap_nr; |
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255 | bool cap_extended; |
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256 | unsigned int size; |
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257 | u32 data[0]; |
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258 | }; |
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259 | |||
260 | struct pci_cap_saved_state { |
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261 | struct hlist_node next; |
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262 | struct pci_cap_saved_data cap; |
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263 | }; |
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264 | |||
265 | struct pcie_link_state; |
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266 | struct pci_vpd; |
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267 | struct pci_sriov; |
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268 | struct pci_ats; |
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269 | |||
1408 | serge | 270 | /* |
271 | * The pci_dev structure is used to describe PCI devices. |
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272 | */ |
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273 | struct pci_dev { |
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6102 | serge | 274 | struct list_head bus_list; /* node in per-bus list */ |
275 | struct pci_bus *bus; /* bus this device is on */ |
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276 | struct pci_bus *subordinate; /* bus this device bridges to */ |
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1408 | serge | 277 | |
2161 | serge | 278 | void *sysdata; /* hook for sys-specific extension */ |
1408 | serge | 279 | // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
2161 | serge | 280 | struct pci_slot *slot; /* Physical slot this device is in */ |
5270 | serge | 281 | u32 busnr; |
2161 | serge | 282 | unsigned int devfn; /* encoded device & function index */ |
283 | unsigned short vendor; |
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284 | unsigned short device; |
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285 | unsigned short subsystem_vendor; |
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286 | unsigned short subsystem_device; |
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287 | unsigned int class; /* 3 bytes: (base,sub,prog-if) */ |
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288 | u8 revision; /* PCI revision, low byte of class word */ |
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289 | u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
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6102 | serge | 290 | u8 pcie_cap; /* PCIe capability offset */ |
291 | u8 msi_cap; /* MSI capability offset */ |
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292 | u8 msix_cap; /* MSI-X capability offset */ |
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293 | u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ |
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2161 | serge | 294 | u8 rom_base_reg; /* which config register controls the ROM */ |
6102 | serge | 295 | u8 pin; /* which interrupt pin this device uses */ |
296 | u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ |
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9493 | turbocat | 297 | int pcie_type; |
6102 | serge | 298 | u8 dma_alias_devfn;/* devfn of DMA alias, if any */ |
1408 | serge | 299 | |
6102 | serge | 300 | u64 dma_mask; /* Mask of the bits of bus address this |
301 | device implements. Normally this is |
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302 | 0xffffffff. You only need to change |
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303 | this if your device has broken DMA |
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304 | or supports 64-bit transfers. */ |
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1408 | serge | 305 | |
306 | |||
2161 | serge | 307 | pci_power_t current_state; /* Current operating state. In ACPI-speak, |
308 | this is D0-D3, D0 being fully functional, |
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309 | and D3 being off. */ |
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3747 | Serge | 310 | u8 pm_cap; /* PM capability offset */ |
6102 | serge | 311 | unsigned int pme_support:5; /* Bitmask of states from which PME# |
312 | can be generated */ |
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2161 | serge | 313 | unsigned int pme_interrupt:1; |
3031 | serge | 314 | unsigned int pme_poll:1; /* Poll device's PME status bit */ |
6102 | serge | 315 | unsigned int d1_support:1; /* Low power state D1 is supported */ |
316 | unsigned int d2_support:1; /* Low power state D2 is supported */ |
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3031 | serge | 317 | unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
318 | unsigned int no_d3cold:1; /* D3cold is forbidden */ |
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319 | unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
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2161 | serge | 320 | unsigned int mmio_always_on:1; /* disallow turning off io/mem |
321 | decoding during bar sizing */ |
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322 | unsigned int wakeup_prepared:1; |
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3031 | serge | 323 | unsigned int runtime_d3cold:1; /* whether go through runtime |
324 | D3cold, not set for devices |
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325 | powered on/off by the |
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326 | corresponding bridge */ |
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6082 | serge | 327 | unsigned int ignore_hotplug:1; /* Ignore hotplug events */ |
2161 | serge | 328 | unsigned int d3_delay; /* D3->D0 transition time in ms */ |
3031 | serge | 329 | unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
1408 | serge | 330 | |
3031 | serge | 331 | #ifdef CONFIG_PCIEASPM |
6082 | serge | 332 | struct pcie_link_state *link_state; /* ASPM link state */ |
3031 | serge | 333 | #endif |
2161 | serge | 334 | |
335 | pci_channel_state_t error_state; /* current connectivity state */ |
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6102 | serge | 336 | struct device dev; /* Generic device interface */ |
3747 | Serge | 337 | |
6102 | serge | 338 | int cfg_size; /* Size of configuration space */ |
1408 | serge | 339 | |
6102 | serge | 340 | /* |
341 | * Instead of touching interrupt line and base address registers |
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342 | * directly, use the values stored here. They might be different! |
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343 | */ |
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344 | unsigned int irq; |
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345 | struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
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1408 | serge | 346 | |
6082 | serge | 347 | bool match_driver; /* Skip attaching driver */ |
6102 | serge | 348 | /* These fields are used by common fixups */ |
6082 | serge | 349 | unsigned int transparent:1; /* Subtractive decode PCI bridge */ |
6102 | serge | 350 | unsigned int multifunction:1;/* Part of multi-function device */ |
351 | /* keep track of device state */ |
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352 | unsigned int is_added:1; |
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353 | unsigned int is_busmaster:1; /* device is busmaster */ |
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354 | unsigned int no_msi:1; /* device may not use msi */ |
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6082 | serge | 355 | unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ |
3031 | serge | 356 | unsigned int block_cfg_access:1; /* config space access is blocked */ |
6102 | serge | 357 | unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
358 | unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
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359 | unsigned int msi_enabled:1; |
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360 | unsigned int msix_enabled:1; |
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2161 | serge | 361 | unsigned int ari_enabled:1; /* ARI forwarding */ |
6102 | serge | 362 | unsigned int ats_enabled:1; /* Address Translation Service */ |
363 | unsigned int is_managed:1; |
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2161 | serge | 364 | unsigned int needs_freset:1; /* Dev requires fundamental reset */ |
6102 | serge | 365 | unsigned int state_saved:1; |
366 | unsigned int is_physfn:1; |
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367 | unsigned int is_virtfn:1; |
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2161 | serge | 368 | unsigned int reset_fn:1; |
369 | unsigned int is_hotplug_bridge:1; |
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3031 | serge | 370 | unsigned int __aer_firmware_first_valid:1; |
371 | unsigned int __aer_firmware_first:1; |
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372 | unsigned int broken_intx_masking:1; |
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373 | unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
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6102 | serge | 374 | unsigned int irq_managed:1; |
375 | unsigned int has_secondary_link:1; |
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6934 | serge | 376 | unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ |
6102 | serge | 377 | pci_dev_flags_t dev_flags; |
3031 | serge | 378 | atomic_t enable_cnt; /* pci_enable_device has been called */ |
1408 | serge | 379 | |
6102 | serge | 380 | u32 saved_config_space[16]; /* config space saved at suspend time */ |
381 | struct hlist_head saved_cap_space; |
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382 | struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
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383 | int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
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384 | #ifdef CONFIG_PCI_MSI |
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385 | const struct attribute_group **msi_irq_groups; |
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386 | #endif |
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387 | #ifdef CONFIG_PCI_ATS |
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388 | union { |
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389 | struct pci_sriov *sriov; /* SR-IOV capability related */ |
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390 | struct pci_dev *physfn; /* the PF this VF is associated with */ |
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391 | }; |
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392 | u16 ats_cap; /* ATS Capability offset */ |
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393 | u8 ats_stu; /* ATS Smallest Translation Unit */ |
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394 | atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ |
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395 | #endif |
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396 | phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ |
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397 | size_t romlen; /* Length of ROM if it's not from the BAR */ |
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398 | char *driver_override; /* Driver name to force a match */ |
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9493 | turbocat | 399 | #ifdef HAVE_ACPICA |
400 | struct acpi_device *acpi_dev; |
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401 | #endif |
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6102 | serge | 402 | }; |
3031 | serge | 403 | |
6102 | serge | 404 | static inline struct pci_dev *pci_physfn(struct pci_dev *dev) |
405 | { |
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406 | #ifdef CONFIG_PCI_IOV |
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407 | if (dev->is_virtfn) |
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408 | dev = dev->physfn; |
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409 | #endif |
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410 | return dev; |
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411 | } |
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3031 | serge | 412 | |
6102 | serge | 413 | struct pci_dev *pci_alloc_dev(struct pci_bus *bus); |
414 | |||
415 | #define to_pci_dev(n) container_of(n, struct pci_dev, dev) |
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416 | #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL) |
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417 | |||
418 | static inline int pci_channel_offline(struct pci_dev *pdev) |
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419 | { |
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420 | return (pdev->error_state != pci_channel_io_normal); |
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421 | } |
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422 | |||
423 | struct pci_host_bridge { |
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424 | struct device dev; |
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425 | struct pci_bus *bus; /* root bus */ |
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426 | struct list_head windows; /* resource_entry */ |
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427 | void (*release_fn)(struct pci_host_bridge *); |
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428 | void *release_data; |
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429 | unsigned int ignore_reset_delay:1; /* for entire hierarchy */ |
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430 | /* Resource alignment requirements */ |
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431 | resource_size_t (*align_resource)(struct pci_dev *dev, |
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432 | const struct resource *res, |
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433 | resource_size_t start, |
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434 | resource_size_t size, |
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435 | resource_size_t align); |
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1408 | serge | 436 | }; |
437 | |||
6102 | serge | 438 | #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) |
1408 | serge | 439 | |
6102 | serge | 440 | struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); |
1408 | serge | 441 | |
6102 | serge | 442 | void pci_set_host_bridge_release(struct pci_host_bridge *bridge, |
443 | void (*release_fn)(struct pci_host_bridge *), |
||
444 | void *release_data); |
||
1964 | serge | 445 | |
6102 | serge | 446 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); |
1964 | serge | 447 | |
6102 | serge | 448 | /* |
449 | * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond |
||
450 | * to P2P or CardBus bridge windows) go in a table. Additional ones (for |
||
451 | * buses below host bridges or subtractive decode bridges) go in the list. |
||
452 | * Use pci_bus_for_each_resource() to iterate through all the resources. |
||
453 | */ |
||
2161 | serge | 454 | |
6102 | serge | 455 | /* |
456 | * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly |
||
457 | * and there's no way to program the bridge with the details of the window. |
||
458 | * This does not apply to ACPI _CRS windows, even with the _DEC subtractive- |
||
459 | * decode bit set, because they are explicit and can be programmed with _SRS. |
||
460 | */ |
||
461 | #define PCI_SUBTRACTIVE_DECODE 0x1 |
||
2161 | serge | 462 | |
6102 | serge | 463 | struct pci_bus_resource { |
464 | struct list_head list; |
||
465 | struct resource *res; |
||
466 | unsigned int flags; |
||
2161 | serge | 467 | }; |
468 | |||
6102 | serge | 469 | #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ |
2161 | serge | 470 | |
6102 | serge | 471 | struct pci_bus { |
472 | struct list_head node; /* node in list of buses */ |
||
473 | struct pci_bus *parent; /* parent bus this bridge is on */ |
||
9493 | turbocat | 474 | struct pci_bus *subordinate; |
475 | struct pci_bus *secondary; |
||
6102 | serge | 476 | struct list_head children; /* list of child buses */ |
477 | struct list_head devices; /* list of devices on this bus */ |
||
478 | struct pci_dev *self; /* bridge device as seen by parent */ |
||
479 | struct list_head slots; /* list of slots on this bus; |
||
480 | protected by pci_slot_mutex */ |
||
481 | struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
||
482 | struct list_head resources; /* address space routed to this bus */ |
||
483 | struct resource busn_res; /* bus numbers routed to this bus */ |
||
2161 | serge | 484 | |
6102 | serge | 485 | struct pci_ops *ops; /* configuration access functions */ |
486 | struct msi_controller *msi; /* MSI controller */ |
||
487 | void *sysdata; /* hook for sys-specific extension */ |
||
488 | struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ |
||
2161 | serge | 489 | |
6102 | serge | 490 | unsigned char number; /* bus number */ |
491 | unsigned char primary; /* number of primary bridge */ |
||
492 | unsigned char max_bus_speed; /* enum pci_bus_speed */ |
||
493 | unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
||
494 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
||
495 | int domain_nr; |
||
496 | #endif |
||
2161 | serge | 497 | |
6102 | serge | 498 | char name[48]; |
499 | |||
500 | unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ |
||
501 | pci_bus_flags_t bus_flags; /* inherited by child buses */ |
||
502 | struct device *bridge; |
||
503 | struct device dev; |
||
504 | struct bin_attribute *legacy_io; /* legacy I/O for this bus */ |
||
505 | struct bin_attribute *legacy_mem; /* legacy mem */ |
||
506 | unsigned int is_added:1; |
||
2161 | serge | 507 | }; |
508 | |||
9493 | turbocat | 509 | #define pci_bus_b(n) list_entry(n, struct pci_bus, node) |
510 | #define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) |
||
6102 | serge | 511 | #define to_pci_bus(n) container_of(n, struct pci_bus, dev) |
2161 | serge | 512 | |
513 | /* |
||
5056 | serge | 514 | * Returns true if the PCI bus is root (behind host-PCI bridge), |
2161 | serge | 515 | * false otherwise |
5056 | serge | 516 | * |
517 | * Some code assumes that "bus->self == NULL" means that bus is a root bus. |
||
518 | * This is incorrect because "virtual" buses added for SR-IOV (via |
||
519 | * virtfn_add_bus()) have "bus->self == NULL" but are not root buses. |
||
2161 | serge | 520 | */ |
521 | static inline bool pci_is_root_bus(struct pci_bus *pbus) |
||
522 | { |
||
6102 | serge | 523 | return !(pbus->parent); |
2161 | serge | 524 | } |
525 | |||
6102 | serge | 526 | /** |
527 | * pci_is_bridge - check if the PCI device is a bridge |
||
528 | * @dev: PCI device |
||
529 | * |
||
530 | * Return true if the PCI device is bridge whether it has subordinate |
||
531 | * or not. |
||
532 | */ |
||
533 | static inline bool pci_is_bridge(struct pci_dev *dev) |
||
534 | { |
||
535 | return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
||
536 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; |
||
537 | } |
||
2161 | serge | 538 | |
6102 | serge | 539 | static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) |
540 | { |
||
541 | dev = pci_physfn(dev); |
||
542 | if (pci_is_root_bus(dev->bus)) |
||
543 | return NULL; |
||
2161 | serge | 544 | |
6102 | serge | 545 | return dev->bus->self; |
546 | } |
||
547 | |||
548 | struct device *pci_get_host_bridge_device(struct pci_dev *dev); |
||
549 | void pci_put_host_bridge_device(struct device *dev); |
||
550 | |||
551 | #ifdef CONFIG_PCI_MSI |
||
552 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) |
||
553 | { |
||
554 | return pci_dev->msi_enabled || pci_dev->msix_enabled; |
||
555 | } |
||
556 | #else |
||
557 | static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } |
||
558 | #endif |
||
559 | |||
560 | /* |
||
2161 | serge | 561 | * Error values that may be returned by PCI functions. |
562 | */ |
||
6102 | serge | 563 | #define PCIBIOS_SUCCESSFUL 0x00 |
564 | #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 |
||
565 | #define PCIBIOS_BAD_VENDOR_ID 0x83 |
||
566 | #define PCIBIOS_DEVICE_NOT_FOUND 0x86 |
||
567 | #define PCIBIOS_BAD_REGISTER_NUMBER 0x87 |
||
568 | #define PCIBIOS_SET_FAILED 0x88 |
||
569 | #define PCIBIOS_BUFFER_TOO_SMALL 0x89 |
||
2161 | serge | 570 | |
5056 | serge | 571 | /* |
572 | * Translate above to generic errno for passing back through non-PCI code. |
||
573 | */ |
||
574 | static inline int pcibios_err_to_errno(int err) |
||
575 | { |
||
576 | if (err <= PCIBIOS_SUCCESSFUL) |
||
577 | return err; /* Assume already errno */ |
||
578 | |||
579 | switch (err) { |
||
580 | case PCIBIOS_FUNC_NOT_SUPPORTED: |
||
581 | return -ENOENT; |
||
582 | case PCIBIOS_BAD_VENDOR_ID: |
||
5270 | serge | 583 | return -ENOTTY; |
5056 | serge | 584 | case PCIBIOS_DEVICE_NOT_FOUND: |
585 | return -ENODEV; |
||
586 | case PCIBIOS_BAD_REGISTER_NUMBER: |
||
587 | return -EFAULT; |
||
588 | case PCIBIOS_SET_FAILED: |
||
589 | return -EIO; |
||
590 | case PCIBIOS_BUFFER_TOO_SMALL: |
||
591 | return -ENOSPC; |
||
592 | } |
||
593 | |||
5270 | serge | 594 | return -ERANGE; |
5056 | serge | 595 | } |
596 | |||
2161 | serge | 597 | /* Low-level architecture-dependent routines */ |
598 | |||
599 | struct pci_ops { |
||
6102 | serge | 600 | void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where); |
601 | int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); |
||
602 | int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); |
||
2161 | serge | 603 | }; |
604 | |||
5270 | serge | 605 | /* |
606 | * ACPI needs to be able to access PCI config space before we've done a |
||
607 | * PCI bus scan and created pci_bus structures. |
||
608 | */ |
||
609 | int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, |
||
610 | int reg, int len, u32 *val); |
||
611 | int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, |
||
612 | int reg, int len, u32 val); |
||
2161 | serge | 613 | |
6102 | serge | 614 | #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT |
615 | typedef u64 pci_bus_addr_t; |
||
616 | #else |
||
617 | typedef u32 pci_bus_addr_t; |
||
618 | #endif |
||
619 | |||
5270 | serge | 620 | struct pci_bus_region { |
6102 | serge | 621 | pci_bus_addr_t start; |
622 | pci_bus_addr_t end; |
||
5270 | serge | 623 | }; |
624 | |||
6102 | serge | 625 | struct pci_dynids { |
626 | spinlock_t lock; /* protects list, index */ |
||
627 | struct list_head list; /* for IDs added at runtime */ |
||
2161 | serge | 628 | }; |
629 | |||
6102 | serge | 630 | |
2161 | serge | 631 | /* |
6102 | serge | 632 | * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides |
633 | * a set of callbacks in struct pci_error_handlers, that device driver |
||
634 | * will be notified of PCI bus errors, and will be driven to recovery |
||
635 | * when an error occurs. |
||
636 | */ |
||
637 | |||
638 | typedef unsigned int __bitwise pci_ers_result_t; |
||
639 | |||
640 | enum pci_ers_result { |
||
641 | /* no result/none/not supported in device driver */ |
||
642 | PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, |
||
643 | |||
644 | /* Device driver can recover without slot reset */ |
||
645 | PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, |
||
646 | |||
647 | /* Device driver wants slot to be reset. */ |
||
648 | PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, |
||
649 | |||
650 | /* Device has completely failed, is unrecoverable */ |
||
651 | PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4, |
||
652 | |||
653 | /* Device driver is fully recovered and operational */ |
||
654 | PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5, |
||
655 | |||
656 | /* No AER capabilities registered for the driver */ |
||
657 | PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6, |
||
658 | }; |
||
659 | |||
660 | /* PCI bus error event callbacks */ |
||
661 | struct pci_error_handlers { |
||
662 | /* PCI bus error detected on this device */ |
||
663 | pci_ers_result_t (*error_detected)(struct pci_dev *dev, |
||
664 | enum pci_channel_state error); |
||
665 | |||
666 | /* MMIO has been re-enabled, but not DMA */ |
||
667 | pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); |
||
668 | |||
669 | /* PCI Express link has been reset */ |
||
670 | pci_ers_result_t (*link_reset)(struct pci_dev *dev); |
||
671 | |||
672 | /* PCI slot has been reset */ |
||
673 | pci_ers_result_t (*slot_reset)(struct pci_dev *dev); |
||
674 | |||
675 | /* PCI function reset prepare or completed */ |
||
676 | void (*reset_notify)(struct pci_dev *dev, bool prepare); |
||
677 | |||
678 | /* Device driver may resume normal operations */ |
||
679 | void (*resume)(struct pci_dev *dev); |
||
680 | }; |
||
681 | |||
682 | |||
683 | struct module; |
||
684 | struct pci_driver { |
||
685 | struct list_head node; |
||
686 | const char *name; |
||
687 | const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ |
||
688 | int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ |
||
689 | void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ |
||
690 | int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ |
||
691 | int (*suspend_late) (struct pci_dev *dev, pm_message_t state); |
||
692 | int (*resume_early) (struct pci_dev *dev); |
||
693 | int (*resume) (struct pci_dev *dev); /* Device woken up */ |
||
694 | void (*shutdown) (struct pci_dev *dev); |
||
695 | int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ |
||
696 | const struct pci_error_handlers *err_handler; |
||
697 | struct device_driver driver; |
||
698 | struct pci_dynids dynids; |
||
699 | }; |
||
700 | |||
701 | #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) |
||
702 | |||
703 | /** |
||
704 | * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table |
||
705 | * @_table: device table name |
||
706 | * |
||
707 | * This macro is deprecated and should not be used in new code. |
||
708 | */ |
||
709 | #define DEFINE_PCI_DEVICE_TABLE(_table) \ |
||
710 | const struct pci_device_id _table[] |
||
711 | |||
712 | /** |
||
713 | * PCI_DEVICE - macro used to describe a specific pci device |
||
714 | * @vend: the 16 bit PCI Vendor ID |
||
715 | * @dev: the 16 bit PCI Device ID |
||
716 | * |
||
717 | * This macro is used to create a struct pci_device_id that matches a |
||
718 | * specific device. The subvendor and subdevice fields will be set to |
||
719 | * PCI_ANY_ID. |
||
720 | */ |
||
721 | #define PCI_DEVICE(vend,dev) \ |
||
722 | .vendor = (vend), .device = (dev), \ |
||
723 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
||
724 | |||
725 | /** |
||
726 | * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem |
||
727 | * @vend: the 16 bit PCI Vendor ID |
||
728 | * @dev: the 16 bit PCI Device ID |
||
729 | * @subvend: the 16 bit PCI Subvendor ID |
||
730 | * @subdev: the 16 bit PCI Subdevice ID |
||
731 | * |
||
732 | * This macro is used to create a struct pci_device_id that matches a |
||
733 | * specific device with subsystem information. |
||
734 | */ |
||
735 | #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ |
||
736 | .vendor = (vend), .device = (dev), \ |
||
737 | .subvendor = (subvend), .subdevice = (subdev) |
||
738 | |||
739 | /** |
||
740 | * PCI_DEVICE_CLASS - macro used to describe a specific pci device class |
||
741 | * @dev_class: the class, subclass, prog-if triple for this device |
||
742 | * @dev_class_mask: the class mask for this device |
||
743 | * |
||
744 | * This macro is used to create a struct pci_device_id that matches a |
||
745 | * specific PCI class. The vendor, device, subvendor, and subdevice |
||
746 | * fields will be set to PCI_ANY_ID. |
||
747 | */ |
||
748 | #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \ |
||
749 | .class = (dev_class), .class_mask = (dev_class_mask), \ |
||
750 | .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ |
||
751 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID |
||
752 | |||
753 | /** |
||
754 | * PCI_VDEVICE - macro used to describe a specific pci device in short form |
||
755 | * @vend: the vendor name |
||
756 | * @dev: the 16 bit PCI Device ID |
||
757 | * |
||
758 | * This macro is used to create a struct pci_device_id that matches a |
||
759 | * specific PCI device. The subvendor, and subdevice fields will be set |
||
760 | * to PCI_ANY_ID. The macro allows the next field to follow as the device |
||
761 | * private data. |
||
762 | */ |
||
763 | |||
764 | #define PCI_VDEVICE(vend, dev) \ |
||
765 | .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ |
||
766 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 |
||
767 | |||
7143 | serge | 768 | enum { |
769 | PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */ |
||
770 | PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */ |
||
771 | PCI_PROBE_ONLY = 0x00000004, /* use existing setup */ |
||
772 | PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */ |
||
773 | PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */ |
||
774 | PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ |
||
775 | PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */ |
||
776 | }; |
||
777 | |||
6102 | serge | 778 | /* these external functions are only available when PCI support is enabled */ |
779 | #ifdef CONFIG_PCI |
||
780 | |||
7143 | serge | 781 | extern unsigned int pci_flags; |
782 | |||
783 | static inline void pci_set_flags(int flags) { pci_flags = flags; } |
||
784 | static inline void pci_add_flags(int flags) { pci_flags |= flags; } |
||
785 | static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; } |
||
786 | static inline int pci_has_flag(int flag) { return pci_flags & flag; } |
||
787 | |||
6102 | serge | 788 | void pcie_bus_configure_settings(struct pci_bus *bus); |
789 | |||
790 | enum pcie_bus_config_types { |
||
791 | PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ |
||
792 | PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ |
||
793 | PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ |
||
794 | PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ |
||
795 | PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ |
||
796 | }; |
||
797 | |||
798 | extern enum pcie_bus_config_types pcie_bus_config; |
||
799 | |||
800 | extern struct bus_type pci_bus_type; |
||
801 | |||
802 | /* Do NOT directly access these two variables, unless you are arch-specific PCI |
||
803 | * code, or PCI core code. */ |
||
804 | extern struct list_head pci_root_buses; /* list of all known PCI buses */ |
||
805 | /* Some device drivers need know if PCI is initiated */ |
||
806 | int no_pci_devices(void); |
||
807 | |||
808 | void pcibios_resource_survey_bus(struct pci_bus *bus); |
||
7143 | serge | 809 | void pcibios_bus_add_device(struct pci_dev *pdev); |
6102 | serge | 810 | void pcibios_add_bus(struct pci_bus *bus); |
811 | void pcibios_remove_bus(struct pci_bus *bus); |
||
812 | void pcibios_fixup_bus(struct pci_bus *); |
||
813 | int __must_check pcibios_enable_device(struct pci_dev *, int mask); |
||
814 | /* Architecture-specific versions may override this (weak) */ |
||
815 | char *pcibios_setup(char *str); |
||
816 | |||
817 | /* Used only when drivers/pci/setup.c is used */ |
||
818 | resource_size_t pcibios_align_resource(void *, const struct resource *, |
||
819 | resource_size_t, |
||
820 | resource_size_t); |
||
821 | void pcibios_update_irq(struct pci_dev *, int irq); |
||
822 | |||
823 | /* Weak but can be overriden by arch */ |
||
824 | void pci_fixup_cardbus(struct pci_bus *); |
||
825 | |||
826 | /* Generic PCI functions used internally */ |
||
827 | |||
828 | void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region, |
||
829 | struct resource *res); |
||
830 | void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res, |
||
831 | struct pci_bus_region *region); |
||
832 | void pcibios_scan_specific_bus(int busn); |
||
833 | struct pci_bus *pci_find_bus(int domain, int busnr); |
||
834 | void pci_bus_add_devices(const struct pci_bus *bus); |
||
835 | struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); |
||
836 | struct pci_bus *pci_create_root_bus(struct device *parent, int bus, |
||
837 | struct pci_ops *ops, void *sysdata, |
||
838 | struct list_head *resources); |
||
839 | int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); |
||
840 | int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); |
||
841 | void pci_bus_release_busn_res(struct pci_bus *b); |
||
842 | struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus, |
||
843 | struct pci_ops *ops, void *sysdata, |
||
844 | struct list_head *resources, |
||
845 | struct msi_controller *msi); |
||
846 | struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, |
||
847 | struct pci_ops *ops, void *sysdata, |
||
848 | struct list_head *resources); |
||
849 | struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, |
||
850 | int busnr); |
||
851 | void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); |
||
852 | struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, |
||
853 | const char *name, |
||
854 | struct hotplug_slot *hotplug); |
||
855 | void pci_destroy_slot(struct pci_slot *slot); |
||
856 | #ifdef CONFIG_SYSFS |
||
857 | void pci_dev_assign_slot(struct pci_dev *dev); |
||
858 | #else |
||
859 | static inline void pci_dev_assign_slot(struct pci_dev *dev) { } |
||
860 | #endif |
||
861 | int pci_scan_slot(struct pci_bus *bus, int devfn); |
||
862 | struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); |
||
863 | void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); |
||
864 | unsigned int pci_scan_child_bus(struct pci_bus *bus); |
||
865 | void pci_bus_add_device(struct pci_dev *dev); |
||
866 | void pci_read_bridge_bases(struct pci_bus *child); |
||
867 | struct resource *pci_find_parent_resource(const struct pci_dev *dev, |
||
868 | struct resource *res); |
||
869 | struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev); |
||
9493 | turbocat | 870 | u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin); |
6102 | serge | 871 | int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); |
872 | u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp); |
||
873 | struct pci_dev *pci_dev_get(struct pci_dev *dev); |
||
874 | void pci_dev_put(struct pci_dev *dev); |
||
875 | void pci_remove_bus(struct pci_bus *b); |
||
876 | void pci_stop_and_remove_bus_device(struct pci_dev *dev); |
||
877 | void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev); |
||
878 | void pci_stop_root_bus(struct pci_bus *bus); |
||
879 | void pci_remove_root_bus(struct pci_bus *bus); |
||
880 | void pci_setup_cardbus(struct pci_bus *bus); |
||
881 | void pci_sort_breadthfirst(void); |
||
882 | #define dev_is_pci(d) ((d)->bus == &pci_bus_type) |
||
883 | #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false)) |
||
884 | #define dev_num_vf(d) ((dev_is_pci(d) ? pci_num_vf(to_pci_dev(d)) : 0)) |
||
885 | |||
886 | /* Generic PCI functions exported to card drivers */ |
||
887 | |||
888 | enum pci_lost_interrupt_reason { |
||
889 | PCI_LOST_IRQ_NO_INFORMATION = 0, |
||
890 | PCI_LOST_IRQ_DISABLE_MSI, |
||
891 | PCI_LOST_IRQ_DISABLE_MSIX, |
||
892 | PCI_LOST_IRQ_DISABLE_ACPI, |
||
893 | }; |
||
894 | enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); |
||
895 | int pci_find_capability(struct pci_dev *dev, int cap); |
||
896 | int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); |
||
897 | int pci_find_ext_capability(struct pci_dev *dev, int cap); |
||
898 | int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap); |
||
899 | int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); |
||
900 | int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); |
||
901 | struct pci_bus *pci_find_next_bus(const struct pci_bus *from); |
||
902 | |||
903 | struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, |
||
904 | struct pci_dev *from); |
||
905 | struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, |
||
906 | unsigned int ss_vendor, unsigned int ss_device, |
||
907 | struct pci_dev *from); |
||
908 | struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); |
||
909 | struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, |
||
910 | unsigned int devfn); |
||
911 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
||
912 | unsigned int devfn) |
||
913 | { |
||
914 | return pci_get_domain_bus_and_slot(0, bus, devfn); |
||
915 | } |
||
916 | struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); |
||
917 | int pci_dev_present(const struct pci_device_id *ids); |
||
918 | |||
919 | int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, |
||
920 | int where, u8 *val); |
||
921 | int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, |
||
922 | int where, u16 *val); |
||
923 | int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, |
||
924 | int where, u32 *val); |
||
925 | int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, |
||
926 | int where, u8 val); |
||
927 | int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, |
||
928 | int where, u16 val); |
||
929 | int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, |
||
930 | int where, u32 val); |
||
931 | |||
932 | int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn, |
||
933 | int where, int size, u32 *val); |
||
934 | int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn, |
||
935 | int where, int size, u32 val); |
||
936 | int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn, |
||
937 | int where, int size, u32 *val); |
||
938 | int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn, |
||
939 | int where, int size, u32 val); |
||
940 | |||
941 | struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops); |
||
942 | |||
9078 | turbocat | 943 | |
944 | #if 0 |
||
6102 | serge | 945 | static inline int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val) |
946 | { |
||
947 | *val = PciRead8(dev->busnr, dev->devfn, where); |
||
948 | return 1; |
||
949 | } |
||
950 | static inline int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val) |
||
951 | { |
||
952 | *val = PciRead16(dev->busnr, dev->devfn, where); |
||
953 | return 1; |
||
954 | } |
||
955 | static inline int pci_read_config_dword(const struct pci_dev *dev, int where, |
||
956 | u32 *val) |
||
957 | { |
||
958 | *val = PciRead32(dev->busnr, dev->devfn, where); |
||
959 | return 1; |
||
960 | } |
||
961 | static inline int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val) |
||
962 | { |
||
963 | PciWrite8(dev->busnr, dev->devfn, where, val); |
||
964 | return 1; |
||
965 | } |
||
966 | static inline int pci_write_config_word(const struct pci_dev *dev, int where, u16 val) |
||
967 | { |
||
968 | PciWrite16(dev->busnr, dev->devfn, where, val); |
||
969 | return 1; |
||
970 | } |
||
971 | static inline int pci_write_config_dword(const struct pci_dev *dev, int where, |
||
972 | u32 val) |
||
973 | { |
||
974 | PciWrite32(dev->busnr, dev->devfn, where, val); |
||
975 | return 1; |
||
976 | } |
||
9078 | turbocat | 977 | #endif |
6102 | serge | 978 | |
9078 | turbocat | 979 | static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) |
980 | { |
||
981 | *val = PciRead8(dev->busnr, dev->devfn, where); |
||
982 | return 0; |
||
983 | } |
||
984 | |||
985 | static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) |
||
986 | { |
||
987 | |||
988 | if ( where & 1) |
||
989 | return PCIBIOS_BAD_REGISTER_NUMBER; |
||
990 | *val = PciRead16(dev->busnr, dev->devfn, where); |
||
991 | return 0; |
||
992 | } |
||
993 | |||
994 | static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val) |
||
995 | { |
||
996 | |||
997 | if ( where & 3) |
||
998 | return PCIBIOS_BAD_REGISTER_NUMBER; |
||
999 | *val = PciRead32(dev->busnr, dev->devfn, where); |
||
1000 | return 0; |
||
1001 | } |
||
1002 | |||
1003 | static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) |
||
1004 | { |
||
1005 | PciWrite8(dev->busnr, dev->devfn, where, val); |
||
1006 | return 0; |
||
1007 | }; |
||
1008 | |||
1009 | static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) |
||
1010 | { |
||
1011 | if ( where & 1) |
||
1012 | return PCIBIOS_BAD_REGISTER_NUMBER; |
||
1013 | PciWrite16(dev->busnr, dev->devfn, where, val); |
||
1014 | return 0; |
||
1015 | } |
||
1016 | |||
1017 | static inline int pci_write_config_dword(struct pci_dev *dev, int where, |
||
1018 | u32 val) |
||
1019 | { |
||
1020 | if ( where & 3) |
||
1021 | return PCIBIOS_BAD_REGISTER_NUMBER; |
||
1022 | PciWrite32(dev->busnr, dev->devfn, where, val); |
||
1023 | return 0; |
||
1024 | } |
||
1025 | |||
1026 | |||
6102 | serge | 1027 | int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val); |
1028 | int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); |
||
1029 | int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val); |
||
1030 | int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val); |
||
1031 | int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos, |
||
1032 | u16 clear, u16 set); |
||
1033 | int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos, |
||
1034 | u32 clear, u32 set); |
||
1035 | |||
1036 | static inline int pcie_capability_set_word(struct pci_dev *dev, int pos, |
||
1037 | u16 set) |
||
1038 | { |
||
1039 | return pcie_capability_clear_and_set_word(dev, pos, 0, set); |
||
1040 | } |
||
1041 | |||
1042 | static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos, |
||
1043 | u32 set) |
||
1044 | { |
||
1045 | return pcie_capability_clear_and_set_dword(dev, pos, 0, set); |
||
1046 | } |
||
1047 | |||
1048 | static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos, |
||
1049 | u16 clear) |
||
1050 | { |
||
1051 | return pcie_capability_clear_and_set_word(dev, pos, clear, 0); |
||
1052 | } |
||
1053 | |||
1054 | static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos, |
||
1055 | u32 clear) |
||
1056 | { |
||
1057 | return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); |
||
1058 | } |
||
1059 | |||
1060 | /* user-space driven config access */ |
||
1061 | int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); |
||
1062 | int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); |
||
1063 | int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); |
||
1064 | int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val); |
||
1065 | int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val); |
||
1066 | int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val); |
||
1067 | |||
1068 | int __must_check pci_enable_device(struct pci_dev *dev); |
||
1069 | int __must_check pci_enable_device_io(struct pci_dev *dev); |
||
1070 | int __must_check pci_enable_device_mem(struct pci_dev *dev); |
||
1071 | int __must_check pci_reenable_device(struct pci_dev *); |
||
1072 | int __must_check pcim_enable_device(struct pci_dev *pdev); |
||
1073 | void pcim_pin_device(struct pci_dev *pdev); |
||
1074 | |||
1075 | static inline int pci_is_enabled(struct pci_dev *pdev) |
||
1076 | { |
||
1077 | return (atomic_read(&pdev->enable_cnt) > 0); |
||
1078 | } |
||
1079 | |||
1080 | static inline int pci_is_managed(struct pci_dev *pdev) |
||
1081 | { |
||
1082 | return pdev->is_managed; |
||
1083 | } |
||
1084 | |||
1085 | void pci_disable_device(struct pci_dev *dev); |
||
1086 | |||
1087 | extern unsigned int pcibios_max_latency; |
||
1088 | void pci_set_master(struct pci_dev *dev); |
||
1089 | void pci_clear_master(struct pci_dev *dev); |
||
1090 | |||
1091 | int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state); |
||
1092 | int pci_set_cacheline_size(struct pci_dev *dev); |
||
1093 | #define HAVE_PCI_SET_MWI |
||
1094 | int __must_check pci_set_mwi(struct pci_dev *dev); |
||
1095 | int pci_try_set_mwi(struct pci_dev *dev); |
||
1096 | void pci_clear_mwi(struct pci_dev *dev); |
||
1097 | void pci_intx(struct pci_dev *dev, int enable); |
||
1098 | bool pci_intx_mask_supported(struct pci_dev *dev); |
||
1099 | bool pci_check_and_mask_intx(struct pci_dev *dev); |
||
1100 | bool pci_check_and_unmask_intx(struct pci_dev *dev); |
||
1101 | int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask); |
||
1102 | int pci_wait_for_pending_transaction(struct pci_dev *dev); |
||
1103 | int pcix_get_max_mmrbc(struct pci_dev *dev); |
||
1104 | int pcix_get_mmrbc(struct pci_dev *dev); |
||
1105 | int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); |
||
1106 | int pcie_get_readrq(struct pci_dev *dev); |
||
1107 | int pcie_set_readrq(struct pci_dev *dev, int rq); |
||
1108 | int pcie_get_mps(struct pci_dev *dev); |
||
1109 | int pcie_set_mps(struct pci_dev *dev, int mps); |
||
1110 | int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed, |
||
1111 | enum pcie_link_width *width); |
||
1112 | int __pci_reset_function(struct pci_dev *dev); |
||
1113 | int __pci_reset_function_locked(struct pci_dev *dev); |
||
1114 | int pci_reset_function(struct pci_dev *dev); |
||
1115 | int pci_try_reset_function(struct pci_dev *dev); |
||
1116 | int pci_probe_reset_slot(struct pci_slot *slot); |
||
1117 | int pci_reset_slot(struct pci_slot *slot); |
||
1118 | int pci_try_reset_slot(struct pci_slot *slot); |
||
1119 | int pci_probe_reset_bus(struct pci_bus *bus); |
||
1120 | int pci_reset_bus(struct pci_bus *bus); |
||
1121 | int pci_try_reset_bus(struct pci_bus *bus); |
||
1122 | void pci_reset_secondary_bus(struct pci_dev *dev); |
||
1123 | void pcibios_reset_secondary_bus(struct pci_dev *dev); |
||
1124 | void pci_reset_bridge_secondary_bus(struct pci_dev *dev); |
||
1125 | void pci_update_resource(struct pci_dev *dev, int resno); |
||
1126 | int __must_check pci_assign_resource(struct pci_dev *dev, int i); |
||
1127 | int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); |
||
1128 | int pci_select_bars(struct pci_dev *dev, unsigned long flags); |
||
1129 | bool pci_device_is_present(struct pci_dev *pdev); |
||
1130 | void pci_ignore_hotplug(struct pci_dev *dev); |
||
1131 | |||
1132 | /* ROM control related routines */ |
||
1133 | int pci_enable_rom(struct pci_dev *pdev); |
||
1134 | void pci_disable_rom(struct pci_dev *pdev); |
||
1135 | void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); |
||
1136 | void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); |
||
1137 | size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size); |
||
1138 | void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size); |
||
1139 | |||
1140 | /* Power management related routines */ |
||
1141 | int pci_save_state(struct pci_dev *dev); |
||
1142 | void pci_restore_state(struct pci_dev *dev); |
||
1143 | struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev); |
||
1144 | int pci_load_saved_state(struct pci_dev *dev, |
||
1145 | struct pci_saved_state *state); |
||
1146 | int pci_load_and_free_saved_state(struct pci_dev *dev, |
||
1147 | struct pci_saved_state **state); |
||
1148 | struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); |
||
1149 | struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, |
||
1150 | u16 cap); |
||
1151 | int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); |
||
1152 | int pci_add_ext_cap_save_buffer(struct pci_dev *dev, |
||
1153 | u16 cap, unsigned int size); |
||
1154 | int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state); |
||
1155 | int pci_set_power_state(struct pci_dev *dev, pci_power_t state); |
||
1156 | pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); |
||
1157 | bool pci_pme_capable(struct pci_dev *dev, pci_power_t state); |
||
1158 | void pci_pme_active(struct pci_dev *dev, bool enable); |
||
1159 | int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
||
1160 | bool runtime, bool enable); |
||
1161 | int pci_wake_from_d3(struct pci_dev *dev, bool enable); |
||
1162 | int pci_prepare_to_sleep(struct pci_dev *dev); |
||
1163 | int pci_back_from_sleep(struct pci_dev *dev); |
||
1164 | bool pci_dev_run_wake(struct pci_dev *dev); |
||
1165 | bool pci_check_pme_status(struct pci_dev *dev); |
||
1166 | void pci_pme_wakeup_bus(struct pci_bus *bus); |
||
1167 | |||
1168 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
||
1169 | bool enable) |
||
1170 | { |
||
1171 | return __pci_enable_wake(dev, state, false, enable); |
||
1172 | } |
||
1173 | |||
1174 | /* PCI Virtual Channel */ |
||
1175 | int pci_save_vc_state(struct pci_dev *dev); |
||
1176 | void pci_restore_vc_state(struct pci_dev *dev); |
||
1177 | void pci_allocate_vc_save_buffers(struct pci_dev *dev); |
||
1178 | |||
1179 | /* For use by arch with custom probe code */ |
||
1180 | void set_pcie_port_type(struct pci_dev *pdev); |
||
1181 | void set_pcie_hotplug_bridge(struct pci_dev *pdev); |
||
1182 | |||
1183 | /* Functions for PCI Hotplug drivers to use */ |
||
1184 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); |
||
1185 | unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); |
||
1186 | unsigned int pci_rescan_bus(struct pci_bus *bus); |
||
1187 | void pci_lock_rescan_remove(void); |
||
1188 | void pci_unlock_rescan_remove(void); |
||
1189 | |||
1190 | /* Vital product data routines */ |
||
1191 | ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); |
||
1192 | ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); |
||
7143 | serge | 1193 | int pci_set_vpd_size(struct pci_dev *dev, size_t len); |
6102 | serge | 1194 | |
1195 | /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ |
||
1196 | resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx); |
||
1197 | void pci_bus_assign_resources(const struct pci_bus *bus); |
||
1198 | void pci_bus_size_bridges(struct pci_bus *bus); |
||
1199 | int pci_claim_resource(struct pci_dev *, int); |
||
1200 | int pci_claim_bridge_resource(struct pci_dev *bridge, int i); |
||
1201 | void pci_assign_unassigned_resources(void); |
||
1202 | void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge); |
||
1203 | void pci_assign_unassigned_bus_resources(struct pci_bus *bus); |
||
1204 | void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus); |
||
1205 | void pdev_enable_device(struct pci_dev *); |
||
1206 | int pci_enable_resources(struct pci_dev *, int mask); |
||
1207 | void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), |
||
1208 | int (*)(const struct pci_dev *, u8, u8)); |
||
1209 | #define HAVE_PCI_REQ_REGIONS 2 |
||
1210 | int __must_check pci_request_regions(struct pci_dev *, const char *); |
||
1211 | int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *); |
||
1212 | void pci_release_regions(struct pci_dev *); |
||
1213 | int __must_check pci_request_region(struct pci_dev *, int, const char *); |
||
1214 | int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *); |
||
1215 | void pci_release_region(struct pci_dev *, int); |
||
1216 | int pci_request_selected_regions(struct pci_dev *, int, const char *); |
||
1217 | int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *); |
||
1218 | void pci_release_selected_regions(struct pci_dev *, int); |
||
1219 | |||
1220 | /* drivers/pci/bus.c */ |
||
1221 | struct pci_bus *pci_bus_get(struct pci_bus *bus); |
||
1222 | void pci_bus_put(struct pci_bus *bus); |
||
1223 | void pci_add_resource(struct list_head *resources, struct resource *res); |
||
1224 | void pci_add_resource_offset(struct list_head *resources, struct resource *res, |
||
1225 | resource_size_t offset); |
||
1226 | void pci_free_resource_list(struct list_head *resources); |
||
1227 | void pci_bus_add_resource(struct pci_bus *bus, struct resource *res, unsigned int flags); |
||
1228 | struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n); |
||
1229 | void pci_bus_remove_resources(struct pci_bus *bus); |
||
1230 | |||
1231 | #define pci_bus_for_each_resource(bus, res, i) \ |
||
1232 | for (i = 0; \ |
||
1233 | (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \ |
||
1234 | i++) |
||
1235 | |||
1236 | int __must_check pci_bus_alloc_resource(struct pci_bus *bus, |
||
1237 | struct resource *res, resource_size_t size, |
||
1238 | resource_size_t align, resource_size_t min, |
||
1239 | unsigned long type_mask, |
||
1240 | resource_size_t (*alignf)(void *, |
||
1241 | const struct resource *, |
||
1242 | resource_size_t, |
||
1243 | resource_size_t), |
||
1244 | void *alignf_data); |
||
1245 | |||
1246 | |||
1247 | int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr); |
||
1248 | |||
6125 | serge | 1249 | static inline void |
1250 | _pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, |
||
1251 | struct resource *res) |
||
1252 | { |
||
1253 | region->start = res->start; |
||
1254 | region->end = res->end; |
||
1255 | } |
||
1256 | |||
6102 | serge | 1257 | static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar) |
1258 | { |
||
1259 | struct pci_bus_region region; |
||
1260 | |||
6125 | serge | 1261 | _pcibios_resource_to_bus(pdev, ®ion, &pdev->resource[bar]); |
6102 | serge | 1262 | return region.start; |
1263 | } |
||
1264 | |||
1265 | /* Proper probing supporting hot-pluggable devices */ |
||
1266 | int __must_check __pci_register_driver(struct pci_driver *, struct module *, |
||
1267 | const char *mod_name); |
||
1268 | |||
1269 | /* |
||
1270 | * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded |
||
1271 | */ |
||
1272 | #define pci_register_driver(driver) \ |
||
1273 | __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) |
||
1274 | |||
1275 | void pci_unregister_driver(struct pci_driver *dev); |
||
1276 | |||
1277 | /** |
||
1278 | * module_pci_driver() - Helper macro for registering a PCI driver |
||
1279 | * @__pci_driver: pci_driver struct |
||
1280 | * |
||
1281 | * Helper macro for PCI drivers which do not do anything special in module |
||
1282 | * init/exit. This eliminates a lot of boilerplate. Each module may only |
||
1283 | * use this macro once, and calling it replaces module_init() and module_exit() |
||
1284 | */ |
||
1285 | #define module_pci_driver(__pci_driver) \ |
||
1286 | module_driver(__pci_driver, pci_register_driver, \ |
||
1287 | pci_unregister_driver) |
||
1288 | |||
1289 | /** |
||
1290 | * builtin_pci_driver() - Helper macro for registering a PCI driver |
||
1291 | * @__pci_driver: pci_driver struct |
||
1292 | * |
||
1293 | * Helper macro for PCI drivers which do not do anything special in their |
||
1294 | * init code. This eliminates a lot of boilerplate. Each driver may only |
||
1295 | * use this macro once, and calling it replaces device_initcall(...) |
||
1296 | */ |
||
1297 | #define builtin_pci_driver(__pci_driver) \ |
||
1298 | builtin_driver(__pci_driver, pci_register_driver) |
||
1299 | |||
1300 | struct pci_driver *pci_dev_driver(const struct pci_dev *dev); |
||
1301 | int pci_add_dynid(struct pci_driver *drv, |
||
1302 | unsigned int vendor, unsigned int device, |
||
1303 | unsigned int subvendor, unsigned int subdevice, |
||
1304 | unsigned int class, unsigned int class_mask, |
||
1305 | unsigned long driver_data); |
||
1306 | const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, |
||
1307 | struct pci_dev *dev); |
||
1308 | int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, |
||
1309 | int pass); |
||
1310 | |||
1311 | void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), |
||
1312 | void *userdata); |
||
1313 | int pci_cfg_space_size(struct pci_dev *dev); |
||
1314 | unsigned char pci_bus_max_busnr(struct pci_bus *bus); |
||
1315 | void pci_setup_bridge(struct pci_bus *bus); |
||
1316 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, |
||
1317 | unsigned long type); |
||
1318 | resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno); |
||
1319 | |||
1320 | #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) |
||
1321 | #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) |
||
1322 | |||
1323 | int pci_set_vga_state(struct pci_dev *pdev, bool decode, |
||
1324 | unsigned int command_bits, u32 flags); |
||
7143 | serge | 1325 | |
6102 | serge | 1326 | /* kmem_cache style wrapper around pci_alloc_consistent() */ |
1327 | |||
1328 | #include |
||
1329 | #include |
||
1330 | |||
1331 | #define pci_pool dma_pool |
||
1332 | #define pci_pool_create(name, pdev, size, align, allocation) \ |
||
1333 | dma_pool_create(name, &pdev->dev, size, align, allocation) |
||
1334 | #define pci_pool_destroy(pool) dma_pool_destroy(pool) |
||
1335 | #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle) |
||
1336 | #define pci_pool_zalloc(pool, flags, handle) \ |
||
1337 | dma_pool_zalloc(pool, flags, handle) |
||
1338 | #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) |
||
1339 | |||
1340 | struct msix_entry { |
||
1341 | u32 vector; /* kernel uses to write allocated vector */ |
||
1342 | u16 entry; /* driver uses to specify entry, OS writes */ |
||
1343 | }; |
||
1344 | |||
1345 | #ifdef CONFIG_PCI_MSI |
||
1346 | int pci_msi_vec_count(struct pci_dev *dev); |
||
1347 | void pci_msi_shutdown(struct pci_dev *dev); |
||
1348 | void pci_disable_msi(struct pci_dev *dev); |
||
1349 | int pci_msix_vec_count(struct pci_dev *dev); |
||
1350 | int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); |
||
1351 | void pci_msix_shutdown(struct pci_dev *dev); |
||
1352 | void pci_disable_msix(struct pci_dev *dev); |
||
1353 | void pci_restore_msi_state(struct pci_dev *dev); |
||
1354 | int pci_msi_enabled(void); |
||
1355 | int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec); |
||
1356 | static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) |
||
1357 | { |
||
1358 | int rc = pci_enable_msi_range(dev, nvec, nvec); |
||
1359 | if (rc < 0) |
||
1360 | return rc; |
||
1361 | return 0; |
||
1362 | } |
||
1363 | int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, |
||
1364 | int minvec, int maxvec); |
||
1365 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
||
1366 | struct msix_entry *entries, int nvec) |
||
1367 | { |
||
1368 | int rc = pci_enable_msix_range(dev, entries, nvec, nvec); |
||
1369 | if (rc < 0) |
||
1370 | return rc; |
||
1371 | return 0; |
||
1372 | } |
||
1373 | #else |
||
1374 | static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
||
1375 | static inline void pci_msi_shutdown(struct pci_dev *dev) { } |
||
1376 | static inline void pci_disable_msi(struct pci_dev *dev) { } |
||
1377 | static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; } |
||
1378 | static inline int pci_enable_msix(struct pci_dev *dev, |
||
1379 | struct msix_entry *entries, int nvec) |
||
1380 | { return -ENOSYS; } |
||
1381 | static inline void pci_msix_shutdown(struct pci_dev *dev) { } |
||
1382 | static inline void pci_disable_msix(struct pci_dev *dev) { } |
||
1383 | static inline void pci_restore_msi_state(struct pci_dev *dev) { } |
||
1384 | static inline int pci_msi_enabled(void) { return 0; } |
||
1385 | static inline int pci_enable_msi_range(struct pci_dev *dev, int minvec, |
||
1386 | int maxvec) |
||
1387 | { return -ENOSYS; } |
||
1388 | static inline int pci_enable_msi_exact(struct pci_dev *dev, int nvec) |
||
1389 | { return -ENOSYS; } |
||
1390 | static inline int pci_enable_msix_range(struct pci_dev *dev, |
||
1391 | struct msix_entry *entries, int minvec, int maxvec) |
||
1392 | { return -ENOSYS; } |
||
1393 | static inline int pci_enable_msix_exact(struct pci_dev *dev, |
||
1394 | struct msix_entry *entries, int nvec) |
||
1395 | { return -ENOSYS; } |
||
1396 | #endif |
||
1397 | |||
1398 | #ifdef CONFIG_PCIEPORTBUS |
||
1399 | extern bool pcie_ports_disabled; |
||
1400 | extern bool pcie_ports_auto; |
||
1401 | #else |
||
1402 | #define pcie_ports_disabled true |
||
1403 | #define pcie_ports_auto false |
||
1404 | #endif |
||
1405 | |||
1406 | #ifdef CONFIG_PCIEASPM |
||
1407 | bool pcie_aspm_support_enabled(void); |
||
1408 | #else |
||
1409 | static inline bool pcie_aspm_support_enabled(void) { return false; } |
||
1410 | #endif |
||
1411 | |||
1412 | #ifdef CONFIG_PCIEAER |
||
1413 | void pci_no_aer(void); |
||
1414 | bool pci_aer_available(void); |
||
1415 | #else |
||
1416 | static inline void pci_no_aer(void) { } |
||
1417 | static inline bool pci_aer_available(void) { return false; } |
||
1418 | #endif |
||
1419 | |||
1420 | #ifdef CONFIG_PCIE_ECRC |
||
1421 | void pcie_set_ecrc_checking(struct pci_dev *dev); |
||
1422 | void pcie_ecrc_get_policy(char *str); |
||
1423 | #else |
||
1424 | static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } |
||
1425 | static inline void pcie_ecrc_get_policy(char *str) { } |
||
1426 | #endif |
||
1427 | |||
1428 | #define pci_enable_msi(pdev) pci_enable_msi_exact(pdev, 1) |
||
1429 | |||
1430 | #ifdef CONFIG_HT_IRQ |
||
1431 | /* The functions a driver should call */ |
||
1432 | int ht_create_irq(struct pci_dev *dev, int idx); |
||
1433 | void ht_destroy_irq(unsigned int irq); |
||
1434 | #endif /* CONFIG_HT_IRQ */ |
||
1435 | |||
1436 | #ifdef CONFIG_PCI_ATS |
||
1437 | /* Address Translation Service */ |
||
1438 | void pci_ats_init(struct pci_dev *dev); |
||
1439 | int pci_enable_ats(struct pci_dev *dev, int ps); |
||
1440 | void pci_disable_ats(struct pci_dev *dev); |
||
1441 | int pci_ats_queue_depth(struct pci_dev *dev); |
||
1442 | #else |
||
1443 | static inline void pci_ats_init(struct pci_dev *d) { } |
||
1444 | static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; } |
||
1445 | static inline void pci_disable_ats(struct pci_dev *d) { } |
||
1446 | static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; } |
||
1447 | #endif |
||
1448 | |||
1449 | void pci_cfg_access_lock(struct pci_dev *dev); |
||
1450 | bool pci_cfg_access_trylock(struct pci_dev *dev); |
||
1451 | void pci_cfg_access_unlock(struct pci_dev *dev); |
||
1452 | |||
1453 | /* |
||
2161 | serge | 1454 | * PCI domain support. Sometimes called PCI segment (eg by ACPI), |
6102 | serge | 1455 | * a PCI domain is defined to be a set of PCI buses which share |
2161 | serge | 1456 | * configuration space. |
1457 | */ |
||
1458 | #ifdef CONFIG_PCI_DOMAINS |
||
1459 | extern int pci_domains_supported; |
||
6102 | serge | 1460 | int pci_get_new_domain_nr(void); |
2161 | serge | 1461 | #else |
1462 | enum { pci_domains_supported = 0 }; |
||
6102 | serge | 1463 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
1464 | static inline int pci_proc_domain(struct pci_bus *bus) { return 0; } |
||
1465 | static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } |
||
1466 | #endif /* CONFIG_PCI_DOMAINS */ |
||
1467 | |||
1468 | /* |
||
1469 | * Generic implementation for PCI domain support. If your |
||
1470 | * architecture does not need custom management of PCI |
||
1471 | * domains then this implementation will be used |
||
1472 | */ |
||
1473 | #ifdef CONFIG_PCI_DOMAINS_GENERIC |
||
2161 | serge | 1474 | static inline int pci_domain_nr(struct pci_bus *bus) |
1475 | { |
||
6102 | serge | 1476 | return bus->domain_nr; |
2161 | serge | 1477 | } |
6102 | serge | 1478 | void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent); |
1479 | #else |
||
1480 | static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, |
||
1481 | struct device *parent) |
||
1482 | { |
||
1483 | } |
||
1484 | #endif |
||
2161 | serge | 1485 | |
6102 | serge | 1486 | /* some architectures require additional setup to direct VGA traffic */ |
1487 | typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, |
||
1488 | unsigned int command_bits, u32 flags); |
||
1489 | void pci_register_set_vga_state(arch_set_vga_state_t func); |
||
1490 | |||
1491 | #else /* CONFIG_PCI is not enabled */ |
||
1492 | |||
7143 | serge | 1493 | static inline void pci_set_flags(int flags) { } |
1494 | static inline void pci_add_flags(int flags) { } |
||
1495 | static inline void pci_clear_flags(int flags) { } |
||
1496 | static inline int pci_has_flag(int flag) { return 0; } |
||
1497 | |||
6102 | serge | 1498 | /* |
1499 | * If the system does not have PCI, clearly these return errors. Define |
||
1500 | * these as simple inline functions to avoid hair in drivers. |
||
1501 | */ |
||
1502 | |||
1503 | #define _PCI_NOP(o, s, t) \ |
||
1504 | static inline int pci_##o##_config_##s(struct pci_dev *dev, \ |
||
1505 | int where, t val) \ |
||
1506 | { return PCIBIOS_FUNC_NOT_SUPPORTED; } |
||
1507 | |||
1508 | #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ |
||
1509 | _PCI_NOP(o, word, u16 x) \ |
||
1510 | _PCI_NOP(o, dword, u32 x) |
||
1511 | _PCI_NOP_ALL(read, *) |
||
1512 | _PCI_NOP_ALL(write,) |
||
9078 | turbocat | 1513 | /* |
6102 | serge | 1514 | static inline struct pci_dev *pci_get_device(unsigned int vendor, |
1515 | unsigned int device, |
||
1516 | struct pci_dev *from) |
||
9078 | turbocat | 1517 | { return NULL; }*/ |
6102 | serge | 1518 | |
1519 | static inline struct pci_dev *pci_get_subsys(unsigned int vendor, |
||
1520 | unsigned int device, |
||
1521 | unsigned int ss_vendor, |
||
1522 | unsigned int ss_device, |
||
1523 | struct pci_dev *from) |
||
1524 | { return NULL; } |
||
1525 | |||
1526 | static inline struct pci_dev *pci_get_class(unsigned int class, |
||
1527 | struct pci_dev *from) |
||
1528 | { return NULL; } |
||
1529 | |||
1530 | #define pci_dev_present(ids) (0) |
||
1531 | #define no_pci_devices() (1) |
||
1532 | #define pci_dev_put(dev) do { } while (0) |
||
1533 | |||
1534 | static inline void pci_set_master(struct pci_dev *dev) { } |
||
1535 | static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } |
||
1536 | static inline void pci_disable_device(struct pci_dev *dev) { } |
||
1537 | static inline int pci_assign_resource(struct pci_dev *dev, int i) |
||
1538 | { return -EBUSY; } |
||
1539 | static inline int __pci_register_driver(struct pci_driver *drv, |
||
1540 | struct module *owner) |
||
1541 | { return 0; } |
||
1542 | static inline int pci_register_driver(struct pci_driver *drv) |
||
1543 | { return 0; } |
||
1544 | static inline void pci_unregister_driver(struct pci_driver *drv) { } |
||
1545 | static inline int pci_find_capability(struct pci_dev *dev, int cap) |
||
1546 | { return 0; } |
||
1547 | static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, |
||
1548 | int cap) |
||
1549 | { return 0; } |
||
1550 | static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) |
||
1551 | { return 0; } |
||
1552 | |||
1553 | /* Power management related routines */ |
||
1554 | static inline int pci_save_state(struct pci_dev *dev) { return 0; } |
||
1555 | static inline void pci_restore_state(struct pci_dev *dev) { } |
||
1556 | static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
||
1557 | { return 0; } |
||
1558 | static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable) |
||
1559 | { return 0; } |
||
1560 | static inline pci_power_t pci_choose_state(struct pci_dev *dev, |
||
1561 | pm_message_t state) |
||
1562 | { return PCI_D0; } |
||
1563 | static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, |
||
1564 | int enable) |
||
1565 | { return 0; } |
||
1566 | |||
1567 | static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) |
||
1568 | { return -EIO; } |
||
1569 | static inline void pci_release_regions(struct pci_dev *dev) { } |
||
1570 | |||
1571 | static inline void pci_block_cfg_access(struct pci_dev *dev) { } |
||
1572 | static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev) |
||
1573 | { return 0; } |
||
1574 | static inline void pci_unblock_cfg_access(struct pci_dev *dev) { } |
||
1575 | |||
1576 | static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) |
||
1577 | { return NULL; } |
||
1578 | static inline struct pci_dev *pci_get_slot(struct pci_bus *bus, |
||
1579 | unsigned int devfn) |
||
1580 | { return NULL; } |
||
1581 | static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, |
||
1582 | unsigned int devfn) |
||
1583 | { return NULL; } |
||
1584 | |||
1585 | static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } |
||
1586 | static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } |
||
1587 | static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } |
||
1588 | |||
1589 | #define dev_is_pci(d) (false) |
||
1590 | #define dev_is_pf(d) (false) |
||
1591 | #define dev_num_vf(d) (0) |
||
1592 | #endif /* CONFIG_PCI */ |
||
1593 | |||
1594 | /* Include architecture-dependent settings and functions */ |
||
1595 | |||
1596 | #include |
||
1597 | |||
7143 | serge | 1598 | #ifndef pci_root_bus_fwnode |
1599 | #define pci_root_bus_fwnode(bus) NULL |
||
1600 | #endif |
||
1601 | |||
6102 | serge | 1602 | /* these helpers provide future and backwards compatibility |
1603 | * for accessing popular PCI BAR info */ |
||
1604 | #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
||
1605 | #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
||
1606 | #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
||
1607 | #define pci_resource_len(dev,bar) \ |
||
1608 | ((pci_resource_start((dev), (bar)) == 0 && \ |
||
1609 | pci_resource_end((dev), (bar)) == \ |
||
1610 | pci_resource_start((dev), (bar))) ? 0 : \ |
||
1611 | \ |
||
1612 | (pci_resource_end((dev), (bar)) - \ |
||
1613 | pci_resource_start((dev), (bar)) + 1)) |
||
1614 | |||
1615 | /* Similar to the helpers above, these manipulate per-pci_dev |
||
1616 | * driver-specific data. They are really just a wrapper around |
||
1617 | * the generic device structure functions of these calls. |
||
1618 | */ |
||
1619 | static inline void *pci_get_drvdata(struct pci_dev *pdev) |
||
2161 | serge | 1620 | { |
6102 | serge | 1621 | return dev_get_drvdata(&pdev->dev); |
2161 | serge | 1622 | } |
1623 | |||
6102 | serge | 1624 | static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) |
1625 | { |
||
1626 | dev_set_drvdata(&pdev->dev, data); |
||
1627 | } |
||
1628 | |||
1629 | /* If you want to know what to call your pci_dev, ask this function. |
||
1630 | * Again, it's a wrapper around the generic device. |
||
1631 | */ |
||
1632 | static inline const char *pci_name(const struct pci_dev *pdev) |
||
1633 | { |
||
1634 | return dev_name(&pdev->dev); |
||
1635 | } |
||
1636 | |||
1637 | |||
1638 | /* Some archs don't want to expose struct resource to userland as-is |
||
1639 | * in sysfs and /proc |
||
1640 | */ |
||
1641 | #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER |
||
1642 | static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, |
||
1643 | const struct resource *rsrc, resource_size_t *start, |
||
1644 | resource_size_t *end) |
||
1645 | { |
||
1646 | *start = rsrc->start; |
||
1647 | *end = rsrc->end; |
||
1648 | } |
||
1649 | #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */ |
||
1650 | |||
1651 | |||
1652 | /* |
||
1653 | * The world is not perfect and supplies us with broken PCI devices. |
||
1654 | * For at least a part of these bugs we need a work-around, so both |
||
1655 | * generic (drivers/pci/quirks.c) and per-architecture code can define |
||
1656 | * fixup hooks to be called for particular buggy devices. |
||
1657 | */ |
||
1658 | |||
1659 | struct pci_fixup { |
||
1660 | u16 vendor; /* You can use PCI_ANY_ID here of course */ |
||
1661 | u16 device; /* You can use PCI_ANY_ID here of course */ |
||
1662 | u32 class; /* You can use PCI_ANY_ID here too */ |
||
1663 | unsigned int class_shift; /* should be 0, 8, 16 */ |
||
1664 | void (*hook)(struct pci_dev *dev); |
||
1665 | }; |
||
1666 | |||
1667 | enum pci_fixup_pass { |
||
1668 | pci_fixup_early, /* Before probing BARs */ |
||
1669 | pci_fixup_header, /* After reading configuration header */ |
||
1670 | pci_fixup_final, /* Final phase of device fixups */ |
||
1671 | pci_fixup_enable, /* pci_enable_device() time */ |
||
1672 | pci_fixup_resume, /* pci_device_resume() */ |
||
1673 | pci_fixup_suspend, /* pci_device_suspend() */ |
||
1674 | pci_fixup_resume_early, /* pci_device_resume_early() */ |
||
1675 | pci_fixup_suspend_late, /* pci_device_suspend_late() */ |
||
1676 | }; |
||
1677 | |||
1678 | /* Anonymous variables would be nice... */ |
||
1679 | #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \ |
||
1680 | class_shift, hook) \ |
||
1681 | static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \ |
||
1682 | __attribute__((__section__(#section), aligned((sizeof(void *))))) \ |
||
1683 | = { vendor, device, class, class_shift, hook }; |
||
1684 | |||
1685 | #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \ |
||
1686 | class_shift, hook) \ |
||
1687 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ |
||
1688 | hook, vendor, device, class, class_shift, hook) |
||
1689 | #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \ |
||
1690 | class_shift, hook) \ |
||
1691 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ |
||
1692 | hook, vendor, device, class, class_shift, hook) |
||
1693 | #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \ |
||
1694 | class_shift, hook) \ |
||
1695 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ |
||
1696 | hook, vendor, device, class, class_shift, hook) |
||
1697 | #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \ |
||
1698 | class_shift, hook) \ |
||
1699 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ |
||
1700 | hook, vendor, device, class, class_shift, hook) |
||
1701 | #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ |
||
1702 | class_shift, hook) \ |
||
1703 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ |
||
1704 | resume##hook, vendor, device, class, \ |
||
1705 | class_shift, hook) |
||
1706 | #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ |
||
1707 | class_shift, hook) \ |
||
1708 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ |
||
1709 | resume_early##hook, vendor, device, \ |
||
1710 | class, class_shift, hook) |
||
1711 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ |
||
1712 | class_shift, hook) \ |
||
1713 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ |
||
1714 | suspend##hook, vendor, device, class, \ |
||
1715 | class_shift, hook) |
||
1716 | #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ |
||
1717 | class_shift, hook) \ |
||
1718 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ |
||
1719 | suspend_late##hook, vendor, device, \ |
||
1720 | class, class_shift, hook) |
||
1721 | |||
1722 | #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ |
||
1723 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ |
||
1724 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
||
1725 | #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \ |
||
1726 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \ |
||
1727 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
||
1728 | #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \ |
||
1729 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \ |
||
1730 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
||
1731 | #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \ |
||
1732 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \ |
||
1733 | hook, vendor, device, PCI_ANY_ID, 0, hook) |
||
1734 | #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ |
||
1735 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ |
||
1736 | resume##hook, vendor, device, \ |
||
1737 | PCI_ANY_ID, 0, hook) |
||
1738 | #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ |
||
1739 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ |
||
1740 | resume_early##hook, vendor, device, \ |
||
1741 | PCI_ANY_ID, 0, hook) |
||
1742 | #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ |
||
1743 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ |
||
1744 | suspend##hook, vendor, device, \ |
||
1745 | PCI_ANY_ID, 0, hook) |
||
1746 | #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ |
||
1747 | DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ |
||
1748 | suspend_late##hook, vendor, device, \ |
||
1749 | PCI_ANY_ID, 0, hook) |
||
1750 | |||
1751 | #ifdef CONFIG_PCI_QUIRKS |
||
1752 | void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); |
||
1753 | int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); |
||
1754 | void pci_dev_specific_enable_acs(struct pci_dev *dev); |
||
1755 | #else |
||
1756 | static inline void pci_fixup_device(enum pci_fixup_pass pass, |
||
1757 | struct pci_dev *dev) { } |
||
1758 | static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, |
||
1759 | u16 acs_flags) |
||
1760 | { |
||
1761 | return -ENOTTY; |
||
1762 | } |
||
1763 | static inline void pci_dev_specific_enable_acs(struct pci_dev *dev) { } |
||
1764 | #endif |
||
1765 | |||
1766 | void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); |
||
1767 | void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); |
||
1768 | void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); |
||
1769 | int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name); |
||
1770 | int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask, |
||
1771 | const char *name); |
||
1772 | void pcim_iounmap_regions(struct pci_dev *pdev, int mask); |
||
1773 | |||
1774 | extern int pci_pci_problems; |
||
1775 | #define PCIPCI_FAIL 1 /* No PCI PCI DMA */ |
||
1776 | #define PCIPCI_TRITON 2 |
||
1777 | #define PCIPCI_NATOMA 4 |
||
1778 | #define PCIPCI_VIAETBF 8 |
||
1779 | #define PCIPCI_VSFX 16 |
||
1780 | #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */ |
||
1781 | #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */ |
||
1782 | |||
1783 | extern unsigned long pci_cardbus_io_size; |
||
1784 | extern unsigned long pci_cardbus_mem_size; |
||
1785 | extern u8 pci_dfl_cache_line_size; |
||
1786 | extern u8 pci_cache_line_size; |
||
1787 | |||
1788 | extern unsigned long pci_hotplug_io_size; |
||
1789 | extern unsigned long pci_hotplug_mem_size; |
||
1790 | |||
1791 | /* Architecture-specific versions may override these (weak) */ |
||
1792 | void pcibios_disable_device(struct pci_dev *dev); |
||
1793 | void pcibios_set_master(struct pci_dev *dev); |
||
1794 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, |
||
1795 | enum pcie_reset_state state); |
||
1796 | int pcibios_add_device(struct pci_dev *dev); |
||
1797 | void pcibios_release_device(struct pci_dev *dev); |
||
1798 | void pcibios_penalize_isa_irq(int irq, int active); |
||
1799 | int pcibios_alloc_irq(struct pci_dev *dev); |
||
1800 | void pcibios_free_irq(struct pci_dev *dev); |
||
1801 | |||
1802 | #ifdef CONFIG_HIBERNATE_CALLBACKS |
||
1803 | extern struct dev_pm_ops pcibios_pm_ops; |
||
1804 | #endif |
||
1805 | |||
1806 | #ifdef CONFIG_PCI_MMCONFIG |
||
1807 | void __init pci_mmcfg_early_init(void); |
||
1808 | void __init pci_mmcfg_late_init(void); |
||
1809 | #else |
||
1810 | static inline void pci_mmcfg_early_init(void) { } |
||
1811 | static inline void pci_mmcfg_late_init(void) { } |
||
1812 | #endif |
||
1813 | |||
1814 | int pci_ext_cfg_avail(void); |
||
1815 | |||
1816 | void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar); |
||
1817 | void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar); |
||
1818 | |||
1819 | #ifdef CONFIG_PCI_IOV |
||
1820 | int pci_iov_virtfn_bus(struct pci_dev *dev, int id); |
||
1821 | int pci_iov_virtfn_devfn(struct pci_dev *dev, int id); |
||
1822 | |||
1823 | int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn); |
||
1824 | void pci_disable_sriov(struct pci_dev *dev); |
||
7143 | serge | 1825 | int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset); |
1826 | void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset); |
||
6102 | serge | 1827 | int pci_num_vf(struct pci_dev *dev); |
1828 | int pci_vfs_assigned(struct pci_dev *dev); |
||
1829 | int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs); |
||
1830 | int pci_sriov_get_totalvfs(struct pci_dev *dev); |
||
1831 | resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno); |
||
1832 | #else |
||
1833 | static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id) |
||
1834 | { |
||
1835 | return -ENOSYS; |
||
1836 | } |
||
1837 | static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id) |
||
1838 | { |
||
1839 | return -ENOSYS; |
||
1840 | } |
||
1841 | static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn) |
||
1842 | { return -ENODEV; } |
||
7143 | serge | 1843 | static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset) |
1844 | { |
||
1845 | return -ENOSYS; |
||
1846 | } |
||
1847 | static inline void pci_iov_remove_virtfn(struct pci_dev *dev, |
||
1848 | int id, int reset) { } |
||
6102 | serge | 1849 | static inline void pci_disable_sriov(struct pci_dev *dev) { } |
1850 | static inline int pci_num_vf(struct pci_dev *dev) { return 0; } |
||
1851 | static inline int pci_vfs_assigned(struct pci_dev *dev) |
||
1852 | { return 0; } |
||
1853 | static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs) |
||
1854 | { return 0; } |
||
1855 | static inline int pci_sriov_get_totalvfs(struct pci_dev *dev) |
||
1856 | { return 0; } |
||
1857 | static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno) |
||
1858 | { return 0; } |
||
1859 | #endif |
||
1860 | |||
1861 | #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE) |
||
1862 | void pci_hp_create_module_link(struct pci_slot *pci_slot); |
||
1863 | void pci_hp_remove_module_link(struct pci_slot *pci_slot); |
||
1864 | #endif |
||
1865 | |||
2161 | serge | 1866 | /** |
1867 | * pci_pcie_cap - get the saved PCIe capability offset |
||
1868 | * @dev: PCI device |
||
1869 | * |
||
1870 | * PCIe capability offset is calculated at PCI device initialization |
||
1871 | * time and saved in the data structure. This function returns saved |
||
1872 | * PCIe capability offset. Using this instead of pci_find_capability() |
||
1873 | * reduces unnecessary search in the PCI configuration space. If you |
||
1874 | * need to calculate PCIe capability offset from raw device for some |
||
1875 | * reasons, please use pci_find_capability() instead. |
||
1876 | */ |
||
1877 | static inline int pci_pcie_cap(struct pci_dev *dev) |
||
1878 | { |
||
6102 | serge | 1879 | return dev->pcie_cap; |
2161 | serge | 1880 | } |
1881 | |||
1882 | /** |
||
1883 | * pci_is_pcie - check if the PCI device is PCI Express capable |
||
1884 | * @dev: PCI device |
||
1885 | * |
||
5056 | serge | 1886 | * Returns: true if the PCI device is PCI Express capable, false otherwise. |
2161 | serge | 1887 | */ |
1888 | static inline bool pci_is_pcie(struct pci_dev *dev) |
||
1889 | { |
||
6102 | serge | 1890 | return pci_pcie_cap(dev); |
2161 | serge | 1891 | } |
1892 | |||
3031 | serge | 1893 | /** |
6102 | serge | 1894 | * pcie_caps_reg - get the PCIe Capabilities Register |
1895 | * @dev: PCI device |
||
1896 | */ |
||
1897 | static inline u16 pcie_caps_reg(const struct pci_dev *dev) |
||
1898 | { |
||
1899 | return dev->pcie_flags_reg; |
||
1900 | } |
||
1901 | |||
1902 | /** |
||
3031 | serge | 1903 | * pci_pcie_type - get the PCIe device/port type |
1904 | * @dev: PCI device |
||
1905 | */ |
||
1906 | static inline int pci_pcie_type(const struct pci_dev *dev) |
||
1907 | { |
||
6102 | serge | 1908 | return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; |
3031 | serge | 1909 | } |
1910 | |||
6102 | serge | 1911 | void pci_request_acs(void); |
1912 | bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); |
||
1913 | bool pci_acs_path_enabled(struct pci_dev *start, |
||
1914 | struct pci_dev *end, u16 acs_flags); |
||
3031 | serge | 1915 | |
6102 | serge | 1916 | #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ |
1917 | #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) |
||
1918 | |||
1919 | /* Large Resource Data Type Tag Item Names */ |
||
1920 | #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */ |
||
1921 | #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */ |
||
1922 | #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */ |
||
1923 | |||
1924 | #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING) |
||
1925 | #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA) |
||
1926 | #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA) |
||
1927 | |||
1928 | /* Small Resource Data Type Tag Item Names */ |
||
7143 | serge | 1929 | #define PCI_VPD_STIN_END 0x0f /* End */ |
6102 | serge | 1930 | |
7143 | serge | 1931 | #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3) |
6102 | serge | 1932 | |
1933 | #define PCI_VPD_SRDT_TIN_MASK 0x78 |
||
1934 | #define PCI_VPD_SRDT_LEN_MASK 0x07 |
||
7143 | serge | 1935 | #define PCI_VPD_LRDT_TIN_MASK 0x7f |
6102 | serge | 1936 | |
1937 | #define PCI_VPD_LRDT_TAG_SIZE 3 |
||
1938 | #define PCI_VPD_SRDT_TAG_SIZE 1 |
||
1939 | |||
1940 | #define PCI_VPD_INFO_FLD_HDR_SIZE 3 |
||
1941 | |||
1942 | #define PCI_VPD_RO_KEYWORD_PARTNO "PN" |
||
1943 | #define PCI_VPD_RO_KEYWORD_MFR_ID "MN" |
||
1944 | #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0" |
||
1945 | #define PCI_VPD_RO_KEYWORD_CHKSUM "RV" |
||
1946 | |||
1947 | /** |
||
1948 | * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length |
||
1949 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag |
||
1950 | * |
||
1951 | * Returns the extracted Large Resource Data Type length. |
||
1952 | */ |
||
1953 | static inline u16 pci_vpd_lrdt_size(const u8 *lrdt) |
||
2161 | serge | 1954 | { |
6102 | serge | 1955 | return (u16)lrdt[1] + ((u16)lrdt[2] << 8); |
2161 | serge | 1956 | } |
1957 | |||
6102 | serge | 1958 | /** |
7143 | serge | 1959 | * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item |
1960 | * @lrdt: Pointer to the beginning of the Large Resource Data Type tag |
||
1961 | * |
||
1962 | * Returns the extracted Large Resource Data Type Tag item. |
||
1963 | */ |
||
1964 | static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) |
||
1965 | { |
||
1966 | return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); |
||
1967 | } |
||
1968 | |||
1969 | /** |
||
6102 | serge | 1970 | * pci_vpd_srdt_size - Extracts the Small Resource Data Type length |
1971 | * @lrdt: Pointer to the beginning of the Small Resource Data Type tag |
||
1972 | * |
||
1973 | * Returns the extracted Small Resource Data Type length. |
||
1974 | */ |
||
1975 | static inline u8 pci_vpd_srdt_size(const u8 *srdt) |
||
1976 | { |
||
1977 | return (*srdt) & PCI_VPD_SRDT_LEN_MASK; |
||
1978 | } |
||
2161 | serge | 1979 | |
6102 | serge | 1980 | /** |
7143 | serge | 1981 | * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item |
1982 | * @lrdt: Pointer to the beginning of the Small Resource Data Type tag |
||
1983 | * |
||
1984 | * Returns the extracted Small Resource Data Type Tag Item. |
||
1985 | */ |
||
1986 | static inline u8 pci_vpd_srdt_tag(const u8 *srdt) |
||
1987 | { |
||
1988 | return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3; |
||
1989 | } |
||
1990 | |||
1991 | /** |
||
6102 | serge | 1992 | * pci_vpd_info_field_size - Extracts the information field length |
1993 | * @lrdt: Pointer to the beginning of an information field header |
||
1994 | * |
||
1995 | * Returns the extracted information field length. |
||
1996 | */ |
||
1997 | static inline u8 pci_vpd_info_field_size(const u8 *info_field) |
||
2161 | serge | 1998 | { |
6102 | serge | 1999 | return info_field[2]; |
2161 | serge | 2000 | } |
6102 | serge | 2001 | |
2002 | /** |
||
2003 | * pci_vpd_find_tag - Locates the Resource Data Type tag provided |
||
2004 | * @buf: Pointer to buffered vpd data |
||
2005 | * @off: The offset into the buffer at which to begin the search |
||
2006 | * @len: The length of the vpd buffer |
||
2007 | * @rdt: The Resource Data Type to search for |
||
2008 | * |
||
2009 | * Returns the index where the Resource Data Type was found or |
||
2010 | * -ENOENT otherwise. |
||
2011 | */ |
||
2012 | int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt); |
||
2013 | |||
2014 | /** |
||
2015 | * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD |
||
2016 | * @buf: Pointer to buffered vpd data |
||
2017 | * @off: The offset into the buffer at which to begin the search |
||
2018 | * @len: The length of the buffer area, relative to off, in which to search |
||
2019 | * @kw: The keyword to search for |
||
2020 | * |
||
2021 | * Returns the index where the information field keyword was found or |
||
2022 | * -ENOENT otherwise. |
||
2023 | */ |
||
2024 | int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off, |
||
2025 | unsigned int len, const char *kw); |
||
2026 | |||
2027 | /* PCI <-> OF binding helpers */ |
||
2028 | #ifdef CONFIG_OF |
||
2029 | struct device_node; |
||
2030 | struct irq_domain; |
||
2031 | void pci_set_of_node(struct pci_dev *dev); |
||
2032 | void pci_release_of_node(struct pci_dev *dev); |
||
2033 | void pci_set_bus_of_node(struct pci_bus *bus); |
||
2034 | void pci_release_bus_of_node(struct pci_bus *bus); |
||
2035 | struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); |
||
2036 | |||
2037 | /* Arch may override this (weak) */ |
||
2038 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); |
||
2039 | |||
2040 | static inline struct device_node * |
||
2041 | pci_device_to_OF_node(const struct pci_dev *pdev) |
||
2161 | serge | 2042 | { |
6102 | serge | 2043 | return pdev ? pdev->dev.of_node : NULL; |
2161 | serge | 2044 | } |
6102 | serge | 2045 | |
2046 | static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) |
||
2161 | serge | 2047 | { |
6102 | serge | 2048 | return bus ? bus->dev.of_node : NULL; |
2161 | serge | 2049 | } |
2050 | |||
6102 | serge | 2051 | #else /* CONFIG_OF */ |
2052 | static inline void pci_set_of_node(struct pci_dev *dev) { } |
||
2053 | static inline void pci_release_of_node(struct pci_dev *dev) { } |
||
2054 | static inline void pci_set_bus_of_node(struct pci_bus *bus) { } |
||
2055 | static inline void pci_release_bus_of_node(struct pci_bus *bus) { } |
||
2056 | static inline struct device_node * |
||
2057 | pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } |
||
2058 | static inline struct irq_domain * |
||
2059 | pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } |
||
2060 | #endif /* CONFIG_OF */ |
||
2061 | |||
6936 | serge | 2062 | #ifdef CONFIG_ACPI |
2063 | struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus); |
||
2064 | |||
2065 | void |
||
2066 | pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *)); |
||
2067 | #else |
||
2068 | static inline struct irq_domain * |
||
2069 | pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; } |
||
2070 | #endif |
||
2071 | |||
6102 | serge | 2072 | #ifdef CONFIG_EEH |
2073 | static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev) |
||
2161 | serge | 2074 | { |
6102 | serge | 2075 | return pdev->dev.archdata.edev; |
2161 | serge | 2076 | } |
6102 | serge | 2077 | #endif |
2078 | |||
2079 | int pci_for_each_dma_alias(struct pci_dev *pdev, |
||
2080 | int (*fn)(struct pci_dev *pdev, |
||
2081 | u16 alias, void *data), void *data); |
||
2082 | |||
2083 | /* helper functions for operation of device flag */ |
||
2084 | static inline void pci_set_dev_assigned(struct pci_dev *pdev) |
||
2161 | serge | 2085 | { |
6102 | serge | 2086 | pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; |
2161 | serge | 2087 | } |
6102 | serge | 2088 | static inline void pci_clear_dev_assigned(struct pci_dev *pdev) |
2161 | serge | 2089 | { |
6102 | serge | 2090 | pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED; |
2161 | serge | 2091 | } |
6102 | serge | 2092 | static inline bool pci_is_dev_assigned(struct pci_dev *pdev) |
2161 | serge | 2093 | { |
6102 | serge | 2094 | return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED; |
2161 | serge | 2095 | } |
2096 | |||
6102 | serge | 2097 | /** |
2098 | * pci_ari_enabled - query ARI forwarding status |
||
2099 | * @bus: the PCI bus |
||
2100 | * |
||
2101 | * Returns true if ARI forwarding is enabled. |
||
2102 | */ |
||
2103 | static inline bool pci_ari_enabled(struct pci_bus *bus) |
||
2104 | { |
||
2105 | return bus->self && bus->self->ari_enabled; |
||
2106 | } |
||
2161 | serge | 2107 | |
7143 | serge | 2108 | /* provide the legacy pci_dma_* API */ |
2109 | #include |
||
2110 | |||
1408 | serge | 2111 | typedef struct |
2112 | { |
||
6102 | serge | 2113 | struct list_head link; |
2114 | struct pci_dev pci_dev; |
||
1408 | serge | 2115 | }pci_dev_t; |
2116 | |||
2117 | int enum_pci_devices(void); |
||
2118 | |||
2967 | Serge | 2119 | const struct pci_device_id* |
2120 | find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist); |
||
1408 | serge | 2121 | |
6936 | serge | 2122 | struct pci_dev * _pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); |
2123 | |||
6102 | serge | 2124 | #endif /* LINUX_PCI_H */->><>><>>>><>><>>=>><>><>><>><>><>><>><>><>><>><>><> |