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Rev | Author | Line No. | Line |
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1408 | serge | 1 | /* |
2 | * Defines x86 CPU feature bits |
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3 | */ |
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4 | #ifndef _ASM_X86_CPUFEATURE_H |
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5 | #define _ASM_X86_CPUFEATURE_H |
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6 | |||
7 | #include |
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8 | |||
9 | #define NCAPINTS 9 /* N 32-bit words worth of info */ |
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10 | |||
11 | /* |
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12 | * Note: If the comment begins with a quoted string, that string is used |
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13 | * in /proc/cpuinfo instead of the macro name. If the string is "", |
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14 | * this feature bit is not displayed in /proc/cpuinfo at all. |
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15 | */ |
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16 | |||
17 | /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */ |
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18 | #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */ |
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19 | #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */ |
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20 | #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */ |
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21 | #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */ |
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22 | #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */ |
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23 | #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */ |
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24 | #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */ |
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25 | #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */ |
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26 | #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */ |
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27 | #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */ |
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28 | #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */ |
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29 | #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */ |
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30 | #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */ |
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31 | #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */ |
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32 | #define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */ |
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33 | /* (plus FCMOVcc, FCOMI with FPU) */ |
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34 | #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */ |
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35 | #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */ |
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36 | #define X86_FEATURE_PN (0*32+18) /* Processor serial number */ |
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37 | #define X86_FEATURE_CLFLSH (0*32+19) /* "clflush" CLFLUSH instruction */ |
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38 | #define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */ |
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39 | #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */ |
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40 | #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */ |
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41 | #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */ |
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42 | #define X86_FEATURE_XMM (0*32+25) /* "sse" */ |
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43 | #define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */ |
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44 | #define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */ |
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45 | #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */ |
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46 | #define X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */ |
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47 | #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */ |
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48 | #define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */ |
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49 | |||
50 | /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */ |
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51 | /* Don't duplicate feature flags which are redundant with Intel! */ |
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52 | #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */ |
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53 | #define X86_FEATURE_MP (1*32+19) /* MP Capable. */ |
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54 | #define X86_FEATURE_NX (1*32+20) /* Execute Disable */ |
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55 | #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */ |
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56 | #define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */ |
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57 | #define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */ |
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58 | #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */ |
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59 | #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */ |
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60 | #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */ |
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61 | #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */ |
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62 | |||
63 | /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */ |
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64 | #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */ |
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65 | #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */ |
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66 | #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */ |
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67 | |||
68 | /* Other features, Linux-defined mapping, word 3 */ |
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69 | /* This range is used for feature bits which conflict or are synthesized */ |
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70 | #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */ |
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71 | #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ |
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72 | #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ |
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73 | #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ |
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74 | /* cpu types for specific tunings: */ |
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75 | #define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */ |
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76 | #define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */ |
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77 | #define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */ |
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78 | #define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */ |
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79 | #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */ |
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80 | #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ |
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81 | #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */ |
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82 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ |
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83 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
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84 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
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85 | #define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */ |
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86 | #define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */ |
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87 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */ |
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88 | #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */ |
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89 | #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */ |
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90 | #define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ |
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91 | #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ |
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92 | #define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */ |
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93 | #define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ |
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94 | #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ |
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95 | #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ |
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96 | #define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */ |
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97 | #define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */ |
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98 | #define X86_FEATURE_AMD_DCM (3*32+27) /* multi-node processor */ |
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99 | #define X86_FEATURE_APERFMPERF (3*32+28) /* APERFMPERF */ |
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100 | |||
101 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
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102 | #define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ |
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103 | #define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */ |
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104 | #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */ |
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105 | #define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */ |
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106 | #define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */ |
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107 | #define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */ |
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108 | #define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */ |
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109 | #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */ |
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110 | #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */ |
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111 | #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */ |
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112 | #define X86_FEATURE_CID (4*32+10) /* Context ID */ |
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113 | #define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */ |
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114 | #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ |
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115 | #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ |
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116 | #define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */ |
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117 | #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ |
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118 | #define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */ |
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119 | #define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */ |
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120 | #define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ |
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121 | #define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */ |
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122 | #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ |
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123 | #define X86_FEATURE_AES (4*32+25) /* AES instructions */ |
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124 | #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ |
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125 | #define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ |
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126 | #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ |
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127 | #define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */ |
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128 | |||
129 | /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ |
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130 | #define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */ |
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131 | #define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */ |
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132 | #define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */ |
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133 | #define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */ |
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134 | #define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */ |
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135 | #define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */ |
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136 | #define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */ |
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137 | #define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */ |
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138 | #define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */ |
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139 | #define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */ |
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140 | |||
141 | /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ |
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142 | #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ |
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143 | #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ |
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144 | #define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */ |
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145 | #define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */ |
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146 | #define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */ |
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147 | #define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */ |
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148 | #define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */ |
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149 | #define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */ |
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150 | #define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */ |
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151 | #define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ |
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152 | #define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */ |
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153 | #define X86_FEATURE_SSE5 (6*32+11) /* SSE-5 */ |
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154 | #define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */ |
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155 | #define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ |
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156 | |||
157 | /* |
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158 | * Auxiliary flags: Linux defined - For features scattered in various |
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159 | * CPUID levels like 0x6, 0xA etc |
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160 | */ |
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161 | #define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ |
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162 | #define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */ |
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163 | |||
164 | /* Virtualization flags: Linux defined */ |
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165 | #define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ |
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166 | #define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */ |
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167 | #define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */ |
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168 | #define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */ |
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169 | #define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */ |
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170 | |||
171 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
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172 | |||
173 | #include |
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174 | |||
175 | extern const char * const x86_cap_flags[NCAPINTS*32]; |
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176 | extern const char * const x86_power_flags[32]; |
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177 | |||
178 | #define test_cpu_cap(c, bit) \ |
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179 | test_bit(bit, (unsigned long *)((c)->x86_capability)) |
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180 | |||
181 | #define cpu_has(c, bit) \ |
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182 | (__builtin_constant_p(bit) && \ |
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183 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ |
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184 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ |
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185 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ |
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186 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \ |
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187 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ |
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188 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ |
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189 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ |
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190 | (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \ |
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191 | ? 1 : \ |
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192 | test_cpu_cap(c, bit)) |
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193 | |||
194 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
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195 | |||
196 | #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) |
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197 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) |
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198 | #define setup_clear_cpu_cap(bit) do { \ |
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199 | clear_cpu_cap(&boot_cpu_data, bit); \ |
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200 | set_bit(bit, (unsigned long *)cpu_caps_cleared); \ |
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201 | } while (0) |
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202 | #define setup_force_cpu_cap(bit) do { \ |
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203 | set_cpu_cap(&boot_cpu_data, bit); \ |
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204 | set_bit(bit, (unsigned long *)cpu_caps_set); \ |
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205 | } while (0) |
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206 | |||
207 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
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208 | #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME) |
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209 | #define cpu_has_de boot_cpu_has(X86_FEATURE_DE) |
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210 | #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE) |
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211 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) |
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212 | #define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE) |
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213 | #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) |
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214 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) |
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215 | #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) |
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216 | #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) |
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217 | #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) |
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218 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) |
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219 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) |
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220 | #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) |
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221 | #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) |
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222 | #define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) |
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223 | #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) |
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224 | #define cpu_has_mp boot_cpu_has(X86_FEATURE_MP) |
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225 | #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) |
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226 | #define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR) |
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227 | #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR) |
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228 | #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR) |
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229 | #define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE) |
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230 | #define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN) |
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231 | #define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT) |
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232 | #define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN) |
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233 | #define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2) |
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234 | #define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN) |
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235 | #define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE) |
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236 | #define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN) |
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237 | #define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM) |
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238 | #define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN) |
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239 | #define cpu_has_ds boot_cpu_has(X86_FEATURE_DS) |
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240 | #define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS) |
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241 | #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH) |
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242 | #define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS) |
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243 | #define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES) |
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244 | #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) |
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245 | #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT) |
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246 | #define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1) |
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247 | #define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) |
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248 | #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
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249 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
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250 | #define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) |
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251 | #define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) |
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252 | |||
253 | #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) |
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254 | # define cpu_has_invlpg 1 |
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255 | #else |
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256 | # define cpu_has_invlpg (boot_cpu_data.x86 > 3) |
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257 | #endif |
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258 | |||
259 | #ifdef CONFIG_X86_64 |
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260 | |||
261 | #undef cpu_has_vme |
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262 | #define cpu_has_vme 0 |
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263 | |||
264 | #undef cpu_has_pae |
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265 | #define cpu_has_pae ___BUG___ |
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266 | |||
267 | #undef cpu_has_mp |
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268 | #define cpu_has_mp 1 |
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269 | |||
270 | #undef cpu_has_k6_mtrr |
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271 | #define cpu_has_k6_mtrr 0 |
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272 | |||
273 | #undef cpu_has_cyrix_arr |
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274 | #define cpu_has_cyrix_arr 0 |
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275 | |||
276 | #undef cpu_has_centaur_mcr |
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277 | #define cpu_has_centaur_mcr 0 |
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278 | |||
279 | #endif /* CONFIG_X86_64 */ |
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280 | |||
281 | #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ |
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282 | |||
283 | #endif /* _ASM_X86_CPUFEATURE_H */((bit)&31)><((bit)&31)>((bit)&31)><((bit)&31)>((bit)&31)><((bit)&31)>((bit)&31)><((bit)&31)>((bit)&31)><((bit)&31)>((bit)&31)><((bit)&31)>((bit)&31)><((bit)&31)>((bit)&31)><((bit)&31)> |