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1408 | serge | 1 | /* |
2 | * Copyright © 2008 Keith Packard |
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3 | * |
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4 | * Permission to use, copy, modify, distribute, and sell this software and its |
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5 | * documentation for any purpose is hereby granted without fee, provided that |
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6 | * the above copyright notice appear in all copies and that both that copyright |
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7 | * notice and this permission notice appear in supporting documentation, and |
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8 | * that the name of the copyright holders not be used in advertising or |
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9 | * publicity pertaining to distribution of the software without specific, |
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10 | * written prior permission. The copyright holders make no representations |
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11 | * about the suitability of this software for any purpose. It is provided "as |
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12 | * is" without express or implied warranty. |
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13 | * |
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14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, |
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15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO |
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16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR |
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17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, |
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18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
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19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE |
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20 | * OF THIS SOFTWARE. |
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21 | */ |
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22 | |||
23 | #ifndef _DRM_DP_HELPER_H_ |
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24 | #define _DRM_DP_HELPER_H_ |
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25 | |||
1964 | serge | 26 | #include |
27 | #include |
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3192 | Serge | 28 | #include |
1964 | serge | 29 | |
3031 | serge | 30 | /* |
31 | * Unless otherwise noted, all values are from the DP 1.1a spec. Note that |
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32 | * DP and DPCD versions are independent. Differences from 1.0 are not noted, |
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33 | * 1.0 devices basically don't exist in the wild. |
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34 | * |
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35 | * Abbreviations, in chronological order: |
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36 | * |
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37 | * eDP: Embedded DisplayPort version 1 |
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38 | * DPI: DisplayPort Interoperability Guideline v1.1a |
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39 | * 1.2: DisplayPort 1.2 |
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5056 | serge | 40 | * MST: Multistream Transport - part of DP 1.2a |
3031 | serge | 41 | * |
42 | * 1.2 formally includes both eDP and DPI definitions. |
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43 | */ |
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1408 | serge | 44 | |
4559 | Serge | 45 | #define DP_AUX_I2C_WRITE 0x0 |
46 | #define DP_AUX_I2C_READ 0x1 |
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47 | #define DP_AUX_I2C_STATUS 0x2 |
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48 | #define DP_AUX_I2C_MOT 0x4 |
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49 | #define DP_AUX_NATIVE_WRITE 0x8 |
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50 | #define DP_AUX_NATIVE_READ 0x9 |
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1408 | serge | 51 | |
4559 | Serge | 52 | #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) |
53 | #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) |
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54 | #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) |
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55 | #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) |
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1408 | serge | 56 | |
4559 | Serge | 57 | #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) |
58 | #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) |
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59 | #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) |
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60 | #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) |
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1408 | serge | 61 | |
62 | /* AUX CH addresses */ |
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63 | /* DPCD */ |
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64 | #define DP_DPCD_REV 0x000 |
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65 | |||
66 | #define DP_MAX_LINK_RATE 0x001 |
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67 | |||
68 | #define DP_MAX_LANE_COUNT 0x002 |
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69 | # define DP_MAX_LANE_COUNT_MASK 0x1f |
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3031 | serge | 70 | # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ |
1408 | serge | 71 | # define DP_ENHANCED_FRAME_CAP (1 << 7) |
72 | |||
73 | #define DP_MAX_DOWNSPREAD 0x003 |
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74 | # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) |
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75 | |||
76 | #define DP_NORP 0x004 |
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77 | |||
78 | #define DP_DOWNSTREAMPORT_PRESENT 0x005 |
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79 | # define DP_DWN_STRM_PORT_PRESENT (1 << 0) |
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80 | # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 |
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4559 | Serge | 81 | # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) |
82 | # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) |
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83 | # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) |
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84 | # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) |
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1408 | serge | 85 | # define DP_FORMAT_CONVERSION (1 << 3) |
3031 | serge | 86 | # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
1408 | serge | 87 | |
88 | #define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
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89 | |||
3031 | serge | 90 | #define DP_DOWN_STREAM_PORT_COUNT 0x007 |
91 | # define DP_PORT_COUNT_MASK 0x0f |
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92 | # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
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93 | # define DP_OUI_SUPPORT (1 << 7) |
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1964 | serge | 94 | |
3031 | serge | 95 | #define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
96 | # define DP_I2C_SPEED_1K 0x01 |
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97 | # define DP_I2C_SPEED_5K 0x02 |
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98 | # define DP_I2C_SPEED_10K 0x04 |
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99 | # define DP_I2C_SPEED_100K 0x08 |
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100 | # define DP_I2C_SPEED_400K 0x10 |
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101 | # define DP_I2C_SPEED_1M 0x20 |
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102 | |||
103 | #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
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104 | #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
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105 | |||
106 | /* Multiple stream transport */ |
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5056 | serge | 107 | #define DP_FAUX_CAP 0x020 /* 1.2 */ |
108 | # define DP_FAUX_CAP_1 (1 << 0) |
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109 | |||
3031 | serge | 110 | #define DP_MSTM_CAP 0x021 /* 1.2 */ |
111 | # define DP_MST_CAP (1 << 0) |
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112 | |||
5056 | serge | 113 | #define DP_GUID 0x030 /* 1.2 */ |
114 | |||
3031 | serge | 115 | #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ |
2967 | Serge | 116 | # define DP_PSR_IS_SUPPORTED 1 |
3031 | serge | 117 | #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ |
2967 | Serge | 118 | # define DP_PSR_NO_TRAIN_ON_EXIT 1 |
119 | # define DP_PSR_SETUP_TIME_330 (0 << 1) |
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120 | # define DP_PSR_SETUP_TIME_275 (1 << 1) |
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121 | # define DP_PSR_SETUP_TIME_220 (2 << 1) |
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122 | # define DP_PSR_SETUP_TIME_165 (3 << 1) |
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123 | # define DP_PSR_SETUP_TIME_110 (4 << 1) |
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124 | # define DP_PSR_SETUP_TIME_55 (5 << 1) |
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125 | # define DP_PSR_SETUP_TIME_0 (6 << 1) |
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126 | # define DP_PSR_SETUP_TIME_MASK (7 << 1) |
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127 | # define DP_PSR_SETUP_TIME_SHIFT 1 |
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128 | |||
3031 | serge | 129 | /* |
130 | * 0x80-0x8f describe downstream port capabilities, but there are two layouts |
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131 | * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, |
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132 | * each port's descriptor is one byte wide. If it was set, each port's is |
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133 | * four bytes wide, starting with the one byte from the base info. As of |
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134 | * DP interop v1.1a only VGA defines additional detail. |
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135 | */ |
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136 | |||
137 | /* offset 0 */ |
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138 | #define DP_DOWNSTREAM_PORT_0 0x80 |
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139 | # define DP_DS_PORT_TYPE_MASK (7 << 0) |
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140 | # define DP_DS_PORT_TYPE_DP 0 |
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141 | # define DP_DS_PORT_TYPE_VGA 1 |
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142 | # define DP_DS_PORT_TYPE_DVI 2 |
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143 | # define DP_DS_PORT_TYPE_HDMI 3 |
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144 | # define DP_DS_PORT_TYPE_NON_EDID 4 |
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145 | # define DP_DS_PORT_HPD (1 << 3) |
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146 | /* offset 1 for VGA is maximum megapixels per second / 8 */ |
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147 | /* offset 2 */ |
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148 | # define DP_DS_VGA_MAX_BPC_MASK (3 << 0) |
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149 | # define DP_DS_VGA_8BPC 0 |
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150 | # define DP_DS_VGA_10BPC 1 |
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151 | # define DP_DS_VGA_12BPC 2 |
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152 | # define DP_DS_VGA_16BPC 3 |
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153 | |||
1408 | serge | 154 | /* link configuration */ |
155 | #define DP_LINK_BW_SET 0x100 |
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156 | # define DP_LINK_BW_1_62 0x06 |
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157 | # define DP_LINK_BW_2_7 0x0a |
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3031 | serge | 158 | # define DP_LINK_BW_5_4 0x14 /* 1.2 */ |
1408 | serge | 159 | |
160 | #define DP_LANE_COUNT_SET 0x101 |
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161 | # define DP_LANE_COUNT_MASK 0x0f |
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162 | # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) |
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163 | |||
164 | #define DP_TRAINING_PATTERN_SET 0x102 |
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165 | # define DP_TRAINING_PATTERN_DISABLE 0 |
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166 | # define DP_TRAINING_PATTERN_1 1 |
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167 | # define DP_TRAINING_PATTERN_2 2 |
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3031 | serge | 168 | # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ |
1408 | serge | 169 | # define DP_TRAINING_PATTERN_MASK 0x3 |
170 | |||
171 | # define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) |
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172 | # define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) |
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173 | # define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) |
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174 | # define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) |
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175 | # define DP_LINK_QUAL_PATTERN_MASK (3 << 2) |
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176 | |||
177 | # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) |
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178 | # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) |
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179 | |||
180 | # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) |
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181 | # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) |
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182 | # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) |
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183 | # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) |
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184 | |||
185 | #define DP_TRAINING_LANE0_SET 0x103 |
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186 | #define DP_TRAINING_LANE1_SET 0x104 |
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187 | #define DP_TRAINING_LANE2_SET 0x105 |
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188 | #define DP_TRAINING_LANE3_SET 0x106 |
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189 | |||
190 | # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 |
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191 | # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 |
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192 | # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) |
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193 | # define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) |
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194 | # define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) |
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195 | # define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) |
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196 | # define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) |
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197 | |||
198 | # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) |
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199 | # define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) |
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200 | # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) |
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201 | # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) |
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202 | # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) |
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203 | |||
204 | # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 |
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205 | # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) |
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206 | |||
207 | #define DP_DOWNSPREAD_CTRL 0x107 |
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208 | # define DP_SPREAD_AMP_0_5 (1 << 4) |
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3031 | serge | 209 | # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ |
1408 | serge | 210 | |
211 | #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
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212 | # define DP_SET_ANSI_8B10B (1 << 0) |
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213 | |||
3031 | serge | 214 | #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ |
215 | /* bitmask as for DP_I2C_SPEED_CAP */ |
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216 | |||
217 | #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ |
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218 | |||
219 | #define DP_MSTM_CTRL 0x111 /* 1.2 */ |
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220 | # define DP_MST_EN (1 << 0) |
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221 | # define DP_UP_REQ_EN (1 << 1) |
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222 | # define DP_UPSTREAM_IS_SRC (1 << 2) |
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223 | |||
224 | #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
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2967 | Serge | 225 | # define DP_PSR_ENABLE (1 << 0) |
226 | # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
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227 | # define DP_PSR_CRC_VERIFICATION (1 << 2) |
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228 | # define DP_PSR_FRAME_CAPTURE (1 << 3) |
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229 | |||
5056 | serge | 230 | #define DP_ADAPTER_CTRL 0x1a0 |
231 | # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) |
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232 | |||
233 | #define DP_BRANCH_DEVICE_CTRL 0x1a1 |
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234 | # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) |
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235 | |||
236 | #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 |
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237 | #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 |
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238 | #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 |
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239 | |||
3031 | serge | 240 | #define DP_SINK_COUNT 0x200 |
241 | /* prior to 1.2 bit 7 was reserved mbz */ |
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242 | # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) |
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243 | # define DP_SINK_CP_READY (1 << 6) |
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244 | |||
2967 | Serge | 245 | #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
246 | # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) |
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247 | # define DP_AUTOMATED_TEST_REQUEST (1 << 1) |
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248 | # define DP_CP_IRQ (1 << 2) |
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5056 | serge | 249 | # define DP_MCCS_IRQ (1 << 3) |
250 | # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ |
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251 | # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ |
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2967 | Serge | 252 | # define DP_SINK_SPECIFIC_IRQ (1 << 6) |
253 | |||
1408 | serge | 254 | #define DP_LANE0_1_STATUS 0x202 |
255 | #define DP_LANE2_3_STATUS 0x203 |
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256 | # define DP_LANE_CR_DONE (1 << 0) |
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257 | # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) |
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258 | # define DP_LANE_SYMBOL_LOCKED (1 << 2) |
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259 | |||
260 | #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ |
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261 | DP_LANE_CHANNEL_EQ_DONE | \ |
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262 | DP_LANE_SYMBOL_LOCKED) |
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263 | |||
264 | #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 |
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265 | |||
266 | #define DP_INTERLANE_ALIGN_DONE (1 << 0) |
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267 | #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) |
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268 | #define DP_LINK_STATUS_UPDATED (1 << 7) |
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269 | |||
270 | #define DP_SINK_STATUS 0x205 |
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271 | |||
272 | #define DP_RECEIVE_PORT_0_STATUS (1 << 0) |
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273 | #define DP_RECEIVE_PORT_1_STATUS (1 << 1) |
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274 | |||
275 | #define DP_ADJUST_REQUEST_LANE0_1 0x206 |
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276 | #define DP_ADJUST_REQUEST_LANE2_3 0x207 |
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277 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 |
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278 | # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 |
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279 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c |
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280 | # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 |
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281 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 |
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282 | # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 |
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283 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 |
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284 | # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 |
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285 | |||
2967 | Serge | 286 | #define DP_TEST_REQUEST 0x218 |
287 | # define DP_TEST_LINK_TRAINING (1 << 0) |
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4559 | Serge | 288 | # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) |
2967 | Serge | 289 | # define DP_TEST_LINK_EDID_READ (1 << 2) |
290 | # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ |
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4559 | Serge | 291 | # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ |
2967 | Serge | 292 | |
293 | #define DP_TEST_LINK_RATE 0x219 |
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294 | # define DP_LINK_RATE_162 (0x6) |
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295 | # define DP_LINK_RATE_27 (0xa) |
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296 | |||
297 | #define DP_TEST_LANE_COUNT 0x220 |
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298 | |||
299 | #define DP_TEST_PATTERN 0x221 |
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300 | |||
5056 | serge | 301 | #define DP_TEST_CRC_R_CR 0x240 |
302 | #define DP_TEST_CRC_G_Y 0x242 |
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303 | #define DP_TEST_CRC_B_CB 0x244 |
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304 | |||
305 | #define DP_TEST_SINK_MISC 0x246 |
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306 | #define DP_TEST_CRC_SUPPORTED (1 << 5) |
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307 | |||
2967 | Serge | 308 | #define DP_TEST_RESPONSE 0x260 |
309 | # define DP_TEST_ACK (1 << 0) |
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310 | # define DP_TEST_NAK (1 << 1) |
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311 | # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) |
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312 | |||
5056 | serge | 313 | #define DP_TEST_EDID_CHECKSUM 0x261 |
314 | |||
315 | #define DP_TEST_SINK 0x270 |
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316 | #define DP_TEST_SINK_START (1 << 0) |
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317 | |||
318 | #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ |
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319 | # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) |
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320 | # define DP_PAYLOAD_ACT_HANDLED (1 << 1) |
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321 | |||
322 | #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ |
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323 | /* up to ID_SLOT_63 at 0x2ff */ |
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324 | |||
3031 | serge | 325 | #define DP_SOURCE_OUI 0x300 |
326 | #define DP_SINK_OUI 0x400 |
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327 | #define DP_BRANCH_OUI 0x500 |
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328 | |||
1408 | serge | 329 | #define DP_SET_POWER 0x600 |
330 | # define DP_SET_POWER_D0 0x1 |
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331 | # define DP_SET_POWER_D3 0x2 |
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5056 | serge | 332 | # define DP_SET_POWER_MASK 0x3 |
1408 | serge | 333 | |
5056 | serge | 334 | #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ |
335 | #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ |
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336 | #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ |
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337 | #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ |
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338 | |||
339 | #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ |
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340 | /* 0-5 sink count */ |
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341 | # define DP_SINK_COUNT_CP_READY (1 << 6) |
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342 | |||
343 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ |
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344 | |||
345 | #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ |
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346 | |||
347 | #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ |
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348 | |||
3031 | serge | 349 | #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ |
2967 | Serge | 350 | # define DP_PSR_LINK_CRC_ERROR (1 << 0) |
351 | # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) |
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352 | |||
3031 | serge | 353 | #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ |
2967 | Serge | 354 | # define DP_PSR_CAPS_CHANGE (1 << 0) |
355 | |||
3031 | serge | 356 | #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ |
2967 | Serge | 357 | # define DP_PSR_SINK_INACTIVE 0 |
358 | # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 |
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359 | # define DP_PSR_SINK_ACTIVE_RFB 2 |
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360 | # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 |
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361 | # define DP_PSR_SINK_ACTIVE_RESYNC 4 |
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362 | # define DP_PSR_SINK_INTERNAL_ERROR 7 |
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363 | # define DP_PSR_SINK_STATE_MASK 0x07 |
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364 | |||
5056 | serge | 365 | /* DP 1.2 Sideband message defines */ |
366 | /* peer device type - DP 1.2a Table 2-92 */ |
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367 | #define DP_PEER_DEVICE_NONE 0x0 |
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368 | #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 |
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369 | #define DP_PEER_DEVICE_MST_BRANCHING 0x2 |
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370 | #define DP_PEER_DEVICE_SST_SINK 0x3 |
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371 | #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 |
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372 | |||
373 | /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ |
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374 | #define DP_LINK_ADDRESS 0x01 |
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375 | #define DP_CONNECTION_STATUS_NOTIFY 0x02 |
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376 | #define DP_ENUM_PATH_RESOURCES 0x10 |
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377 | #define DP_ALLOCATE_PAYLOAD 0x11 |
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378 | #define DP_QUERY_PAYLOAD 0x12 |
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379 | #define DP_RESOURCE_STATUS_NOTIFY 0x13 |
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380 | #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 |
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381 | #define DP_REMOTE_DPCD_READ 0x20 |
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382 | #define DP_REMOTE_DPCD_WRITE 0x21 |
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383 | #define DP_REMOTE_I2C_READ 0x22 |
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384 | #define DP_REMOTE_I2C_WRITE 0x23 |
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385 | #define DP_POWER_UP_PHY 0x24 |
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386 | #define DP_POWER_DOWN_PHY 0x25 |
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387 | #define DP_SINK_EVENT_NOTIFY 0x30 |
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388 | #define DP_QUERY_STREAM_ENC_STATUS 0x38 |
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389 | |||
390 | /* DP 1.2 MST sideband nak reasons - table 2.84 */ |
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391 | #define DP_NAK_WRITE_FAILURE 0x01 |
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392 | #define DP_NAK_INVALID_READ 0x02 |
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393 | #define DP_NAK_CRC_FAILURE 0x03 |
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394 | #define DP_NAK_BAD_PARAM 0x04 |
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395 | #define DP_NAK_DEFER 0x05 |
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396 | #define DP_NAK_LINK_FAILURE 0x06 |
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397 | #define DP_NAK_NO_RESOURCES 0x07 |
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398 | #define DP_NAK_DPCD_FAIL 0x08 |
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399 | #define DP_NAK_I2C_NAK 0x09 |
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400 | #define DP_NAK_ALLOCATE_FAIL 0x0a |
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401 | |||
1408 | serge | 402 | #define MODE_I2C_START 1 |
403 | #define MODE_I2C_WRITE 2 |
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404 | #define MODE_I2C_READ 4 |
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405 | #define MODE_I2C_STOP 8 |
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406 | |||
3192 | Serge | 407 | /** |
408 | * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp |
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409 | * aux algorithm |
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410 | * @running: set by the algo indicating whether an i2c is ongoing or whether |
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411 | * the i2c bus is quiescent |
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412 | * @address: i2c target address for the currently ongoing transfer |
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413 | * @aux_ch: driver callback to transfer a single byte of the i2c payload |
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414 | */ |
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1408 | serge | 415 | struct i2c_algo_dp_aux_data { |
416 | bool running; |
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417 | u16 address; |
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418 | int (*aux_ch) (struct i2c_adapter *adapter, |
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419 | int mode, uint8_t write_byte, |
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420 | uint8_t *read_byte); |
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421 | }; |
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422 | |||
423 | int |
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424 | i2c_dp_aux_add_bus(struct i2c_adapter *adapter); |
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425 | |||
3192 | Serge | 426 | |
427 | #define DP_LINK_STATUS_SIZE 6 |
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4559 | Serge | 428 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
3192 | Serge | 429 | int lane_count); |
4559 | Serge | 430 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
3192 | Serge | 431 | int lane_count); |
4559 | Serge | 432 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
3192 | Serge | 433 | int lane); |
4559 | Serge | 434 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
3192 | Serge | 435 | int lane); |
436 | |||
437 | #define DP_RECEIVER_CAP_SIZE 0xf |
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4103 | Serge | 438 | #define EDP_PSR_RECEIVER_CAP_SIZE 2 |
439 | |||
4559 | Serge | 440 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
441 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
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3192 | Serge | 442 | |
443 | u8 drm_dp_link_rate_to_bw_code(int link_rate); |
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444 | int drm_dp_bw_code_to_link_rate(u8 link_bw); |
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445 | |||
4103 | Serge | 446 | struct edp_sdp_header { |
447 | u8 HB0; /* Secondary Data Packet ID */ |
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448 | u8 HB1; /* Secondary Data Packet Type */ |
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449 | u8 HB2; /* 7:5 reserved, 4:0 revision number */ |
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450 | u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ |
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451 | } __packed; |
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452 | |||
453 | #define EDP_SDP_HEADER_REVISION_MASK 0x1F |
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454 | #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F |
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455 | |||
456 | struct edp_vsc_psr { |
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457 | struct edp_sdp_header sdp_header; |
||
458 | u8 DB0; /* Stereo Interface */ |
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459 | u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ |
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460 | u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ |
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461 | u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ |
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462 | u8 DB4; /* CRC value bits 7:0 of the G or Y component */ |
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463 | u8 DB5; /* CRC value bits 15:8 of the G or Y component */ |
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464 | u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ |
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465 | u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ |
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466 | u8 DB8_31[24]; /* Reserved */ |
||
467 | } __packed; |
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468 | |||
469 | #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) |
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470 | #define EDP_VSC_PSR_UPDATE_RFB (1<<1) |
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471 | #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) |
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472 | |||
3192 | Serge | 473 | static inline int |
4559 | Serge | 474 | drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
3192 | Serge | 475 | { |
476 | return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); |
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477 | } |
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478 | |||
479 | static inline u8 |
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4559 | Serge | 480 | drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
3192 | Serge | 481 | { |
482 | return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; |
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483 | } |
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484 | |||
4559 | Serge | 485 | static inline bool |
486 | drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) |
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487 | { |
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488 | return dpcd[DP_DPCD_REV] >= 0x11 && |
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489 | (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); |
||
490 | } |
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491 | |||
5056 | serge | 492 | /* |
493 | * DisplayPort AUX channel |
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494 | */ |
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495 | |||
496 | /** |
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497 | * struct drm_dp_aux_msg - DisplayPort AUX channel transaction |
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498 | * @address: address of the (first) register to access |
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499 | * @request: contains the type of transaction (see DP_AUX_* macros) |
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500 | * @reply: upon completion, contains the reply type of the transaction |
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501 | * @buffer: pointer to a transmission or reception buffer |
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502 | * @size: size of @buffer |
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503 | */ |
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504 | struct drm_dp_aux_msg { |
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505 | unsigned int address; |
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506 | u8 request; |
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507 | u8 reply; |
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508 | void *buffer; |
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509 | size_t size; |
||
510 | }; |
||
511 | |||
512 | /** |
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513 | * struct drm_dp_aux - DisplayPort AUX channel |
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514 | * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter |
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515 | * @ddc: I2C adapter that can be used for I2C-over-AUX communication |
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516 | * @dev: pointer to struct device that is the parent for this AUX channel |
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517 | * @hw_mutex: internal mutex used for locking transfers |
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518 | * @transfer: transfers a message representing a single AUX transaction |
||
519 | * |
||
520 | * The .dev field should be set to a pointer to the device that implements |
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521 | * the AUX channel. |
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522 | * |
||
523 | * The .name field may be used to specify the name of the I2C adapter. If set to |
||
524 | * NULL, dev_name() of .dev will be used. |
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525 | * |
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526 | * Drivers provide a hardware-specific implementation of how transactions |
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527 | * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg |
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528 | * structure describing the transaction is passed into this function. Upon |
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529 | * success, the implementation should return the number of payload bytes |
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530 | * that were transferred, or a negative error-code on failure. Helpers |
||
531 | * propagate errors from the .transfer() function, with the exception of |
||
532 | * the -EBUSY error, which causes a transaction to be retried. On a short, |
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533 | * helpers will return -EPROTO to make it simpler to check for failure. |
||
534 | * |
||
535 | * An AUX channel can also be used to transport I2C messages to a sink. A |
||
536 | * typical application of that is to access an EDID that's present in the |
||
537 | * sink device. The .transfer() function can also be used to execute such |
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538 | * transactions. The drm_dp_aux_register_i2c_bus() function registers an |
||
539 | * I2C adapter that can be passed to drm_probe_ddc(). Upon removal, drivers |
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540 | * should call drm_dp_aux_unregister_i2c_bus() to remove the I2C adapter. |
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541 | * |
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542 | * Note that the aux helper code assumes that the .transfer() function |
||
543 | * only modifies the reply field of the drm_dp_aux_msg structure. The |
||
544 | * retry logic and i2c helpers assume this is the case. |
||
545 | */ |
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546 | struct drm_dp_aux { |
||
547 | const char *name; |
||
548 | struct i2c_adapter ddc; |
||
549 | struct device *dev; |
||
550 | struct mutex hw_mutex; |
||
551 | ssize_t (*transfer)(struct drm_dp_aux *aux, |
||
552 | struct drm_dp_aux_msg *msg); |
||
553 | }; |
||
554 | |||
555 | ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, |
||
556 | void *buffer, size_t size); |
||
557 | ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, |
||
558 | void *buffer, size_t size); |
||
559 | |||
560 | /** |
||
561 | * drm_dp_dpcd_readb() - read a single byte from the DPCD |
||
562 | * @aux: DisplayPort AUX channel |
||
563 | * @offset: address of the register to read |
||
564 | * @valuep: location where the value of the register will be stored |
||
565 | * |
||
566 | * Returns the number of bytes transferred (1) on success, or a negative |
||
567 | * error code on failure. |
||
568 | */ |
||
569 | static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, |
||
570 | unsigned int offset, u8 *valuep) |
||
571 | { |
||
572 | return drm_dp_dpcd_read(aux, offset, valuep, 1); |
||
573 | } |
||
574 | |||
575 | /** |
||
576 | * drm_dp_dpcd_writeb() - write a single byte to the DPCD |
||
577 | * @aux: DisplayPort AUX channel |
||
578 | * @offset: address of the register to write |
||
579 | * @value: value to write to the register |
||
580 | * |
||
581 | * Returns the number of bytes transferred (1) on success, or a negative |
||
582 | * error code on failure. |
||
583 | */ |
||
584 | static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, |
||
585 | unsigned int offset, u8 value) |
||
586 | { |
||
587 | return drm_dp_dpcd_write(aux, offset, &value, 1); |
||
588 | } |
||
589 | |||
590 | int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, |
||
591 | u8 status[DP_LINK_STATUS_SIZE]); |
||
592 | |||
593 | /* |
||
594 | * DisplayPort link |
||
595 | */ |
||
596 | #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) |
||
597 | |||
598 | struct drm_dp_link { |
||
599 | unsigned char revision; |
||
600 | unsigned int rate; |
||
601 | unsigned int num_lanes; |
||
602 | unsigned long capabilities; |
||
603 | }; |
||
604 | |||
605 | int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); |
||
606 | int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); |
||
607 | int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); |
||
608 | |||
609 | int drm_dp_aux_register(struct drm_dp_aux *aux); |
||
610 | void drm_dp_aux_unregister(struct drm_dp_aux *aux); |
||
611 | |||
1408 | serge | 612 | #endif /* _DRM_DP_HELPER_H_ */><>2) |