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5270 | serge | 1 | #ifndef _ASM_X86_PROCESSOR_H |
2 | #define _ASM_X86_PROCESSOR_H |
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3 | |||
4 | #include |
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5 | |||
6 | /* Forward declaration, a strange C thing */ |
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7 | struct task_struct; |
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8 | struct mm_struct; |
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6082 | serge | 9 | struct vm86; |
5270 | serge | 10 | |
11 | #include |
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12 | #include |
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13 | #include |
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6082 | serge | 14 | #include |
5270 | serge | 15 | #include |
16 | #include |
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17 | #include |
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18 | #include |
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19 | #include |
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20 | #include |
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21 | #include |
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22 | #include |
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23 | #include |
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6082 | serge | 24 | #include |
5270 | serge | 25 | |
26 | #include |
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27 | #include |
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28 | #include |
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29 | #include |
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30 | #include |
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31 | #include |
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32 | #include |
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33 | |||
34 | /* |
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35 | * We handle most unaligned accesses in hardware. On the other hand |
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36 | * unaligned DMA can be quite expensive on some Nehalem processors. |
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37 | * |
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38 | * Based on this we disable the IP header alignment in network drivers. |
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39 | */ |
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40 | #define NET_IP_ALIGN 0 |
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41 | |||
42 | #define HBP_NUM 4 |
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43 | /* |
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44 | * Default implementation of macro that returns current |
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45 | * instruction pointer ("program counter"). |
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46 | */ |
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47 | static inline void *current_text_addr(void) |
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48 | { |
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49 | void *pc; |
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50 | |||
51 | asm volatile("mov $1f, %0; 1:":"=r" (pc)); |
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52 | |||
53 | return pc; |
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54 | } |
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55 | |||
6082 | serge | 56 | /* |
57 | * These alignment constraints are for performance in the vSMP case, |
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58 | * but in the task_struct case we must also meet hardware imposed |
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59 | * alignment requirements of the FPU state: |
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60 | */ |
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5270 | serge | 61 | #ifdef CONFIG_X86_VSMP |
62 | # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT) |
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63 | # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT) |
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64 | #else |
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65 | # define ARCH_MIN_TASKALIGN 16 |
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66 | # define ARCH_MIN_MMSTRUCT_ALIGN 0 |
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67 | #endif |
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68 | |||
69 | enum tlb_infos { |
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70 | ENTRIES, |
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71 | NR_INFO |
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72 | }; |
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73 | |||
74 | extern u16 __read_mostly tlb_lli_4k[NR_INFO]; |
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75 | extern u16 __read_mostly tlb_lli_2m[NR_INFO]; |
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76 | extern u16 __read_mostly tlb_lli_4m[NR_INFO]; |
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77 | extern u16 __read_mostly tlb_lld_4k[NR_INFO]; |
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78 | extern u16 __read_mostly tlb_lld_2m[NR_INFO]; |
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79 | extern u16 __read_mostly tlb_lld_4m[NR_INFO]; |
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80 | extern u16 __read_mostly tlb_lld_1g[NR_INFO]; |
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81 | |||
82 | /* |
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83 | * CPU type and hardware bug flags. Kept separately for each CPU. |
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84 | * Members of this structure are referenced in head.S, so think twice |
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85 | * before touching them. [mj] |
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86 | */ |
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87 | |||
88 | struct cpuinfo_x86 { |
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89 | __u8 x86; /* CPU family */ |
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90 | __u8 x86_vendor; /* CPU vendor */ |
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91 | __u8 x86_model; |
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92 | __u8 x86_mask; |
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93 | #ifdef CONFIG_X86_32 |
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94 | char wp_works_ok; /* It doesn't on 386's */ |
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95 | |||
96 | /* Problems on some 486Dx4's and old 386's: */ |
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97 | char rfu; |
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98 | char pad0; |
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99 | char pad1; |
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100 | #else |
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101 | /* Number of 4K pages in DTLB/ITLB combined(in pages): */ |
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102 | int x86_tlbsize; |
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103 | #endif |
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104 | __u8 x86_virt_bits; |
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105 | __u8 x86_phys_bits; |
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106 | /* CPUID returned core id bits: */ |
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107 | __u8 x86_coreid_bits; |
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108 | /* Max extended CPUID function supported: */ |
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109 | __u32 extended_cpuid_level; |
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110 | /* Maximum supported CPUID level, -1=no CPUID: */ |
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111 | int cpuid_level; |
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112 | __u32 x86_capability[NCAPINTS + NBUGINTS]; |
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113 | char x86_vendor_id[16]; |
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114 | char x86_model_id[64]; |
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115 | /* in KB - valid for CPUS which support this call: */ |
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116 | int x86_cache_size; |
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117 | int x86_cache_alignment; /* In bytes */ |
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6082 | serge | 118 | /* Cache QoS architectural values: */ |
119 | int x86_cache_max_rmid; /* max index */ |
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120 | int x86_cache_occ_scale; /* scale to bytes */ |
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5270 | serge | 121 | int x86_power; |
122 | unsigned long loops_per_jiffy; |
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123 | /* cpuid returned max cores value: */ |
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124 | u16 x86_max_cores; |
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125 | u16 apicid; |
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126 | u16 initial_apicid; |
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127 | u16 x86_clflush_size; |
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128 | /* number of cores as seen by the OS: */ |
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129 | u16 booted_cores; |
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130 | /* Physical processor id: */ |
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131 | u16 phys_proc_id; |
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132 | /* Core id: */ |
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133 | u16 cpu_core_id; |
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134 | /* Compute unit id */ |
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135 | u8 compute_unit_id; |
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136 | /* Index into per_cpu list: */ |
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137 | u16 cpu_index; |
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138 | u32 microcode; |
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139 | }; |
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140 | |||
141 | #define X86_VENDOR_INTEL 0 |
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142 | #define X86_VENDOR_CYRIX 1 |
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143 | #define X86_VENDOR_AMD 2 |
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144 | #define X86_VENDOR_UMC 3 |
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145 | #define X86_VENDOR_CENTAUR 5 |
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146 | #define X86_VENDOR_TRANSMETA 7 |
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147 | #define X86_VENDOR_NSC 8 |
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148 | #define X86_VENDOR_NUM 9 |
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149 | |||
150 | #define X86_VENDOR_UNKNOWN 0xff |
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151 | |||
152 | /* |
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153 | * capabilities of CPUs |
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154 | */ |
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155 | extern struct cpuinfo_x86 boot_cpu_data; |
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156 | extern struct cpuinfo_x86 new_cpu_data; |
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157 | |||
158 | extern struct tss_struct doublefault_tss; |
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159 | extern __u32 cpu_caps_cleared[NCAPINTS]; |
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160 | extern __u32 cpu_caps_set[NCAPINTS]; |
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161 | |||
162 | #ifdef CONFIG_SMP |
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163 | DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
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164 | #define cpu_data(cpu) per_cpu(cpu_info, cpu) |
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165 | #else |
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166 | #define cpu_info boot_cpu_data |
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167 | #define cpu_data(cpu) boot_cpu_data |
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168 | #endif |
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169 | |||
170 | extern const struct seq_operations cpuinfo_op; |
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171 | |||
172 | extern void cpu_detect(struct cpuinfo_x86 *c); |
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173 | |||
174 | extern void early_cpu_init(void); |
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175 | extern void identify_boot_cpu(void); |
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176 | extern void identify_secondary_cpu(struct cpuinfo_x86 *); |
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177 | extern void print_cpu_info(struct cpuinfo_x86 *); |
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178 | void print_cpu_msr(struct cpuinfo_x86 *); |
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179 | extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c); |
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180 | extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); |
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181 | extern void init_amd_cacheinfo(struct cpuinfo_x86 *c); |
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182 | |||
183 | extern void detect_extended_topology(struct cpuinfo_x86 *c); |
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184 | extern void detect_ht(struct cpuinfo_x86 *c); |
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185 | |||
186 | #ifdef CONFIG_X86_32 |
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187 | extern int have_cpuid_p(void); |
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188 | #else |
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189 | static inline int have_cpuid_p(void) |
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190 | { |
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191 | return 1; |
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192 | } |
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193 | #endif |
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194 | static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, |
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195 | unsigned int *ecx, unsigned int *edx) |
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196 | { |
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197 | /* ecx is often an input as well as an output. */ |
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198 | asm volatile("cpuid" |
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199 | : "=a" (*eax), |
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200 | "=b" (*ebx), |
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201 | "=c" (*ecx), |
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202 | "=d" (*edx) |
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203 | : "0" (*eax), "2" (*ecx) |
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204 | : "memory"); |
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205 | } |
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206 | |||
207 | static inline void load_cr3(pgd_t *pgdir) |
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208 | { |
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209 | write_cr3(__pa(pgdir)); |
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210 | } |
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211 | |||
212 | #ifdef CONFIG_X86_32 |
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213 | /* This is the TSS defined by the hardware. */ |
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214 | struct x86_hw_tss { |
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215 | unsigned short back_link, __blh; |
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216 | unsigned long sp0; |
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217 | unsigned short ss0, __ss0h; |
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218 | unsigned long sp1; |
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6082 | serge | 219 | |
220 | /* |
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221 | * We don't use ring 1, so ss1 is a convenient scratch space in |
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222 | * the same cacheline as sp0. We use ss1 to cache the value in |
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223 | * MSR_IA32_SYSENTER_CS. When we context switch |
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224 | * MSR_IA32_SYSENTER_CS, we first check if the new value being |
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225 | * written matches ss1, and, if it's not, then we wrmsr the new |
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226 | * value and update ss1. |
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227 | * |
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228 | * The only reason we context switch MSR_IA32_SYSENTER_CS is |
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229 | * that we set it to zero in vm86 tasks to avoid corrupting the |
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230 | * stack if we were to go through the sysenter path from vm86 |
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231 | * mode. |
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232 | */ |
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233 | unsigned short ss1; /* MSR_IA32_SYSENTER_CS */ |
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234 | |||
235 | unsigned short __ss1h; |
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5270 | serge | 236 | unsigned long sp2; |
237 | unsigned short ss2, __ss2h; |
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238 | unsigned long __cr3; |
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239 | unsigned long ip; |
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240 | unsigned long flags; |
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241 | unsigned long ax; |
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242 | unsigned long cx; |
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243 | unsigned long dx; |
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244 | unsigned long bx; |
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245 | unsigned long sp; |
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246 | unsigned long bp; |
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247 | unsigned long si; |
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248 | unsigned long di; |
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249 | unsigned short es, __esh; |
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250 | unsigned short cs, __csh; |
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251 | unsigned short ss, __ssh; |
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252 | unsigned short ds, __dsh; |
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253 | unsigned short fs, __fsh; |
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254 | unsigned short gs, __gsh; |
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255 | unsigned short ldt, __ldth; |
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256 | unsigned short trace; |
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257 | unsigned short io_bitmap_base; |
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258 | |||
259 | } __attribute__((packed)); |
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260 | #else |
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261 | struct x86_hw_tss { |
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262 | u32 reserved1; |
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263 | u64 sp0; |
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264 | u64 sp1; |
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265 | u64 sp2; |
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266 | u64 reserved2; |
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267 | u64 ist[7]; |
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268 | u32 reserved3; |
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269 | u32 reserved4; |
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270 | u16 reserved5; |
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271 | u16 io_bitmap_base; |
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272 | |||
273 | } __attribute__((packed)) ____cacheline_aligned; |
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274 | #endif |
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275 | |||
276 | /* |
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277 | * IO-bitmap sizes: |
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278 | */ |
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279 | #define IO_BITMAP_BITS 65536 |
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280 | #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8) |
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281 | #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long)) |
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282 | #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap) |
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283 | #define INVALID_IO_BITMAP_OFFSET 0x8000 |
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284 | |||
285 | struct tss_struct { |
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286 | /* |
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287 | * The hardware state: |
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288 | */ |
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289 | struct x86_hw_tss x86_tss; |
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290 | |||
291 | /* |
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292 | * The extra 1 is there because the CPU will access an |
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293 | * additional byte beyond the end of the IO permission |
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294 | * bitmap. The extra byte must be all 1 bits, and must |
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295 | * be within the limit. |
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296 | */ |
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297 | unsigned long io_bitmap[IO_BITMAP_LONGS + 1]; |
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298 | |||
299 | /* |
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6082 | serge | 300 | * Space for the temporary SYSENTER stack: |
5270 | serge | 301 | */ |
6082 | serge | 302 | unsigned long SYSENTER_stack[64]; |
5270 | serge | 303 | |
304 | } ____cacheline_aligned; |
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305 | |||
6082 | serge | 306 | DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss); |
5270 | serge | 307 | |
6082 | serge | 308 | #ifdef CONFIG_X86_32 |
309 | DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack); |
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310 | #endif |
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311 | |||
5270 | serge | 312 | /* |
313 | * Save the original ist values for checking stack pointers during debugging |
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314 | */ |
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315 | struct orig_ist { |
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316 | unsigned long ist[7]; |
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317 | }; |
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318 | |||
319 | #ifdef CONFIG_X86_64 |
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320 | DECLARE_PER_CPU(struct orig_ist, orig_ist); |
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321 | |||
322 | union irq_stack_union { |
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323 | char irq_stack[IRQ_STACK_SIZE]; |
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324 | /* |
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325 | * GCC hardcodes the stack canary as %gs:40. Since the |
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326 | * irq_stack is the object at %gs:0, we reserve the bottom |
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327 | * 48 bytes of the irq stack for the canary. |
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328 | */ |
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329 | struct { |
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330 | char gs_base[40]; |
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331 | unsigned long stack_canary; |
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332 | }; |
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333 | }; |
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334 | |||
335 | DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible; |
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336 | DECLARE_INIT_PER_CPU(irq_stack_union); |
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337 | |||
338 | DECLARE_PER_CPU(char *, irq_stack_ptr); |
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339 | DECLARE_PER_CPU(unsigned int, irq_count); |
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340 | extern asmlinkage void ignore_sysret(void); |
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341 | #else /* X86_64 */ |
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342 | #ifdef CONFIG_CC_STACKPROTECTOR |
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343 | /* |
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344 | * Make sure stack canary segment base is cached-aligned: |
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345 | * "For Intel Atom processors, avoid non zero segment base address |
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346 | * that is not aligned to cache line boundary at all cost." |
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347 | * (Optim Ref Manual Assembly/Compiler Coding Rule 15.) |
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348 | */ |
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349 | struct stack_canary { |
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350 | char __pad[20]; /* canary at %gs:20 */ |
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351 | unsigned long canary; |
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352 | }; |
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353 | DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
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354 | #endif |
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355 | /* |
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356 | * per-CPU IRQ handling stacks |
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357 | */ |
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358 | struct irq_stack { |
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359 | u32 stack[THREAD_SIZE/sizeof(u32)]; |
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360 | } __aligned(THREAD_SIZE); |
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361 | |||
362 | DECLARE_PER_CPU(struct irq_stack *, hardirq_stack); |
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363 | DECLARE_PER_CPU(struct irq_stack *, softirq_stack); |
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364 | #endif /* X86_64 */ |
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365 | |||
366 | extern unsigned int xstate_size; |
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367 | |||
368 | struct perf_event; |
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369 | |||
370 | struct thread_struct { |
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371 | /* Cached TLS descriptors: */ |
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372 | struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES]; |
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373 | unsigned long sp0; |
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374 | unsigned long sp; |
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375 | #ifdef CONFIG_X86_32 |
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376 | unsigned long sysenter_cs; |
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377 | #else |
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378 | unsigned short es; |
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379 | unsigned short ds; |
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380 | unsigned short fsindex; |
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381 | unsigned short gsindex; |
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382 | #endif |
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383 | #ifdef CONFIG_X86_32 |
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384 | unsigned long ip; |
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385 | #endif |
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386 | #ifdef CONFIG_X86_64 |
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387 | unsigned long fs; |
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388 | #endif |
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389 | unsigned long gs; |
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6082 | serge | 390 | |
5270 | serge | 391 | /* Save middle states of ptrace breakpoints */ |
392 | struct perf_event *ptrace_bps[HBP_NUM]; |
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393 | /* Debug status used for traps, single steps, etc... */ |
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394 | unsigned long debugreg6; |
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395 | /* Keep track of the exact dr7 value set by the user */ |
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396 | unsigned long ptrace_dr7; |
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397 | /* Fault info: */ |
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398 | unsigned long cr2; |
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399 | unsigned long trap_nr; |
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400 | unsigned long error_code; |
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6082 | serge | 401 | #ifdef CONFIG_VM86 |
5270 | serge | 402 | /* Virtual 86 mode info */ |
6082 | serge | 403 | struct vm86 *vm86; |
5270 | serge | 404 | #endif |
405 | /* IO permissions: */ |
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406 | unsigned long *io_bitmap_ptr; |
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407 | unsigned long iopl; |
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408 | /* Max allowed port in the bitmap, in bytes: */ |
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409 | unsigned io_bitmap_max; |
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6082 | serge | 410 | |
411 | /* Floating point and extended processor state */ |
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412 | struct fpu fpu; |
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5270 | serge | 413 | /* |
6082 | serge | 414 | * WARNING: 'fpu' is dynamically-sized. It *MUST* be at |
415 | * the end. |
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5270 | serge | 416 | */ |
417 | }; |
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418 | |||
419 | /* |
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420 | * Set IOPL bits in EFLAGS from given mask |
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421 | */ |
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422 | static inline void native_set_iopl_mask(unsigned mask) |
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423 | { |
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424 | #ifdef CONFIG_X86_32 |
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425 | unsigned int reg; |
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426 | |||
427 | asm volatile ("pushfl;" |
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428 | "popl %0;" |
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429 | "andl %1, %0;" |
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430 | "orl %2, %0;" |
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431 | "pushl %0;" |
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432 | "popfl" |
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433 | : "=&r" (reg) |
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434 | : "i" (~X86_EFLAGS_IOPL), "r" (mask)); |
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435 | #endif |
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436 | } |
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437 | |||
438 | static inline void |
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439 | native_load_sp0(struct tss_struct *tss, struct thread_struct *thread) |
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440 | { |
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441 | tss->x86_tss.sp0 = thread->sp0; |
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442 | #ifdef CONFIG_X86_32 |
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443 | /* Only happens when SEP is enabled, no need to test "SEP"arately: */ |
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444 | if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) { |
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445 | tss->x86_tss.ss1 = thread->sysenter_cs; |
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446 | wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); |
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447 | } |
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448 | #endif |
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449 | } |
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450 | |||
451 | static inline void native_swapgs(void) |
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452 | { |
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453 | #ifdef CONFIG_X86_64 |
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454 | asm volatile("swapgs" ::: "memory"); |
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455 | #endif |
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456 | } |
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457 | |||
6082 | serge | 458 | |
5270 | serge | 459 | #ifdef CONFIG_PARAVIRT |
460 | #include |
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461 | #else |
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462 | #define __cpuid native_cpuid |
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463 | #define paravirt_enabled() 0 |
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6082 | serge | 464 | #define paravirt_has(x) 0 |
5270 | serge | 465 | |
466 | static inline void load_sp0(struct tss_struct *tss, |
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467 | struct thread_struct *thread) |
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468 | { |
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469 | native_load_sp0(tss, thread); |
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470 | } |
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471 | |||
472 | #define set_iopl_mask native_set_iopl_mask |
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473 | #endif /* CONFIG_PARAVIRT */ |
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474 | |||
475 | typedef struct { |
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476 | unsigned long seg; |
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477 | } mm_segment_t; |
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478 | |||
479 | |||
480 | /* Free all resources held by a thread. */ |
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481 | extern void release_thread(struct task_struct *); |
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482 | |||
483 | unsigned long get_wchan(struct task_struct *p); |
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484 | |||
485 | /* |
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486 | * Generic CPUID function |
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487 | * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx |
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488 | * resulting in stale register contents being returned. |
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489 | */ |
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490 | static inline void cpuid(unsigned int op, |
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491 | unsigned int *eax, unsigned int *ebx, |
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492 | unsigned int *ecx, unsigned int *edx) |
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493 | { |
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494 | *eax = op; |
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495 | *ecx = 0; |
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496 | __cpuid(eax, ebx, ecx, edx); |
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497 | } |
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498 | |||
499 | /* Some CPUID calls want 'count' to be placed in ecx */ |
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500 | static inline void cpuid_count(unsigned int op, int count, |
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501 | unsigned int *eax, unsigned int *ebx, |
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502 | unsigned int *ecx, unsigned int *edx) |
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503 | { |
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504 | *eax = op; |
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505 | *ecx = count; |
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506 | __cpuid(eax, ebx, ecx, edx); |
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507 | } |
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508 | |||
509 | /* |
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510 | * CPUID functions returning a single datum |
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511 | */ |
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512 | static inline unsigned int cpuid_eax(unsigned int op) |
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513 | { |
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514 | unsigned int eax, ebx, ecx, edx; |
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515 | |||
516 | cpuid(op, &eax, &ebx, &ecx, &edx); |
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517 | |||
518 | return eax; |
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519 | } |
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520 | |||
521 | static inline unsigned int cpuid_ebx(unsigned int op) |
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522 | { |
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523 | unsigned int eax, ebx, ecx, edx; |
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524 | |||
525 | cpuid(op, &eax, &ebx, &ecx, &edx); |
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526 | |||
527 | return ebx; |
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528 | } |
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529 | |||
530 | static inline unsigned int cpuid_ecx(unsigned int op) |
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531 | { |
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532 | unsigned int eax, ebx, ecx, edx; |
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533 | |||
534 | cpuid(op, &eax, &ebx, &ecx, &edx); |
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535 | |||
536 | return ecx; |
||
537 | } |
||
538 | |||
539 | static inline unsigned int cpuid_edx(unsigned int op) |
||
540 | { |
||
541 | unsigned int eax, ebx, ecx, edx; |
||
542 | |||
543 | cpuid(op, &eax, &ebx, &ecx, &edx); |
||
544 | |||
545 | return edx; |
||
546 | } |
||
547 | |||
548 | /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */ |
||
6082 | serge | 549 | static __always_inline void rep_nop(void) |
5270 | serge | 550 | { |
551 | asm volatile("rep; nop" ::: "memory"); |
||
552 | } |
||
553 | |||
6082 | serge | 554 | static __always_inline void cpu_relax(void) |
5270 | serge | 555 | { |
556 | rep_nop(); |
||
557 | } |
||
558 | |||
559 | #define cpu_relax_lowlatency() cpu_relax() |
||
560 | |||
561 | /* Stop speculative execution and prefetching of modified code. */ |
||
562 | static inline void sync_core(void) |
||
563 | { |
||
564 | int tmp; |
||
565 | |||
566 | #ifdef CONFIG_M486 |
||
567 | /* |
||
568 | * Do a CPUID if available, otherwise do a jump. The jump |
||
569 | * can conveniently enough be the jump around CPUID. |
||
570 | */ |
||
571 | asm volatile("cmpl %2,%1\n\t" |
||
572 | "jl 1f\n\t" |
||
573 | "cpuid\n" |
||
574 | "1:" |
||
575 | : "=a" (tmp) |
||
576 | : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1) |
||
577 | : "ebx", "ecx", "edx", "memory"); |
||
578 | #else |
||
579 | /* |
||
580 | * CPUID is a barrier to speculative execution. |
||
581 | * Prefetched instructions are automatically |
||
582 | * invalidated when modified. |
||
583 | */ |
||
584 | asm volatile("cpuid" |
||
585 | : "=a" (tmp) |
||
586 | : "0" (1) |
||
587 | : "ebx", "ecx", "edx", "memory"); |
||
588 | #endif |
||
589 | } |
||
590 | |||
591 | extern void select_idle_routine(const struct cpuinfo_x86 *c); |
||
592 | extern void init_amd_e400_c1e_mask(void); |
||
593 | |||
594 | extern unsigned long boot_option_idle_override; |
||
595 | extern bool amd_e400_c1e_detected; |
||
596 | |||
597 | enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT, |
||
598 | IDLE_POLL}; |
||
599 | |||
600 | extern void enable_sep_cpu(void); |
||
601 | extern int sysenter_setup(void); |
||
602 | |||
603 | extern void early_trap_init(void); |
||
604 | void early_trap_pf_init(void); |
||
605 | |||
606 | /* Defined in head.S */ |
||
607 | extern struct desc_ptr early_gdt_descr; |
||
608 | |||
609 | extern void cpu_set_gdt(int); |
||
610 | extern void switch_to_new_gdt(int); |
||
611 | extern void load_percpu_segment(int); |
||
612 | extern void cpu_init(void); |
||
613 | |||
614 | static inline unsigned long get_debugctlmsr(void) |
||
615 | { |
||
616 | unsigned long debugctlmsr = 0; |
||
617 | |||
618 | #ifndef CONFIG_X86_DEBUGCTLMSR |
||
619 | if (boot_cpu_data.x86 < 6) |
||
620 | return 0; |
||
621 | #endif |
||
622 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); |
||
623 | |||
624 | return debugctlmsr; |
||
625 | } |
||
626 | |||
627 | static inline void update_debugctlmsr(unsigned long debugctlmsr) |
||
628 | { |
||
629 | #ifndef CONFIG_X86_DEBUGCTLMSR |
||
630 | if (boot_cpu_data.x86 < 6) |
||
631 | return; |
||
632 | #endif |
||
633 | wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); |
||
634 | } |
||
635 | |||
636 | extern void set_task_blockstep(struct task_struct *task, bool on); |
||
637 | |||
638 | /* Boot loader type from the setup header: */ |
||
639 | extern int bootloader_type; |
||
640 | extern int bootloader_version; |
||
641 | |||
642 | extern char ignore_fpu_irq; |
||
643 | |||
644 | #define HAVE_ARCH_PICK_MMAP_LAYOUT 1 |
||
645 | #define ARCH_HAS_PREFETCHW |
||
646 | #define ARCH_HAS_SPINLOCK_PREFETCH |
||
647 | |||
648 | #ifdef CONFIG_X86_32 |
||
6082 | serge | 649 | # define BASE_PREFETCH "" |
5270 | serge | 650 | # define ARCH_HAS_PREFETCH |
651 | #else |
||
6082 | serge | 652 | # define BASE_PREFETCH "prefetcht0 %P1" |
5270 | serge | 653 | #endif |
654 | |||
655 | /* |
||
656 | * Prefetch instructions for Pentium III (+) and AMD Athlon (+) |
||
657 | * |
||
658 | * It's not worth to care about 3dnow prefetches for the K6 |
||
659 | * because they are microcoded there and very slow. |
||
660 | */ |
||
661 | static inline void prefetch(const void *x) |
||
662 | { |
||
663 | alternative_input(BASE_PREFETCH, |
||
664 | "prefetchnta (%1)", |
||
665 | X86_FEATURE_XMM, |
||
666 | "r" (x)); |
||
667 | } |
||
668 | |||
669 | /* |
||
670 | * 3dnow prefetch to get an exclusive cache line. |
||
671 | * Useful for spinlocks to avoid one state transition in the |
||
672 | * cache coherency protocol: |
||
673 | */ |
||
674 | static inline void prefetchw(const void *x) |
||
675 | { |
||
676 | alternative_input(BASE_PREFETCH, |
||
677 | "prefetchw (%1)", |
||
678 | X86_FEATURE_3DNOW, |
||
679 | "r" (x)); |
||
680 | } |
||
681 | |||
682 | static inline void spin_lock_prefetch(const void *x) |
||
683 | { |
||
684 | prefetchw(x); |
||
685 | } |
||
686 | |||
6082 | serge | 687 | #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \ |
688 | TOP_OF_KERNEL_STACK_PADDING) |
||
689 | |||
5270 | serge | 690 | #ifdef CONFIG_X86_32 |
691 | /* |
||
692 | * User space process size: 3GB (default). |
||
693 | */ |
||
694 | #define TASK_SIZE PAGE_OFFSET |
||
695 | #define TASK_SIZE_MAX TASK_SIZE |
||
696 | #define STACK_TOP TASK_SIZE |
||
697 | #define STACK_TOP_MAX STACK_TOP |
||
698 | |||
699 | #define INIT_THREAD { \ |
||
6082 | serge | 700 | .sp0 = TOP_OF_INIT_STACK, \ |
5270 | serge | 701 | .sysenter_cs = __KERNEL_CS, \ |
702 | .io_bitmap_ptr = NULL, \ |
||
703 | } |
||
704 | |||
705 | extern unsigned long thread_saved_pc(struct task_struct *tsk); |
||
706 | |||
707 | /* |
||
6082 | serge | 708 | * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack. |
5270 | serge | 709 | * This is necessary to guarantee that the entire "struct pt_regs" |
710 | * is accessible even if the CPU haven't stored the SS/ESP registers |
||
711 | * on the stack (interrupt gate does not save these registers |
||
712 | * when switching to the same priv ring). |
||
713 | * Therefore beware: accessing the ss/esp fields of the |
||
714 | * "struct pt_regs" is possible, but they may contain the |
||
715 | * completely wrong values. |
||
716 | */ |
||
6082 | serge | 717 | #define task_pt_regs(task) \ |
718 | ({ \ |
||
719 | unsigned long __ptr = (unsigned long)task_stack_page(task); \ |
||
720 | __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \ |
||
721 | ((struct pt_regs *)__ptr) - 1; \ |
||
5270 | serge | 722 | }) |
723 | |||
724 | #define KSTK_ESP(task) (task_pt_regs(task)->sp) |
||
725 | |||
726 | #else |
||
727 | /* |
||
728 | * User space process size. 47bits minus one guard page. The guard |
||
729 | * page is necessary on Intel CPUs: if a SYSCALL instruction is at |
||
730 | * the highest possible canonical userspace address, then that |
||
731 | * syscall will enter the kernel with a non-canonical return |
||
732 | * address, and SYSRET will explode dangerously. We avoid this |
||
733 | * particular problem by preventing anything from being mapped |
||
734 | * at the maximum canonical address. |
||
735 | */ |
||
736 | #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) |
||
737 | |||
738 | /* This decides where the kernel will search for a free chunk of vm |
||
739 | * space during mmap's. |
||
740 | */ |
||
741 | #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \ |
||
742 | 0xc0000000 : 0xFFFFe000) |
||
743 | |||
744 | #define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \ |
||
745 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
||
746 | #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \ |
||
747 | IA32_PAGE_OFFSET : TASK_SIZE_MAX) |
||
748 | |||
749 | #define STACK_TOP TASK_SIZE |
||
750 | #define STACK_TOP_MAX TASK_SIZE_MAX |
||
751 | |||
752 | #define INIT_THREAD { \ |
||
6082 | serge | 753 | .sp0 = TOP_OF_INIT_STACK \ |
5270 | serge | 754 | } |
755 | |||
756 | /* |
||
757 | * Return saved PC of a blocked thread. |
||
758 | * What is this good for? it will be always the scheduler or ret_from_fork. |
||
759 | */ |
||
760 | #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8)) |
||
761 | |||
762 | #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1) |
||
763 | extern unsigned long KSTK_ESP(struct task_struct *task); |
||
764 | |||
765 | #endif /* CONFIG_X86_64 */ |
||
766 | |||
767 | extern void start_thread(struct pt_regs *regs, unsigned long new_ip, |
||
768 | unsigned long new_sp); |
||
769 | |||
770 | /* |
||
771 | * This decides where the kernel will search for a free chunk of vm |
||
772 | * space during mmap's. |
||
773 | */ |
||
774 | #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3)) |
||
775 | |||
776 | #define KSTK_EIP(task) (task_pt_regs(task)->ip) |
||
777 | |||
778 | /* Get/set a process' ability to use the timestamp counter instruction */ |
||
779 | #define GET_TSC_CTL(adr) get_tsc_mode((adr)) |
||
780 | #define SET_TSC_CTL(val) set_tsc_mode((val)) |
||
781 | |||
782 | extern int get_tsc_mode(unsigned long adr); |
||
783 | extern int set_tsc_mode(unsigned int val); |
||
784 | |||
785 | /* Register/unregister a process' MPX related resource */ |
||
6082 | serge | 786 | #define MPX_ENABLE_MANAGEMENT() mpx_enable_management() |
787 | #define MPX_DISABLE_MANAGEMENT() mpx_disable_management() |
||
5270 | serge | 788 | |
789 | #ifdef CONFIG_X86_INTEL_MPX |
||
6082 | serge | 790 | extern int mpx_enable_management(void); |
791 | extern int mpx_disable_management(void); |
||
5270 | serge | 792 | #else |
6082 | serge | 793 | static inline int mpx_enable_management(void) |
5270 | serge | 794 | { |
795 | return -EINVAL; |
||
796 | } |
||
6082 | serge | 797 | static inline int mpx_disable_management(void) |
5270 | serge | 798 | { |
799 | return -EINVAL; |
||
800 | } |
||
801 | #endif /* CONFIG_X86_INTEL_MPX */ |
||
802 | |||
803 | extern u16 amd_get_nb_id(int cpu); |
||
6082 | serge | 804 | extern u32 amd_get_nodes_per_socket(void); |
5270 | serge | 805 | |
806 | static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) |
||
807 | { |
||
808 | uint32_t base, eax, signature[3]; |
||
809 | |||
810 | for (base = 0x40000000; base < 0x40010000; base += 0x100) { |
||
811 | cpuid(base, &eax, &signature[0], &signature[1], &signature[2]); |
||
812 | |||
813 | if (!memcmp(sig, signature, 12) && |
||
814 | (leaves == 0 || ((eax - base) >= leaves))) |
||
815 | return base; |
||
816 | } |
||
817 | |||
818 | return 0; |
||
819 | } |
||
820 | |||
821 | extern unsigned long arch_align_stack(unsigned long sp); |
||
822 | extern void free_init_pages(char *what, unsigned long begin, unsigned long end); |
||
823 | |||
824 | void default_idle(void); |
||
825 | #ifdef CONFIG_XEN |
||
826 | bool xen_set_default_idle(void); |
||
827 | #else |
||
828 | #define xen_set_default_idle 0 |
||
829 | #endif |
||
830 | |||
831 | void stop_this_cpu(void *dummy); |
||
832 | void df_debug(struct pt_regs *regs, long error_code); |
||
833 | #endif /* _ASM_X86_PROCESSOR_H */>><>>>><>><> |