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5270 | serge | 1 | #ifndef _ASM_X86_MSR_H |
2 | #define _ASM_X86_MSR_H |
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3 | |||
6082 | serge | 4 | #include "msr-index.h" |
5270 | serge | 5 | |
6 | #ifndef __ASSEMBLY__ |
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7 | |||
8 | #include |
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9 | #include |
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10 | #include |
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6082 | serge | 11 | #include |
5270 | serge | 12 | |
13 | struct msr { |
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14 | union { |
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15 | struct { |
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16 | u32 l; |
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17 | u32 h; |
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18 | }; |
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19 | u64 q; |
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20 | }; |
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21 | }; |
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22 | |||
23 | struct msr_info { |
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24 | u32 msr_no; |
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25 | struct msr reg; |
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26 | struct msr *msrs; |
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27 | int err; |
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28 | }; |
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29 | |||
30 | struct msr_regs_info { |
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31 | u32 *regs; |
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32 | int err; |
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33 | }; |
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34 | |||
35 | static inline unsigned long long native_read_tscp(unsigned int *aux) |
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36 | { |
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37 | unsigned long low, high; |
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38 | asm volatile(".byte 0x0f,0x01,0xf9" |
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39 | : "=a" (low), "=d" (high), "=c" (*aux)); |
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40 | return low | ((u64)high << 32); |
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41 | } |
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42 | |||
43 | /* |
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44 | * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" |
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45 | * constraint has different meanings. For i386, "A" means exactly |
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46 | * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, |
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47 | * it means rax *or* rdx. |
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48 | */ |
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49 | #ifdef CONFIG_X86_64 |
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6082 | serge | 50 | /* Using 64-bit values saves one instruction clearing the high half of low */ |
51 | #define DECLARE_ARGS(val, low, high) unsigned long low, high |
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52 | #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) |
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5270 | serge | 53 | #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) |
54 | #else |
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55 | #define DECLARE_ARGS(val, low, high) unsigned long long val |
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56 | #define EAX_EDX_VAL(val, low, high) (val) |
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57 | #define EAX_EDX_RET(val, low, high) "=A" (val) |
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58 | #endif |
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59 | |||
60 | static inline unsigned long long native_read_msr(unsigned int msr) |
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61 | { |
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62 | DECLARE_ARGS(val, low, high); |
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63 | |||
64 | asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); |
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65 | return EAX_EDX_VAL(val, low, high); |
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66 | } |
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67 | |||
68 | static inline unsigned long long native_read_msr_safe(unsigned int msr, |
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69 | int *err) |
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70 | { |
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71 | DECLARE_ARGS(val, low, high); |
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72 | |||
73 | asm volatile("2: rdmsr ; xor %[err],%[err]\n" |
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74 | "1:\n\t" |
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75 | ".section .fixup,\"ax\"\n\t" |
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76 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
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77 | ".previous\n\t" |
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78 | _ASM_EXTABLE(2b, 3b) |
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79 | : [err] "=r" (*err), EAX_EDX_RET(val, low, high) |
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80 | : "c" (msr), [fault] "i" (-EIO)); |
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81 | return EAX_EDX_VAL(val, low, high); |
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82 | } |
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83 | |||
84 | static inline void native_write_msr(unsigned int msr, |
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85 | unsigned low, unsigned high) |
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86 | { |
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87 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
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88 | } |
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89 | |||
90 | /* Can be uninlined because referenced by paravirt */ |
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91 | notrace static inline int native_write_msr_safe(unsigned int msr, |
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92 | unsigned low, unsigned high) |
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93 | { |
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94 | int err; |
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95 | asm volatile("2: wrmsr ; xor %[err],%[err]\n" |
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96 | "1:\n\t" |
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97 | ".section .fixup,\"ax\"\n\t" |
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98 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
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99 | ".previous\n\t" |
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100 | _ASM_EXTABLE(2b, 3b) |
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101 | : [err] "=a" (err) |
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102 | : "c" (msr), "0" (low), "d" (high), |
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103 | [fault] "i" (-EIO) |
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104 | : "memory"); |
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105 | return err; |
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106 | } |
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107 | |||
108 | extern int rdmsr_safe_regs(u32 regs[8]); |
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109 | extern int wrmsr_safe_regs(u32 regs[8]); |
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110 | |||
6082 | serge | 111 | /** |
112 | * rdtsc() - returns the current TSC without ordering constraints |
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113 | * |
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114 | * rdtsc() returns the result of RDTSC as a 64-bit integer. The |
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115 | * only ordering constraint it supplies is the ordering implied by |
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116 | * "asm volatile": it will put the RDTSC in the place you expect. The |
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117 | * CPU can and will speculatively execute that RDTSC, though, so the |
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118 | * results can be non-monotonic if compared on different CPUs. |
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119 | */ |
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120 | static __always_inline unsigned long long rdtsc(void) |
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5270 | serge | 121 | { |
122 | DECLARE_ARGS(val, low, high); |
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123 | |||
124 | asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); |
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125 | |||
126 | return EAX_EDX_VAL(val, low, high); |
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127 | } |
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128 | |||
129 | static inline unsigned long long native_read_pmc(int counter) |
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130 | { |
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131 | DECLARE_ARGS(val, low, high); |
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132 | |||
133 | asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); |
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134 | return EAX_EDX_VAL(val, low, high); |
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135 | } |
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136 | |||
137 | #ifdef CONFIG_PARAVIRT |
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138 | #include |
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139 | #else |
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140 | #include |
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141 | /* |
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142 | * Access to machine-specific registers (available on 586 and better only) |
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143 | * Note: the rd* operations modify the parameters directly (without using |
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144 | * pointer indirection), this allows gcc to optimize better |
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145 | */ |
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146 | |||
147 | #define rdmsr(msr, low, high) \ |
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148 | do { \ |
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149 | u64 __val = native_read_msr((msr)); \ |
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150 | (void)((low) = (u32)__val); \ |
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151 | (void)((high) = (u32)(__val >> 32)); \ |
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152 | } while (0) |
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153 | |||
154 | static inline void wrmsr(unsigned msr, unsigned low, unsigned high) |
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155 | { |
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156 | native_write_msr(msr, low, high); |
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157 | } |
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158 | |||
159 | #define rdmsrl(msr, val) \ |
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160 | ((val) = native_read_msr((msr))) |
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161 | |||
6082 | serge | 162 | static inline void wrmsrl(unsigned msr, u64 val) |
163 | { |
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164 | native_write_msr(msr, (u32)val, (u32)(val >> 32)); |
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165 | } |
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5270 | serge | 166 | |
167 | /* wrmsr with exception handling */ |
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168 | static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) |
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169 | { |
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170 | return native_write_msr_safe(msr, low, high); |
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171 | } |
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172 | |||
173 | /* rdmsr with exception handling */ |
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174 | #define rdmsr_safe(msr, low, high) \ |
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175 | ({ \ |
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176 | int __err; \ |
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177 | u64 __val = native_read_msr_safe((msr), &__err); \ |
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178 | (*low) = (u32)__val; \ |
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179 | (*high) = (u32)(__val >> 32); \ |
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180 | __err; \ |
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181 | }) |
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182 | |||
183 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
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184 | { |
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185 | int err; |
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186 | |||
187 | *p = native_read_msr_safe(msr, &err); |
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188 | return err; |
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189 | } |
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190 | |||
191 | #define rdpmc(counter, low, high) \ |
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192 | do { \ |
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193 | u64 _l = native_read_pmc((counter)); \ |
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194 | (low) = (u32)_l; \ |
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195 | (high) = (u32)(_l >> 32); \ |
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196 | } while (0) |
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197 | |||
198 | #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) |
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199 | |||
200 | #endif /* !CONFIG_PARAVIRT */ |
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201 | |||
6082 | serge | 202 | /* |
203 | * 64-bit version of wrmsr_safe(): |
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204 | */ |
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205 | static inline int wrmsrl_safe(u32 msr, u64 val) |
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206 | { |
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207 | return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); |
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208 | } |
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5270 | serge | 209 | |
210 | #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high)) |
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211 | |||
212 | #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) |
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213 | |||
214 | struct msr *msrs_alloc(void); |
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215 | void msrs_free(struct msr *msrs); |
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216 | int msr_set_bit(u32 msr, u8 bit); |
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217 | int msr_clear_bit(u32 msr, u8 bit); |
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218 | |||
219 | #ifdef CONFIG_SMP |
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220 | int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
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221 | int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
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222 | int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
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223 | int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); |
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224 | void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
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225 | void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
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226 | int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
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227 | int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
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228 | int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
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229 | int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); |
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230 | int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
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231 | int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
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232 | #else /* CONFIG_SMP */ |
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233 | static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) |
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234 | { |
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235 | rdmsr(msr_no, *l, *h); |
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236 | return 0; |
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237 | } |
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238 | static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
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239 | { |
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240 | wrmsr(msr_no, l, h); |
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241 | return 0; |
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242 | } |
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243 | static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
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244 | { |
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245 | rdmsrl(msr_no, *q); |
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246 | return 0; |
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247 | } |
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248 | static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) |
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249 | { |
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250 | wrmsrl(msr_no, q); |
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251 | return 0; |
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252 | } |
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253 | static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
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254 | struct msr *msrs) |
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255 | { |
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256 | rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); |
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257 | } |
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258 | static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
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259 | struct msr *msrs) |
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260 | { |
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261 | wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); |
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262 | } |
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263 | static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, |
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264 | u32 *l, u32 *h) |
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265 | { |
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266 | return rdmsr_safe(msr_no, l, h); |
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267 | } |
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268 | static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
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269 | { |
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270 | return wrmsr_safe(msr_no, l, h); |
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271 | } |
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272 | static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
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273 | { |
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274 | return rdmsrl_safe(msr_no, q); |
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275 | } |
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276 | static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) |
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277 | { |
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278 | return wrmsrl_safe(msr_no, q); |
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279 | } |
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280 | static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
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281 | { |
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282 | return rdmsr_safe_regs(regs); |
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283 | } |
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284 | static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
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285 | { |
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286 | return wrmsr_safe_regs(regs); |
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287 | } |
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288 | #endif /* CONFIG_SMP */ |
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289 | #endif /* __ASSEMBLY__ */ |
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290 | #endif /* _ASM_X86_MSR_H */><>><> |