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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 9078 | turbocat | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef _ASM_X86_AMD_NB_H |
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| 3 | #define _ASM_X86_AMD_NB_H |
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| 4 | |||
| 5 | #include |
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| 6 | #include |
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| 7 | #include |
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| 8 | |||
| 9 | struct amd_nb_bus_dev_range { |
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| 10 | u8 bus; |
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| 11 | u8 dev_base; |
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| 12 | u8 dev_limit; |
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| 13 | }; |
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| 14 | |||
| 15 | extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[]; |
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| 16 | |||
| 17 | extern bool early_is_amd_nb(u32 value); |
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| 18 | extern struct resource *amd_get_mmconfig_range(struct resource *res); |
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| 19 | extern int amd_cache_northbridges(void); |
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| 20 | extern void amd_flush_garts(void); |
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| 21 | extern int amd_numa_init(void); |
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| 22 | extern int amd_get_subcaches(int); |
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| 23 | extern int amd_set_subcaches(int, unsigned long); |
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| 24 | |||
| 25 | extern int amd_smn_read(u16 node, u32 address, u32 *value); |
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| 26 | extern int amd_smn_write(u16 node, u32 address, u32 value); |
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| 27 | extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo); |
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| 28 | |||
| 29 | struct amd_l3_cache { |
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| 30 | unsigned indices; |
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| 31 | u8 subcaches[4]; |
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| 32 | }; |
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| 33 | |||
| 34 | struct threshold_block { |
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| 35 | unsigned int block; /* Number within bank */ |
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| 36 | unsigned int bank; /* MCA bank the block belongs to */ |
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| 37 | unsigned int cpu; /* CPU which controls MCA bank */ |
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| 38 | u32 address; /* MSR address for the block */ |
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| 39 | u16 interrupt_enable; /* Enable/Disable APIC interrupt */ |
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| 40 | bool interrupt_capable; /* Bank can generate an interrupt. */ |
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| 41 | |||
| 42 | u16 threshold_limit; /* |
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| 43 | * Value upon which threshold |
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| 44 | * interrupt is generated. |
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| 45 | */ |
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| 46 | |||
| 47 | struct kobject kobj; /* sysfs object */ |
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| 48 | struct list_head miscj; /* |
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| 49 | * List of threshold blocks |
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| 50 | * within a bank. |
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| 51 | */ |
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| 52 | }; |
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| 53 | |||
| 54 | struct threshold_bank { |
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| 55 | struct kobject *kobj; |
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| 56 | struct threshold_block *blocks; |
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| 57 | |||
| 58 | /* initialized to the number of CPUs on the node sharing this bank */ |
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| 59 | refcount_t cpus; |
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| 60 | unsigned int shared; |
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| 61 | }; |
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| 62 | |||
| 63 | struct amd_northbridge { |
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| 64 | struct pci_dev *root; |
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| 65 | struct pci_dev *misc; |
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| 66 | struct pci_dev *link; |
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| 67 | struct amd_l3_cache l3_cache; |
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| 68 | struct threshold_bank *bank4; |
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| 69 | }; |
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| 70 | |||
| 71 | struct amd_northbridge_info { |
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| 72 | u16 num; |
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| 73 | u64 flags; |
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| 74 | struct amd_northbridge *nb; |
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| 75 | }; |
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| 76 | |||
| 77 | #define AMD_NB_GART BIT(0) |
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| 78 | #define AMD_NB_L3_INDEX_DISABLE BIT(1) |
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| 79 | #define AMD_NB_L3_PARTITIONING BIT(2) |
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| 80 | |||
| 81 | #ifdef CONFIG_AMD_NB |
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| 82 | |||
| 83 | u16 amd_nb_num(void); |
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| 84 | bool amd_nb_has_feature(unsigned int feature); |
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| 85 | struct amd_northbridge *node_to_amd_nb(int node); |
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| 86 | |||
| 87 | static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev) |
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| 88 | { |
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| 89 | struct pci_dev *misc; |
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| 90 | int i; |
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| 91 | |||
| 92 | for (i = 0; i != amd_nb_num(); i++) { |
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| 93 | misc = node_to_amd_nb(i)->misc; |
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| 94 | |||
| 95 | if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) && |
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| 96 | PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn)) |
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| 97 | return i; |
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| 98 | } |
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| 99 | |||
| 100 | WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev)); |
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| 101 | return 0; |
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| 102 | } |
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| 103 | |||
| 104 | static inline bool amd_gart_present(void) |
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| 105 | { |
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| 106 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) |
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| 107 | return false; |
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| 108 | |||
| 109 | /* GART present only on Fam15h, upto model 0fh */ |
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| 110 | if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 || |
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| 111 | (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10)) |
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| 112 | return true; |
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| 113 | |||
| 114 | return false; |
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| 115 | } |
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| 116 | |||
| 117 | #else |
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| 118 | |||
| 119 | #define amd_nb_num(x) 0 |
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| 120 | #define amd_nb_has_feature(x) false |
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| 121 | #define node_to_amd_nb(x) NULL |
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| 122 | #define amd_gart_present(x) false |
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| 123 | |||
| 124 | #endif |
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| 125 | |||
| 126 | |||
| 127 | #endif /* _ASM_X86_AMD_NB_H */ |