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Rev | Author | Line No. | Line |
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3545 | hidnplayr | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
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3 | ;; Copyright (C) KolibriOS team 2004-2013. All rights reserved. ;; |
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4 | ;; Distributed under terms of the GNU General Public License ;; |
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5 | ;; ;; |
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6 | ;; i8254x driver for KolibriOS ;; |
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7 | ;; ;; |
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8 | ;; based on i8254x.asm from baremetal os ;; |
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9 | ;; ;; |
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10 | ;; Written by hidnplayr (hidnplayr@gmail.com) ;; |
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11 | ;; ;; |
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12 | ;; GNU GENERAL PUBLIC LICENSE ;; |
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13 | ;; Version 2, June 1991 ;; |
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14 | ;; ;; |
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15 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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16 | |||
17 | ; TODO: make better use of the available descriptors |
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18 | |||
19 | format MS COFF |
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20 | |||
21 | API_VERSION = 0x01000100 |
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22 | DRIVER_VERSION = 5 |
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23 | |||
24 | MAX_DEVICES = 16 |
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25 | |||
26 | DEBUG = 1 |
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27 | __DEBUG__ = 1 |
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3855 | hidnplayr | 28 | __DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only |
3545 | hidnplayr | 29 | |
30 | MAX_PKT_SIZE = 16384 ; Maximum packet size |
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31 | |||
32 | |||
33 | include '../proc32.inc' |
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34 | include '../imports.inc' |
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35 | include '../fdo.inc' |
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36 | include '../struct.inc' |
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37 | include '../netdrv.inc' |
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38 | |||
39 | public START |
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40 | public service_proc |
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41 | public version |
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42 | |||
43 | |||
44 | |||
45 | ; Register list |
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46 | REG_CTRL = 0x0000 ; Control Register |
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47 | REG_STATUS = 0x0008 ; Device Status Register |
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48 | REG_CTRLEXT = 0x0018 ; Extended Control Register |
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49 | REG_MDIC = 0x0020 ; MDI Control Register |
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50 | REG_FCAL = 0x0028 ; Flow Control Address Low |
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51 | REG_FCAH = 0x002C ; Flow Control Address High |
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52 | REG_FCT = 0x0030 ; Flow Control Type |
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53 | REG_VET = 0x0038 ; VLAN Ether Type |
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54 | REG_ICR = 0x00C0 ; Interrupt Cause Read |
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55 | REG_ITR = 0x00C4 ; Interrupt Throttling Register |
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56 | REG_ICS = 0x00C8 ; Interrupt Cause Set Register |
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57 | REG_IMS = 0x00D0 ; Interrupt Mask Set/Read Register |
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58 | REG_IMC = 0x00D8 ; Interrupt Mask Clear Register |
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59 | REG_RCTL = 0x0100 ; Receive Control Register |
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60 | REG_FCTTV = 0x0170 ; Flow Control Transmit Timer Value |
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61 | REG_TXCW = 0x0178 ; Transmit Configuration Word |
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62 | REG_RXCW = 0x0180 ; Receive Configuration Word |
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63 | REG_TCTL = 0x0400 ; Transmit Control Register |
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64 | REG_TIPG = 0x0410 ; Transmit Inter Packet Gap |
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65 | |||
66 | REG_LEDCTL = 0x0E00 ; LED Control |
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67 | REG_PBA = 0x1000 ; Packet Buffer Allocation |
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68 | |||
69 | REG_RDBAL = 0x2800 ; RX Descriptor Base Address Low |
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70 | REG_RDBAH = 0x2804 ; RX Descriptor Base Address High |
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71 | REG_RDLEN = 0x2808 ; RX Descriptor Length |
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72 | REG_RDH = 0x2810 ; RX Descriptor Head |
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73 | REG_RDT = 0x2818 ; RX Descriptor Tail |
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74 | REG_RDTR = 0x2820 ; RX Delay Timer Register |
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75 | REG_RXDCTL = 0x3828 ; RX Descriptor Control |
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76 | REG_RADV = 0x282C ; RX Int. Absolute Delay Timer |
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77 | REG_RSRPD = 0x2C00 ; RX Small Packet Detect Interrupt |
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78 | |||
79 | REG_TXDMAC = 0x3000 ; TX DMA Control |
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80 | REG_TDBAL = 0x3800 ; TX Descriptor Base Address Low |
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81 | REG_TDBAH = 0x3804 ; TX Descriptor Base Address High |
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82 | REG_TDLEN = 0x3808 ; TX Descriptor Length |
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83 | REG_TDH = 0x3810 ; TX Descriptor Head |
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84 | REG_TDT = 0x3818 ; TX Descriptor Tail |
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85 | REG_TIDV = 0x3820 ; TX Interrupt Delay Value |
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86 | REG_TXDCTL = 0x3828 ; TX Descriptor Control |
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87 | REG_TADV = 0x382C ; TX Absolute Interrupt Delay Value |
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88 | REG_TSPMT = 0x3830 ; TCP Segmentation Pad & Min Threshold |
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89 | |||
90 | REG_RXCSUM = 0x5000 ; RX Checksum Control |
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91 | |||
92 | ; Register list for i8254x |
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93 | I82542_REG_RDTR = 0x0108 ; RX Delay Timer Register |
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94 | I82542_REG_RDBAL = 0x0110 ; RX Descriptor Base Address Low |
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95 | I82542_REG_RDBAH = 0x0114 ; RX Descriptor Base Address High |
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96 | I82542_REG_RDLEN = 0x0118 ; RX Descriptor Length |
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97 | I82542_REG_RDH = 0x0120 ; RDH for i82542 |
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98 | I82542_REG_RDT = 0x0128 ; RDT for i82542 |
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99 | I82542_REG_TDBAL = 0x0420 ; TX Descriptor Base Address Low |
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100 | I82542_REG_TDBAH = 0x0424 ; TX Descriptor Base Address Low |
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101 | I82542_REG_TDLEN = 0x0428 ; TX Descriptor Length |
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102 | I82542_REG_TDH = 0x0430 ; TDH for i82542 |
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103 | I82542_REG_TDT = 0x0438 ; TDT for i82542 |
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104 | |||
105 | ; CTRL - Control Register (0x0000) |
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106 | CTRL_FD = 0x00000001 ; Full Duplex |
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107 | CTRL_LRST = 0x00000008 ; Link Reset |
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108 | CTRL_ASDE = 0x00000020 ; Auto-speed detection |
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109 | CTRL_SLU = 0x00000040 ; Set Link Up |
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110 | CTRL_ILOS = 0x00000080 ; Invert Loss of Signal |
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111 | CTRL_SPEED_MASK = 0x00000300 ; Speed selection |
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112 | CTRL_SPEED_SHIFT = 8 |
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113 | CTRL_FRCSPD = 0x00000800 ; Force Speed |
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114 | CTRL_FRCDPLX = 0x00001000 ; Force Duplex |
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115 | CTRL_SDP0_DATA = 0x00040000 ; SDP0 data |
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116 | CTRL_SDP1_DATA = 0x00080000 ; SDP1 data |
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117 | CTRL_SDP0_IODIR = 0x00400000 ; SDP0 direction |
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118 | CTRL_SDP1_IODIR = 0x00800000 ; SDP1 direction |
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119 | CTRL_RST = 0x04000000 ; Device Reset |
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120 | CTRL_RFCE = 0x08000000 ; RX Flow Ctrl Enable |
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121 | CTRL_TFCE = 0x10000000 ; TX Flow Ctrl Enable |
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122 | CTRL_VME = 0x40000000 ; VLAN Mode Enable |
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123 | CTRL_PHY_RST = 0x80000000 ; PHY reset |
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124 | |||
125 | ; STATUS - Device Status Register (0x0008) |
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126 | STATUS_FD = 0x00000001 ; Full Duplex |
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127 | STATUS_LU = 0x00000002 ; Link Up |
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128 | STATUS_TXOFF = 0x00000010 ; Transmit paused |
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129 | STATUS_TBIMODE = 0x00000020 ; TBI Mode |
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130 | STATUS_SPEED_MASK = 0x000000C0 ; Link Speed setting |
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131 | STATUS_SPEED_SHIFT = 6 |
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132 | STATUS_ASDV_MASK = 0x00000300 ; Auto Speed Detection |
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133 | STATUS_ASDV_SHIFT = 8 |
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134 | STATUS_PCI66 = 0x00000800 ; PCI bus speed |
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135 | STATUS_BUS64 = 0x00001000 ; PCI bus width |
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136 | STATUS_PCIX_MODE = 0x00002000 ; PCI-X mode |
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137 | STATUS_PCIXSPD_MASK = 0x0000C000 ; PCI-X speed |
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138 | STATUS_PCIXSPD_SHIFT = 14 |
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139 | |||
140 | ; CTRL_EXT - Extended Device Control Register (0x0018) |
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141 | CTRLEXT_PHY_INT = 0x00000020 ; PHY interrupt |
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142 | CTRLEXT_SDP6_DATA = 0x00000040 ; SDP6 data |
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143 | CTRLEXT_SDP7_DATA = 0x00000080 ; SDP7 data |
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144 | CTRLEXT_SDP6_IODIR = 0x00000400 ; SDP6 direction |
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145 | CTRLEXT_SDP7_IODIR = 0x00000800 ; SDP7 direction |
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146 | CTRLEXT_ASDCHK = 0x00001000 ; Auto-Speed Detect Chk |
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147 | CTRLEXT_EE_RST = 0x00002000 ; EEPROM reset |
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148 | CTRLEXT_SPD_BYPS = 0x00008000 ; Speed Select Bypass |
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149 | CTRLEXT_RO_DIS = 0x00020000 ; Relaxed Ordering Dis. |
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150 | CTRLEXT_LNKMOD_MASK = 0x00C00000 ; Link Mode |
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151 | CTRLEXT_LNKMOD_SHIFT = 22 |
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152 | |||
153 | ; MDIC - MDI Control Register (0x0020) |
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154 | MDIC_DATA_MASK = 0x0000FFFF ; Data |
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155 | MDIC_REG_MASK = 0x001F0000 ; PHY Register |
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156 | MDIC_REG_SHIFT = 16 |
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157 | MDIC_PHY_MASK = 0x03E00000 ; PHY Address |
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158 | MDIC_PHY_SHIFT = 21 |
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159 | MDIC_OP_MASK = 0x0C000000 ; Opcode |
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160 | MDIC_OP_SHIFT = 26 |
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161 | MDIC_R = 0x10000000 ; Ready |
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162 | MDIC_I = 0x20000000 ; Interrupt Enable |
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163 | MDIC_E = 0x40000000 ; Error |
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164 | |||
165 | ; ICR - Interrupt Cause Read (0x00c0) |
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166 | ICR_TXDW = 0x00000001 ; TX Desc Written back |
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167 | ICR_TXQE = 0x00000002 ; TX Queue Empty |
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168 | ICR_LSC = 0x00000004 ; Link Status Change |
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169 | ICR_RXSEQ = 0x00000008 ; RX Sence Error |
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170 | ICR_RXDMT0 = 0x00000010 ; RX Desc min threshold reached |
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171 | ICR_RXO = 0x00000040 ; RX Overrun |
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172 | ICR_RXT0 = 0x00000080 ; RX Timer Interrupt |
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173 | ICR_MDAC = 0x00000200 ; MDIO Access Complete |
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174 | ICR_RXCFG = 0x00000400 |
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175 | ICR_PHY_INT = 0x00001000 ; PHY Interrupt |
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176 | ICR_GPI_SDP6 = 0x00002000 ; GPI on SDP6 |
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177 | ICR_GPI_SDP7 = 0x00004000 ; GPI on SDP7 |
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178 | ICR_TXD_LOW = 0x00008000 ; TX Desc low threshold hit |
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179 | ICR_SRPD = 0x00010000 ; Small RX packet detected |
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180 | |||
181 | ; RCTL - Receive Control Register (0x0100) |
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182 | RCTL_EN = 0x00000002 ; Receiver Enable |
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183 | RCTL_SBP = 0x00000004 ; Store Bad Packets |
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184 | RCTL_UPE = 0x00000008 ; Unicast Promiscuous Enabled |
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185 | RCTL_MPE = 0x00000010 ; Xcast Promiscuous Enabled |
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186 | RCTL_LPE = 0x00000020 ; Long Packet Reception Enable |
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187 | RCTL_LBM_MASK = 0x000000C0 ; Loopback Mode |
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188 | RCTL_LBM_SHIFT = 6 |
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189 | RCTL_RDMTS_MASK = 0x00000300 ; RX Desc Min Threshold Size |
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190 | RCTL_RDMTS_SHIFT = 8 |
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191 | RCTL_MO_MASK = 0x00003000 ; Multicast Offset |
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192 | RCTL_MO_SHIFT = 12 |
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193 | RCTL_BAM = 0x00008000 ; Broadcast Accept Mode |
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194 | RCTL_BSIZE_MASK = 0x00030000 ; RX Buffer Size |
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195 | RCTL_BSIZE_SHIFT = 16 |
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196 | RCTL_VFE = 0x00040000 ; VLAN Filter Enable |
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197 | RCTL_CFIEN = 0x00080000 ; CFI Enable |
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198 | RCTL_CFI = 0x00100000 ; Canonical Form Indicator Bit |
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199 | RCTL_DPF = 0x00400000 ; Discard Pause Frames |
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200 | RCTL_PMCF = 0x00800000 ; Pass MAC Control Frames |
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201 | RCTL_BSEX = 0x02000000 ; Buffer Size Extension |
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202 | RCTL_SECRC = 0x04000000 ; Strip Ethernet CRC |
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203 | |||
204 | ; TCTL - Transmit Control Register (0x0400) |
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205 | TCTL_EN = 0x00000002 ; Transmit Enable |
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206 | TCTL_PSP = 0x00000008 ; Pad short packets |
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207 | TCTL_SWXOFF = 0x00400000 ; Software XOFF Transmission |
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208 | |||
209 | ; PBA - Packet Buffer Allocation (0x1000) |
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210 | PBA_RXA_MASK = 0x0000FFFF ; RX Packet Buffer |
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211 | PBA_RXA_SHIFT = 0 |
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212 | PBA_TXA_MASK = 0xFFFF0000 ; TX Packet Buffer |
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213 | PBA_TXA_SHIFT = 16 |
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214 | |||
215 | ; Flow Control Type |
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216 | FCT_TYPE_DEFAULT = 0x8808 |
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217 | |||
218 | ; === TX Descriptor fields === |
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219 | |||
220 | ; TX Packet Length (word 2) |
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221 | TXDESC_LEN_MASK = 0x0000ffff |
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222 | |||
223 | ; TX Descriptor CMD field (word 2) |
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224 | TXDESC_IDE = 0x80000000 ; Interrupt Delay Enable |
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225 | TXDESC_VLE = 0x40000000 ; VLAN Packet Enable |
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226 | TXDESC_DEXT = 0x20000000 ; Extension |
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227 | TXDESC_RPS = 0x10000000 ; Report Packet Sent |
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228 | TXDESC_RS = 0x08000000 ; Report Status |
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229 | TXDESC_IC = 0x04000000 ; Insert Checksum |
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230 | TXDESC_IFCS = 0x02000000 ; Insert FCS |
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231 | TXDESC_EOP = 0x01000000 ; End Of Packet |
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232 | |||
233 | ; TX Descriptor STA field (word 3) |
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234 | TXDESC_TU = 0x00000008 ; Transmit Underrun |
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235 | TXDESC_LC = 0x00000004 ; Late Collision |
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236 | TXDESC_EC = 0x00000002 ; Excess Collisions |
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237 | TXDESC_DD = 0x00000001 ; Descriptor Done |
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238 | |||
239 | ; === RX Descriptor fields === |
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240 | |||
241 | ; RX Packet Length (word 2) |
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242 | RXDESC_LEN_MASK = 0x0000ffff |
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243 | |||
244 | ; RX Descriptor STA field (word 3) |
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245 | RXDESC_PIF = 0x00000080 ; Passed In-exact Filter |
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246 | RXDESC_IPCS = 0x00000040 ; IP cksum calculated |
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247 | RXDESC_TCPCS = 0x00000020 ; TCP cksum calculated |
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248 | RXDESC_VP = 0x00000008 ; Packet is 802.1Q |
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249 | RXDESC_IXSM = 0x00000004 ; Ignore cksum indication |
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250 | RXDESC_EOP = 0x00000002 ; End Of Packet |
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251 | RXDESC_DD = 0x00000001 ; Descriptor Done |
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252 | |||
253 | |||
254 | virtual at ebx |
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255 | device: |
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256 | ETH_DEVICE |
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257 | |||
258 | .mmio_addr dd ? |
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259 | .pci_bus dd ? |
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260 | .pci_dev dd ? |
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261 | .irq_line db ? |
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262 | |||
263 | .cur_tx dd ? |
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264 | .last_tx dd ? |
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265 | |||
266 | rb 0x100 - (($ - device) and 0xff) |
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267 | .rx_desc rd 256/8 |
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268 | |||
269 | rb 0x100 - (($ - device) and 0xff) |
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270 | .tx_desc rd 256/8 |
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271 | |||
272 | sizeof.device_struct = $ - device |
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273 | |||
274 | end virtual |
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275 | |||
276 | section '.flat' code readable align 16 |
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277 | |||
278 | |||
279 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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280 | ;; ;; |
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281 | ;; proc START ;; |
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282 | ;; ;; |
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283 | ;; (standard driver proc) ;; |
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284 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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285 | |||
286 | align 4 |
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287 | proc START stdcall, state:dword |
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288 | |||
289 | cmp [state], 1 |
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290 | jne .exit |
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291 | |||
292 | .entry: |
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293 | |||
3855 | hidnplayr | 294 | DEBUGF 1,"Loading driver\n" |
3545 | hidnplayr | 295 | stdcall RegService, my_service, service_proc |
296 | ret |
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297 | |||
298 | .fail: |
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299 | .exit: |
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300 | xor eax, eax |
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301 | ret |
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302 | |||
303 | endp |
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304 | |||
305 | |||
306 | |||
307 | |||
308 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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309 | ;; ;; |
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310 | ;; proc SERVICE_PROC ;; |
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311 | ;; ;; |
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312 | ;; (standard driver proc) ;; |
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313 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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314 | |||
315 | align 4 |
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316 | proc service_proc stdcall, ioctl:dword |
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317 | |||
318 | mov edx, [ioctl] |
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319 | mov eax, [IOCTL.io_code] |
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320 | |||
321 | ;------------------------------------------------------ |
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322 | |||
323 | cmp eax, 0 ;SRV_GETVERSION |
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324 | jne @F |
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325 | |||
326 | cmp [IOCTL.out_size], 4 |
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327 | jb .fail |
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328 | mov eax, [IOCTL.output] |
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329 | mov [eax], dword API_VERSION |
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330 | |||
331 | xor eax, eax |
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332 | ret |
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333 | |||
334 | ;------------------------------------------------------ |
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335 | @@: |
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336 | cmp eax, 1 ;SRV_HOOK |
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337 | jne .fail |
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338 | |||
339 | cmp [IOCTL.inp_size], 3 ; Data input must be at least 3 bytes |
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340 | jb .fail |
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341 | |||
342 | mov eax, [IOCTL.input] |
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343 | cmp byte [eax], 1 ; 1 means device number and bus number (pci) are given |
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344 | jne .fail ; other types arent supported for this card yet |
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345 | |||
346 | ; check if the device is already listed |
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347 | |||
348 | mov esi, device_list |
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349 | mov ecx, [devices] |
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350 | test ecx, ecx |
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351 | jz .firstdevice |
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352 | |||
353 | ; mov eax, [IOCTL.input] ; get the pci bus and device numbers |
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354 | mov ax, [eax+1] ; |
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355 | .nextdevice: |
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356 | mov ebx, [esi] |
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357 | cmp al, byte [device.pci_bus] |
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358 | jne .next |
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359 | cmp ah, byte [device.pci_dev] |
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360 | je .find_devicenum ; Device is already loaded, let's find it's device number |
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361 | .next: |
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362 | add esi, 4 |
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363 | loop .nextdevice |
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364 | |||
365 | |||
366 | ; This device doesnt have its own eth_device structure yet, lets create one |
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367 | .firstdevice: |
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368 | cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card |
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369 | jae .fail |
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370 | |||
371 | allocate_and_clear ebx, sizeof.device_struct, .fail ; Allocate the buffer for device structure |
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372 | |||
373 | ; Fill in the direct call addresses into the struct |
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374 | |||
375 | mov [device.reset], reset |
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376 | mov [device.transmit], transmit |
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377 | mov [device.unload], unload |
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378 | mov [device.name], my_service |
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379 | |||
380 | ; save the pci bus and device numbers |
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381 | |||
382 | mov eax, [IOCTL.input] |
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383 | movzx ecx, byte [eax+1] |
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384 | mov [device.pci_bus], ecx |
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385 | movzx ecx, byte [eax+2] |
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386 | mov [device.pci_dev], ecx |
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387 | |||
388 | ; Now, it's time to find the base mmio addres of the PCI device |
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389 | |||
390 | PCI_find_mmio32 |
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391 | |||
392 | ; Create virtual mapping of the physical memory |
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393 | |||
394 | push 1Bh ; PG_SW+PG_NOCACHE |
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395 | push 10000h ; size of the map |
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396 | push eax |
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397 | call MapIoMem |
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398 | mov [device.mmio_addr], eax |
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399 | |||
400 | ; We've found the mmio address, find IRQ now |
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401 | |||
402 | PCI_find_irq |
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403 | |||
404 | DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\ |
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405 | [device.pci_dev]:1,[device.pci_bus]:1,[device.irq_line]:1,[device.mmio_addr]:8 |
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406 | |||
407 | ; Ok, the eth_device structure is ready, let's probe the device |
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408 | call probe ; this function will output in eax |
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409 | test eax, eax |
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410 | jnz .err ; If an error occured, exit |
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411 | |||
412 | mov eax, [devices] ; Add the device structure to our device list |
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413 | mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device) |
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414 | inc [devices] ; |
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415 | |||
416 | call start_i8254x |
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417 | |||
418 | mov [device.type], NET_TYPE_ETH |
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419 | call NetRegDev |
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420 | |||
421 | cmp eax, -1 |
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422 | je .destroy |
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423 | |||
424 | ret |
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425 | |||
426 | ; If the device was already loaded, find the device number and return it in eax |
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427 | |||
428 | .find_devicenum: |
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429 | DEBUGF 1,"Trying to find device number of already registered device\n" |
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430 | call NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx |
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431 | ; into a device number in edi |
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432 | mov eax, edi ; Application wants it in eax instead |
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433 | DEBUGF 1,"Kernel says: %u\n", eax |
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434 | ret |
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435 | |||
436 | ; If an error occured, remove all allocated data and exit (returning -1 in eax) |
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437 | |||
438 | .destroy: |
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439 | ; todo: reset device into virgin state |
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440 | |||
441 | .err: |
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442 | stdcall KernelFree, ebx |
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443 | |||
444 | .fail: |
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445 | or eax, -1 |
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446 | ret |
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447 | |||
448 | ;------------------------------------------------------ |
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449 | endp |
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450 | |||
451 | |||
452 | ;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;; |
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453 | ;; ;; |
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454 | ;; Actual Hardware dependent code starts here ;; |
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455 | ;; ;; |
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456 | ;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;; |
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457 | |||
458 | |||
459 | align 4 |
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460 | unload: |
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461 | ; TODO: (in this particular order) |
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462 | ; |
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463 | ; - Stop the device |
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464 | ; - Detach int handler |
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465 | ; - Remove device from local list (device_list) |
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466 | ; - call unregister function in kernel |
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467 | ; - Remove all allocated structures and buffers the card used |
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468 | |||
469 | or eax, -1 |
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470 | |||
471 | ret |
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472 | |||
473 | |||
474 | |||
475 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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476 | ;; |
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477 | ;; probe: enables the device (if it really is I8254X) |
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478 | ;; |
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479 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
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480 | align 4 |
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481 | probe: |
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482 | |||
483 | DEBUGF 1,"Probe\n" |
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484 | |||
485 | PCI_make_bus_master |
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486 | |||
487 | ; TODO: validate the device |
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488 | |||
489 | call read_mac |
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490 | |||
491 | movzx eax, [device.irq_line] |
||
492 | DEBUGF 1,"Attaching int handler to irq %x\n", eax:1 |
||
493 | stdcall AttachIntHandler, eax, int_handler, dword 0 |
||
494 | test eax, eax |
||
495 | jnz @f |
||
3855 | hidnplayr | 496 | DEBUGF 2,"Could not attach int handler!\n" |
3545 | hidnplayr | 497 | ; or eax, -1 |
498 | ; ret |
||
499 | @@: |
||
500 | |||
501 | |||
502 | reset_dontstart: |
||
503 | DEBUGF 1,"Reset\n" |
||
504 | |||
505 | mov esi, [device.mmio_addr] |
||
506 | |||
507 | or dword [esi + REG_CTRL], CTRL_RST ; reset device |
||
508 | .loop: |
||
509 | push esi |
||
510 | xor esi, esi |
||
511 | inc esi |
||
512 | call Sleep |
||
513 | pop esi |
||
514 | test dword [esi + REG_CTRL], CTRL_RST |
||
515 | jnz .loop |
||
516 | |||
517 | mov dword [esi + REG_IMC], 0xffffffff ; Disable all interrupt causes |
||
518 | mov eax, dword [esi + REG_ICR] ; Clear any pending interrupts |
||
519 | mov dword [esi + REG_ITR], 0 ; Disable interrupt throttling logic |
||
520 | |||
521 | mov dword [esi + REG_PBA], 0x00000030 ; PBA: set the RX buffer size to 48KB (TX buffer is calculated as 64-RX buffer) |
||
522 | mov dword [esi + REG_RDTR], 0 ; RDTR: set no delay |
||
523 | |||
524 | mov dword [esi + REG_TXCW], 0x08008060 ; TXCW: set ANE, TxConfigWord (Half/Full duplex, Next Page Reqest) |
||
525 | |||
526 | mov eax, [esi + REG_CTRL] |
||
527 | or eax, 1 shl 6 + 1 shl 5 |
||
528 | and eax, not (1 shl 3 + 1 shl 7 + 1 shl 30 + 1 shl 31) |
||
529 | mov dword [esi + REG_CTRL], eax ; CTRL: clear LRST, set SLU and ASDE, clear RSTPHY, VME, and ILOS |
||
530 | |||
531 | lea edi, [esi + 0x5200] ; MTA: reset |
||
532 | mov eax, 0xffffffff |
||
533 | stosd |
||
534 | stosd |
||
535 | stosd |
||
536 | stosd |
||
537 | |||
538 | stdcall KernelAlloc, 48*1024 |
||
539 | mov dword [device.rx_desc + 16], eax |
||
540 | GetRealAddr |
||
541 | mov dword [device.rx_desc], eax |
||
542 | mov dword [device.rx_desc + 4], 0 |
||
543 | |||
544 | lea eax, [device.rx_desc] |
||
545 | GetRealAddr |
||
546 | mov dword [esi + REG_RDBAL], eax ; Receive Descriptor Base Address Low |
||
547 | mov dword [esi + REG_RDBAH], 0 ; Receive Descriptor Base Address High |
||
548 | mov dword [esi + REG_RDLEN], (1 * 128) ; Receive Descriptor Length |
||
549 | mov dword [esi + REG_RDH], 0 ; Receive Descriptor Head |
||
550 | mov dword [esi + REG_RDT], 1 ; Receive Descriptor Tail |
||
551 | mov dword [esi + REG_RCTL], RCTL_EN or RCTL_SBP or RCTL_BAM or RCTL_SECRC or RCTL_UPE or RCTL_MPE |
||
552 | ; Receiver Enable, Store Bad Packets, Broadcast Accept Mode, Strip Ethernet CRC from incoming packet, Promiscuous mode |
||
553 | |||
554 | mov dword [device.tx_desc], 0 |
||
555 | mov dword [device.tx_desc + 4], 0 |
||
556 | mov dword [device.tx_desc + 16], 0 |
||
557 | |||
558 | lea eax, [device.tx_desc] |
||
559 | GetRealAddr |
||
560 | mov dword [esi + REG_TDBAL], eax ; Transmit Descriptor Base Address Low |
||
561 | mov dword [esi + REG_TDBAH], 0 ; Transmit Descriptor Base Address High |
||
562 | mov dword [esi + REG_TDLEN], (1 * 128) ; Transmit Descriptor Length |
||
563 | mov dword [esi + REG_TDH], 0 ; Transmit Descriptor Head |
||
564 | mov dword [esi + REG_TDT], 0 ; Transmit Descriptor Tail |
||
565 | mov dword [esi + REG_TCTL], 0x010400fa ; Enabled, Pad Short Packets, 15 retrys, 64-byte COLD, Re-transmit on Late Collision |
||
566 | mov dword [esi + REG_TIPG], 0x0060200A ; IPGT 10, IPGR1 8, IPGR2 6 |
||
567 | |||
568 | xor eax, eax |
||
569 | ret |
||
570 | |||
571 | align 4 |
||
572 | reset: |
||
573 | call reset_dontstart |
||
574 | |||
575 | start_i8254x: |
||
576 | |||
577 | xor eax, eax |
||
578 | mov [esi + REG_RDTR], eax ; Clear the Receive Delay Timer Register |
||
579 | mov [esi + REG_RADV], eax ; Clear the Receive Interrupt Absolute Delay Timer |
||
580 | mov [esi + REG_RSRPD], eax ; Clear the Receive Small Packet Detect Interrupt |
||
581 | ; or eax, 1 shl 0 + 1 shl 7 ; TXDW + RXT0 |
||
582 | mov eax, 1+4+16 ;;;; hack! |
||
583 | mov [esi + REG_IMS], eax ; Enable interrupt types |
||
584 | |||
585 | mov [device.mtu], 1514 |
||
586 | |||
587 | ; Set link state to unknown |
||
588 | mov [device.state], ETH_LINK_UNKOWN |
||
589 | |||
590 | xor eax, eax |
||
591 | ret |
||
592 | |||
593 | |||
594 | |||
595 | |||
596 | align 4 |
||
597 | read_mac: |
||
598 | |||
599 | DEBUGF 1,"Read MAC\n" |
||
600 | |||
601 | mov esi, [device.mmio_addr] |
||
602 | |||
603 | mov eax, [esi+0x5400] ; RAL |
||
604 | test eax, eax |
||
605 | jz .try_eeprom |
||
606 | |||
607 | mov dword [device.mac], eax |
||
608 | mov eax, [esi+0x5404] ; RAH |
||
609 | mov word [device.mac+4], ax |
||
610 | |||
611 | jmp .mac_ok |
||
612 | |||
613 | .try_eeprom: |
||
614 | mov dword [esi+0x14], 0x00000001 |
||
615 | mov eax, [esi+0x14] |
||
616 | shr eax, 16 |
||
617 | mov word [device.mac], ax |
||
618 | |||
619 | mov dword [esi+0x14], 0x00000101 |
||
620 | mov eax, [esi+0x14] |
||
621 | shr eax, 16 |
||
622 | mov word [device.mac+2], ax |
||
623 | |||
624 | mov dword [esi+0x14], 0x00000201 |
||
625 | mov eax, [esi+0x14] |
||
626 | shr eax, 16 |
||
627 | mov word [device.mac+4], ax |
||
628 | |||
629 | .mac_ok: |
||
630 | DEBUGF 1,"MAC = %x-%x-%x-%x-%x-%x\n",\ |
||
631 | [device.mac+0]:2,[device.mac+1]:2,[device.mac+2]:2,[device.mac+3]:2,[device.mac+4]:2,[device.mac+5]:2 |
||
632 | |||
633 | ret |
||
634 | |||
635 | |||
636 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
637 | ;; ;; |
||
638 | ;; Transmit ;; |
||
639 | ;; ;; |
||
640 | ;; In: buffer pointer in [esp+4] ;; |
||
641 | ;; size of buffer in [esp+8] ;; |
||
642 | ;; pointer to device structure in ebx ;; |
||
643 | ;; ;; |
||
644 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
645 | align 4 |
||
646 | transmit: |
||
3788 | hidnplayr | 647 | DEBUGF 1,"\nTransmitting packet, buffer:%x, size:%u\n", [esp+4], [esp+8] |
3545 | hidnplayr | 648 | mov eax, [esp+4] |
3788 | hidnplayr | 649 | DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\ |
3545 | hidnplayr | 650 | [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\ |
651 | [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\ |
||
652 | [eax+13]:2,[eax+12]:2 |
||
653 | |||
654 | cmp dword [esp + 8], 1514 |
||
655 | ja .fail |
||
656 | cmp dword [esp + 8], 60 |
||
657 | jb .fail |
||
658 | |||
659 | |||
660 | ; Program the descriptor (use legacy mode) |
||
661 | lea edi, [device.tx_desc] ; Transmit Descriptor Base Address |
||
662 | mov dword [edi + 16], eax ; Store the data location (for driver) |
||
663 | GetRealAddr ; |
||
664 | mov dword [edi], eax ; Real addr (for i8254x) |
||
665 | mov dword [edi + 4], 0x00000000 ; |
||
666 | |||
667 | mov ecx, [esp + 8] |
||
668 | or ecx, 1 shl 24 + 1 shl 25 + 1 shl 27 ; EOP + IFCS + RS |
||
669 | mov dword [edi + 8], ecx ; Packet size |
||
670 | mov dword [edi + 12], 0x00000000 |
||
671 | |||
672 | ; Tell i8254x wich descriptor(s) we programmed |
||
673 | mov edi, [device.mmio_addr] |
||
674 | mov dword [edi + REG_TDH], 0 ; TDH - Transmit Descriptor Head |
||
675 | mov dword [edi + REG_TDT], 1 ; TDT - Transmit Descriptor Tail |
||
676 | |||
677 | ; Update stats |
||
678 | inc [device.packets_tx] |
||
679 | mov eax, [esp + 8] |
||
680 | add dword [device.bytes_tx], eax |
||
681 | adc dword [device.bytes_tx + 4], 0 |
||
682 | |||
683 | ret 8 |
||
684 | |||
685 | .fail: |
||
3788 | hidnplayr | 686 | DEBUGF 2,"Send failed\n" |
3545 | hidnplayr | 687 | ret 8 |
688 | |||
689 | |||
690 | ;;;;;;;;;;;;;;;;;;;;;;; |
||
691 | ;; ;; |
||
692 | ;; Interrupt handler ;; |
||
693 | ;; ;; |
||
694 | ;;;;;;;;;;;;;;;;;;;;;;; |
||
695 | |||
696 | align 4 |
||
697 | int_handler: |
||
698 | |||
699 | push ebx esi edi |
||
700 | |||
3855 | hidnplayr | 701 | DEBUGF 1,"INT\n" |
3545 | hidnplayr | 702 | ;------------------------------------------- |
703 | ; Find pointer of device wich made IRQ occur |
||
704 | |||
705 | mov ecx, [devices] |
||
706 | test ecx, ecx |
||
707 | jz .nothing |
||
708 | mov esi, device_list |
||
709 | .nextdevice: |
||
710 | mov ebx, [esi] |
||
711 | |||
712 | mov edi, [device.mmio_addr] |
||
713 | mov eax, [edi + REG_ICR] |
||
714 | test eax, eax |
||
715 | jnz .got_it |
||
716 | .continue: |
||
717 | add esi, 4 |
||
718 | dec ecx |
||
719 | jnz .nextdevice |
||
720 | .nothing: |
||
721 | pop edi esi ebx |
||
722 | xor eax, eax |
||
723 | |||
724 | ret |
||
725 | |||
726 | .got_it: |
||
727 | |||
728 | DEBUGF 1,"Device: %x Status: %x ", ebx, eax |
||
729 | |||
730 | ;--------- |
||
731 | ; RX done? |
||
732 | |||
733 | test eax, ICR_RXDMT0 |
||
734 | jz .no_rx |
||
735 | |||
736 | push eax ebx |
||
737 | push .retaddr |
||
738 | |||
739 | ; Get last descriptor addr |
||
740 | lea esi, [device.rx_desc] |
||
741 | |||
742 | cmp byte [esi + 12], 0 ; Check status field |
||
743 | je .retaddr |
||
744 | |||
745 | movzx ecx, word [esi + 8] ; Get the packet length |
||
3788 | hidnplayr | 746 | DEBUGF 1,"got %u bytes\n", ecx |
3545 | hidnplayr | 747 | push ecx |
748 | push dword [esi + 16] ; Get packet pointer |
||
749 | |||
750 | ; Update stats |
||
751 | add dword [device.bytes_rx], ecx |
||
752 | adc dword [device.bytes_rx + 4], 0 |
||
753 | inc dword [device.packets_rx] |
||
754 | |||
755 | ; allocate new descriptor |
||
756 | stdcall KernelAlloc, 48*1024 |
||
757 | mov dword [esi + 16], eax |
||
758 | GetRealAddr |
||
759 | mov dword [esi], eax |
||
760 | |||
761 | ; reset descriptor status |
||
762 | mov esi, [device.mmio_addr] |
||
763 | mov dword [esi + REG_RDH], 0x00000000 ; Receive Descriptor Head |
||
764 | mov dword [esi + REG_RDT], 0x00000001 ; Receive Descriptor Tail |
||
765 | |||
766 | jmp Eth_input |
||
767 | .retaddr: |
||
768 | pop ebx eax |
||
769 | |||
770 | .no_rx: |
||
771 | |||
772 | ;-------------- |
||
773 | ; Link Changed? |
||
774 | |||
775 | test eax, ICR_LSC |
||
776 | jz .no_link |
||
777 | |||
3788 | hidnplayr | 778 | DEBUGF 1,"Link Changed\n" |
3545 | hidnplayr | 779 | |
780 | .no_link: |
||
781 | |||
782 | ;--------------- |
||
783 | ; Transmit done? |
||
784 | |||
785 | test eax, ICR_TXDW |
||
786 | jz .no_tx |
||
787 | |||
3788 | hidnplayr | 788 | DEBUGF 1,"Transmit done\n" |
3545 | hidnplayr | 789 | |
790 | lea edi, [device.tx_desc] ; Transmit Descriptor Base Address |
||
791 | push dword [edi + 16] ; Store the data location (for driver) |
||
792 | call KernelFree |
||
793 | |||
794 | .no_tx: |
||
795 | .fail: |
||
796 | pop edi esi ebx |
||
797 | xor eax, eax |
||
798 | inc eax |
||
799 | |||
800 | ret |
||
801 | |||
802 | |||
803 | |||
804 | |||
805 | ; End of code |
||
806 | |||
807 | section '.data' data readable writable align 16 |
||
808 | align 4 |
||
809 | |||
810 | devices dd 0 |
||
811 | version dd (DRIVER_VERSION shl 16) or (API_VERSION and 0xFFFF) |
||
812 | my_service db 'I8254X',0 ; max 16 chars include zero |
||
813 | |||
814 | include_debug_strings ; All data wich FDO uses will be included here |
||
815 | |||
816 | device_list rd MAX_DEVICES ; This list contains all pointers to device structures the driver is handling |
||
817 |