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Rev | Author | Line No. | Line |
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6595 | serge | 1 | /******************************************************************************* |
2 | * |
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3 | * Module Name: hwregs - Read/write access functions for the various ACPI |
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4 | * control and status registers. |
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5 | * |
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6 | ******************************************************************************/ |
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7 | |||
8 | /* |
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9 | * Copyright (C) 2000 - 2015, Intel Corp. |
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10 | * All rights reserved. |
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11 | * |
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12 | * Redistribution and use in source and binary forms, with or without |
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13 | * modification, are permitted provided that the following conditions |
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14 | * are met: |
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15 | * 1. Redistributions of source code must retain the above copyright |
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16 | * notice, this list of conditions, and the following disclaimer, |
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17 | * without modification. |
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18 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer |
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19 | * substantially similar to the "NO WARRANTY" disclaimer below |
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20 | * ("Disclaimer") and any redistribution must be conditioned upon |
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21 | * including a substantially similar Disclaimer requirement for further |
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22 | * binary redistribution. |
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23 | * 3. Neither the names of the above-listed copyright holders nor the names |
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24 | * of any contributors may be used to endorse or promote products derived |
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25 | * from this software without specific prior written permission. |
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26 | * |
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27 | * Alternatively, this software may be distributed under the terms of the |
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28 | * GNU General Public License ("GPL") version 2 as published by the Free |
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29 | * Software Foundation. |
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30 | * |
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31 | * NO WARRANTY |
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32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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33 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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34 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR |
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35 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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36 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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37 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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38 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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39 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
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40 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
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41 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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42 | * POSSIBILITY OF SUCH DAMAGES. |
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43 | */ |
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44 | |||
45 | #include |
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46 | #include "accommon.h" |
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47 | #include "acevents.h" |
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48 | |||
49 | #define _COMPONENT ACPI_HARDWARE |
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50 | ACPI_MODULE_NAME("hwregs") |
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51 | |||
52 | #if (!ACPI_REDUCED_HARDWARE) |
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53 | /* Local Prototypes */ |
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54 | static acpi_status |
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55 | acpi_hw_read_multiple(u32 *value, |
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56 | struct acpi_generic_address *register_a, |
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57 | struct acpi_generic_address *register_b); |
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58 | |||
59 | static acpi_status |
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60 | acpi_hw_write_multiple(u32 value, |
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61 | struct acpi_generic_address *register_a, |
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62 | struct acpi_generic_address *register_b); |
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63 | |||
64 | #endif /* !ACPI_REDUCED_HARDWARE */ |
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65 | |||
66 | /****************************************************************************** |
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67 | * |
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68 | * FUNCTION: acpi_hw_validate_register |
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69 | * |
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70 | * PARAMETERS: reg - GAS register structure |
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71 | * max_bit_width - Max bit_width supported (32 or 64) |
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72 | * address - Pointer to where the gas->address |
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73 | * is returned |
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74 | * |
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75 | * RETURN: Status |
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76 | * |
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77 | * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS |
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78 | * pointer, Address, space_id, bit_width, and bit_offset. |
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79 | * |
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80 | ******************************************************************************/ |
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81 | |||
82 | acpi_status |
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83 | acpi_hw_validate_register(struct acpi_generic_address *reg, |
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84 | u8 max_bit_width, u64 *address) |
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85 | { |
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86 | |||
87 | /* Must have a valid pointer to a GAS structure */ |
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88 | |||
89 | if (!reg) { |
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90 | return (AE_BAD_PARAMETER); |
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91 | } |
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92 | |||
93 | /* |
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94 | * Copy the target address. This handles possible alignment issues. |
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95 | * Address must not be null. A null address also indicates an optional |
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96 | * ACPI register that is not supported, so no error message. |
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97 | */ |
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98 | ACPI_MOVE_64_TO_64(address, ®->address); |
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99 | if (!(*address)) { |
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100 | return (AE_BAD_ADDRESS); |
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101 | } |
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102 | |||
103 | /* Validate the space_ID */ |
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104 | |||
105 | if ((reg->space_id != ACPI_ADR_SPACE_SYSTEM_MEMORY) && |
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106 | (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO)) { |
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107 | ACPI_ERROR((AE_INFO, |
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108 | "Unsupported address space: 0x%X", reg->space_id)); |
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109 | return (AE_SUPPORT); |
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110 | } |
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111 | |||
112 | /* Validate the bit_width */ |
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113 | |||
114 | if ((reg->bit_width != 8) && |
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115 | (reg->bit_width != 16) && |
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116 | (reg->bit_width != 32) && (reg->bit_width != max_bit_width)) { |
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117 | ACPI_ERROR((AE_INFO, |
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118 | "Unsupported register bit width: 0x%X", |
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119 | reg->bit_width)); |
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120 | return (AE_SUPPORT); |
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121 | } |
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122 | |||
123 | /* Validate the bit_offset. Just a warning for now. */ |
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124 | |||
125 | if (reg->bit_offset != 0) { |
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126 | ACPI_WARNING((AE_INFO, |
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127 | "Unsupported register bit offset: 0x%X", |
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128 | reg->bit_offset)); |
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129 | } |
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130 | |||
131 | return (AE_OK); |
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132 | } |
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133 | |||
134 | /****************************************************************************** |
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135 | * |
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136 | * FUNCTION: acpi_hw_read |
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137 | * |
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138 | * PARAMETERS: value - Where the value is returned |
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139 | * reg - GAS register structure |
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140 | * |
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141 | * RETURN: Status |
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142 | * |
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143 | * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max |
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144 | * version of acpi_read, used internally since the overhead of |
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145 | * 64-bit values is not needed. |
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146 | * |
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147 | * LIMITATIONS: |
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148 | * bit_width must be exactly 8, 16, or 32. |
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149 | * space_ID must be system_memory or system_IO. |
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150 | * bit_offset and access_width are currently ignored, as there has |
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151 | * not been a need to implement these. |
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152 | * |
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153 | ******************************************************************************/ |
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154 | |||
155 | acpi_status acpi_hw_read(u32 *value, struct acpi_generic_address *reg) |
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156 | { |
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157 | u64 address; |
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158 | u64 value64; |
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159 | acpi_status status; |
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160 | |||
161 | ACPI_FUNCTION_NAME(hw_read); |
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162 | |||
163 | /* Validate contents of the GAS register */ |
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164 | |||
165 | status = acpi_hw_validate_register(reg, 32, &address); |
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166 | if (ACPI_FAILURE(status)) { |
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167 | return (status); |
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168 | } |
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169 | |||
170 | /* Initialize entire 32-bit return value to zero */ |
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171 | |||
172 | *value = 0; |
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173 | |||
174 | /* |
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175 | * Two address spaces supported: Memory or IO. PCI_Config is |
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176 | * not supported here because the GAS structure is insufficient |
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177 | */ |
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178 | if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { |
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179 | status = acpi_os_read_memory((acpi_physical_address) |
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180 | address, &value64, reg->bit_width); |
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181 | |||
182 | *value = (u32)value64; |
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183 | } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ |
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184 | |||
185 | status = acpi_hw_read_port((acpi_io_address) |
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186 | address, value, reg->bit_width); |
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187 | } |
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188 | |||
189 | ACPI_DEBUG_PRINT((ACPI_DB_IO, |
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190 | "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n", |
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191 | *value, reg->bit_width, ACPI_FORMAT_UINT64(address), |
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192 | acpi_ut_get_region_name(reg->space_id))); |
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193 | |||
194 | return (status); |
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195 | } |
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196 | |||
197 | /****************************************************************************** |
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198 | * |
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199 | * FUNCTION: acpi_hw_write |
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200 | * |
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201 | * PARAMETERS: value - Value to be written |
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202 | * reg - GAS register structure |
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203 | * |
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204 | * RETURN: Status |
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205 | * |
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206 | * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max |
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207 | * version of acpi_write, used internally since the overhead of |
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208 | * 64-bit values is not needed. |
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209 | * |
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210 | ******************************************************************************/ |
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211 | |||
212 | acpi_status acpi_hw_write(u32 value, struct acpi_generic_address *reg) |
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213 | { |
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214 | u64 address; |
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215 | acpi_status status; |
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216 | |||
217 | ACPI_FUNCTION_NAME(hw_write); |
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218 | |||
219 | /* Validate contents of the GAS register */ |
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220 | |||
221 | status = acpi_hw_validate_register(reg, 32, &address); |
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222 | if (ACPI_FAILURE(status)) { |
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223 | return (status); |
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224 | } |
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225 | |||
226 | /* |
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227 | * Two address spaces supported: Memory or IO. PCI_Config is |
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228 | * not supported here because the GAS structure is insufficient |
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229 | */ |
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230 | if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) { |
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231 | status = acpi_os_write_memory((acpi_physical_address) |
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232 | address, (u64)value, |
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233 | reg->bit_width); |
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234 | } else { /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ |
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235 | |||
236 | status = acpi_hw_write_port((acpi_io_address) |
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237 | address, value, reg->bit_width); |
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238 | } |
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239 | |||
240 | ACPI_DEBUG_PRINT((ACPI_DB_IO, |
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241 | "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n", |
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242 | value, reg->bit_width, ACPI_FORMAT_UINT64(address), |
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243 | acpi_ut_get_region_name(reg->space_id))); |
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244 | |||
245 | return (status); |
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246 | } |
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247 | |||
248 | #if (!ACPI_REDUCED_HARDWARE) |
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249 | /******************************************************************************* |
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250 | * |
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251 | * FUNCTION: acpi_hw_clear_acpi_status |
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252 | * |
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253 | * PARAMETERS: None |
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254 | * |
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255 | * RETURN: Status |
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256 | * |
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257 | * DESCRIPTION: Clears all fixed and general purpose status bits |
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258 | * |
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259 | ******************************************************************************/ |
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260 | |||
261 | acpi_status acpi_hw_clear_acpi_status(void) |
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262 | { |
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263 | acpi_status status; |
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264 | acpi_cpu_flags lock_flags = 0; |
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265 | |||
266 | ACPI_FUNCTION_TRACE(hw_clear_acpi_status); |
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267 | |||
268 | ACPI_DEBUG_PRINT((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n", |
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269 | ACPI_BITMASK_ALL_FIXED_STATUS, |
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270 | ACPI_FORMAT_UINT64(acpi_gbl_xpm1a_status.address))); |
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271 | |||
272 | lock_flags = acpi_os_acquire_lock(acpi_gbl_hardware_lock); |
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273 | |||
274 | /* Clear the fixed events in PM1 A/B */ |
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275 | |||
276 | status = acpi_hw_register_write(ACPI_REGISTER_PM1_STATUS, |
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277 | ACPI_BITMASK_ALL_FIXED_STATUS); |
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278 | |||
279 | acpi_os_release_lock(acpi_gbl_hardware_lock, lock_flags); |
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280 | |||
281 | if (ACPI_FAILURE(status)) { |
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282 | goto exit; |
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283 | } |
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284 | |||
285 | /* Clear the GPE Bits in all GPE registers in all GPE blocks */ |
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286 | |||
287 | status = acpi_ev_walk_gpe_list(acpi_hw_clear_gpe_block, NULL); |
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288 | |||
289 | exit: |
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290 | return_ACPI_STATUS(status); |
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291 | } |
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292 | |||
293 | /******************************************************************************* |
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294 | * |
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295 | * FUNCTION: acpi_hw_get_bit_register_info |
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296 | * |
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297 | * PARAMETERS: register_id - Index of ACPI Register to access |
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298 | * |
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299 | * RETURN: The bitmask to be used when accessing the register |
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300 | * |
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301 | * DESCRIPTION: Map register_id into a register bitmask. |
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302 | * |
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303 | ******************************************************************************/ |
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304 | |||
305 | struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id) |
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306 | { |
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307 | ACPI_FUNCTION_ENTRY(); |
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308 | |||
309 | if (register_id > ACPI_BITREG_MAX) { |
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310 | ACPI_ERROR((AE_INFO, "Invalid BitRegister ID: 0x%X", |
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311 | register_id)); |
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312 | return (NULL); |
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313 | } |
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314 | |||
315 | return (&acpi_gbl_bit_register_info[register_id]); |
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316 | } |
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317 | |||
318 | /****************************************************************************** |
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319 | * |
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320 | * FUNCTION: acpi_hw_write_pm1_control |
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321 | * |
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322 | * PARAMETERS: pm1a_control - Value to be written to PM1A control |
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323 | * pm1b_control - Value to be written to PM1B control |
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324 | * |
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325 | * RETURN: Status |
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326 | * |
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327 | * DESCRIPTION: Write the PM1 A/B control registers. These registers are |
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328 | * different than than the PM1 A/B status and enable registers |
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329 | * in that different values can be written to the A/B registers. |
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330 | * Most notably, the SLP_TYP bits can be different, as per the |
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331 | * values returned from the _Sx predefined methods. |
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332 | * |
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333 | ******************************************************************************/ |
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334 | |||
335 | acpi_status acpi_hw_write_pm1_control(u32 pm1a_control, u32 pm1b_control) |
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336 | { |
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337 | acpi_status status; |
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338 | |||
339 | ACPI_FUNCTION_TRACE(hw_write_pm1_control); |
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340 | |||
341 | status = |
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342 | acpi_hw_write(pm1a_control, &acpi_gbl_FADT.xpm1a_control_block); |
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343 | if (ACPI_FAILURE(status)) { |
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344 | return_ACPI_STATUS(status); |
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345 | } |
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346 | |||
347 | if (acpi_gbl_FADT.xpm1b_control_block.address) { |
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348 | status = |
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349 | acpi_hw_write(pm1b_control, |
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350 | &acpi_gbl_FADT.xpm1b_control_block); |
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351 | } |
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352 | return_ACPI_STATUS(status); |
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353 | } |
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354 | |||
355 | /****************************************************************************** |
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356 | * |
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357 | * FUNCTION: acpi_hw_register_read |
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358 | * |
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359 | * PARAMETERS: register_id - ACPI Register ID |
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360 | * return_value - Where the register value is returned |
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361 | * |
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362 | * RETURN: Status and the value read. |
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363 | * |
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364 | * DESCRIPTION: Read from the specified ACPI register |
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365 | * |
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366 | ******************************************************************************/ |
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367 | acpi_status acpi_hw_register_read(u32 register_id, u32 *return_value) |
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368 | { |
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369 | u32 value = 0; |
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370 | acpi_status status; |
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371 | |||
372 | ACPI_FUNCTION_TRACE(hw_register_read); |
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373 | |||
374 | switch (register_id) { |
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375 | case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ |
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376 | |||
377 | status = acpi_hw_read_multiple(&value, |
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378 | &acpi_gbl_xpm1a_status, |
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379 | &acpi_gbl_xpm1b_status); |
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380 | break; |
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381 | |||
382 | case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */ |
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383 | |||
384 | status = acpi_hw_read_multiple(&value, |
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385 | &acpi_gbl_xpm1a_enable, |
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386 | &acpi_gbl_xpm1b_enable); |
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387 | break; |
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388 | |||
389 | case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */ |
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390 | |||
391 | status = acpi_hw_read_multiple(&value, |
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392 | &acpi_gbl_FADT. |
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393 | xpm1a_control_block, |
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394 | &acpi_gbl_FADT. |
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395 | xpm1b_control_block); |
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396 | |||
397 | /* |
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398 | * Zero the write-only bits. From the ACPI specification, "Hardware |
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399 | * Write-Only Bits": "Upon reads to registers with write-only bits, |
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400 | * software masks out all write-only bits." |
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401 | */ |
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402 | value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS; |
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403 | break; |
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404 | |||
405 | case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */ |
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406 | |||
407 | status = |
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408 | acpi_hw_read(&value, &acpi_gbl_FADT.xpm2_control_block); |
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409 | break; |
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410 | |||
411 | case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ |
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412 | |||
413 | status = acpi_hw_read(&value, &acpi_gbl_FADT.xpm_timer_block); |
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414 | break; |
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415 | |||
416 | case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ |
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417 | |||
418 | status = |
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419 | acpi_hw_read_port(acpi_gbl_FADT.smi_command, &value, 8); |
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420 | break; |
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421 | |||
422 | default: |
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423 | |||
424 | ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id)); |
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425 | status = AE_BAD_PARAMETER; |
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426 | break; |
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427 | } |
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428 | |||
429 | if (ACPI_SUCCESS(status)) { |
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430 | *return_value = value; |
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431 | } |
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432 | |||
433 | return_ACPI_STATUS(status); |
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434 | } |
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435 | |||
436 | /****************************************************************************** |
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437 | * |
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438 | * FUNCTION: acpi_hw_register_write |
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439 | * |
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440 | * PARAMETERS: register_id - ACPI Register ID |
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441 | * value - The value to write |
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442 | * |
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443 | * RETURN: Status |
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444 | * |
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445 | * DESCRIPTION: Write to the specified ACPI register |
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446 | * |
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447 | * NOTE: In accordance with the ACPI specification, this function automatically |
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448 | * preserves the value of the following bits, meaning that these bits cannot be |
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449 | * changed via this interface: |
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450 | * |
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451 | * PM1_CONTROL[0] = SCI_EN |
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452 | * PM1_CONTROL[9] |
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453 | * PM1_STATUS[11] |
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454 | * |
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455 | * ACPI References: |
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456 | * 1) Hardware Ignored Bits: When software writes to a register with ignored |
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457 | * bit fields, it preserves the ignored bit fields |
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458 | * 2) SCI_EN: OSPM always preserves this bit position |
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459 | * |
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460 | ******************************************************************************/ |
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461 | |||
462 | acpi_status acpi_hw_register_write(u32 register_id, u32 value) |
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463 | { |
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464 | acpi_status status; |
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465 | u32 read_value; |
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466 | |||
467 | ACPI_FUNCTION_TRACE(hw_register_write); |
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468 | |||
469 | switch (register_id) { |
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470 | case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ |
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471 | /* |
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472 | * Handle the "ignored" bit in PM1 Status. According to the ACPI |
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473 | * specification, ignored bits are to be preserved when writing. |
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474 | * Normally, this would mean a read/modify/write sequence. However, |
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475 | * preserving a bit in the status register is different. Writing a |
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476 | * one clears the status, and writing a zero preserves the status. |
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477 | * Therefore, we must always write zero to the ignored bit. |
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478 | * |
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479 | * This behavior is clarified in the ACPI 4.0 specification. |
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480 | */ |
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481 | value &= ~ACPI_PM1_STATUS_PRESERVED_BITS; |
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482 | |||
483 | status = acpi_hw_write_multiple(value, |
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484 | &acpi_gbl_xpm1a_status, |
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485 | &acpi_gbl_xpm1b_status); |
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486 | break; |
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487 | |||
488 | case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */ |
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489 | |||
490 | status = acpi_hw_write_multiple(value, |
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491 | &acpi_gbl_xpm1a_enable, |
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492 | &acpi_gbl_xpm1b_enable); |
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493 | break; |
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494 | |||
495 | case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */ |
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496 | /* |
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497 | * Perform a read first to preserve certain bits (per ACPI spec) |
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498 | * Note: This includes SCI_EN, we never want to change this bit |
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499 | */ |
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500 | status = acpi_hw_read_multiple(&read_value, |
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501 | &acpi_gbl_FADT. |
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502 | xpm1a_control_block, |
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503 | &acpi_gbl_FADT. |
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504 | xpm1b_control_block); |
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505 | if (ACPI_FAILURE(status)) { |
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506 | goto exit; |
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507 | } |
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508 | |||
509 | /* Insert the bits to be preserved */ |
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510 | |||
511 | ACPI_INSERT_BITS(value, ACPI_PM1_CONTROL_PRESERVED_BITS, |
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512 | read_value); |
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513 | |||
514 | /* Now we can write the data */ |
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515 | |||
516 | status = acpi_hw_write_multiple(value, |
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517 | &acpi_gbl_FADT. |
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518 | xpm1a_control_block, |
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519 | &acpi_gbl_FADT. |
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520 | xpm1b_control_block); |
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521 | break; |
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522 | |||
523 | case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */ |
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524 | /* |
||
525 | * For control registers, all reserved bits must be preserved, |
||
526 | * as per the ACPI spec. |
||
527 | */ |
||
528 | status = |
||
529 | acpi_hw_read(&read_value, |
||
530 | &acpi_gbl_FADT.xpm2_control_block); |
||
531 | if (ACPI_FAILURE(status)) { |
||
532 | goto exit; |
||
533 | } |
||
534 | |||
535 | /* Insert the bits to be preserved */ |
||
536 | |||
537 | ACPI_INSERT_BITS(value, ACPI_PM2_CONTROL_PRESERVED_BITS, |
||
538 | read_value); |
||
539 | |||
540 | status = |
||
541 | acpi_hw_write(value, &acpi_gbl_FADT.xpm2_control_block); |
||
542 | break; |
||
543 | |||
544 | case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ |
||
545 | |||
546 | status = acpi_hw_write(value, &acpi_gbl_FADT.xpm_timer_block); |
||
547 | break; |
||
548 | |||
549 | case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ |
||
550 | |||
551 | /* SMI_CMD is currently always in IO space */ |
||
552 | |||
553 | status = |
||
554 | acpi_hw_write_port(acpi_gbl_FADT.smi_command, value, 8); |
||
555 | break; |
||
556 | |||
557 | default: |
||
558 | |||
559 | ACPI_ERROR((AE_INFO, "Unknown Register ID: 0x%X", register_id)); |
||
560 | status = AE_BAD_PARAMETER; |
||
561 | break; |
||
562 | } |
||
563 | |||
564 | exit: |
||
565 | return_ACPI_STATUS(status); |
||
566 | } |
||
567 | |||
568 | /****************************************************************************** |
||
569 | * |
||
570 | * FUNCTION: acpi_hw_read_multiple |
||
571 | * |
||
572 | * PARAMETERS: value - Where the register value is returned |
||
573 | * register_a - First ACPI register (required) |
||
574 | * register_b - Second ACPI register (optional) |
||
575 | * |
||
576 | * RETURN: Status |
||
577 | * |
||
578 | * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B) |
||
579 | * |
||
580 | ******************************************************************************/ |
||
581 | |||
582 | static acpi_status |
||
583 | acpi_hw_read_multiple(u32 *value, |
||
584 | struct acpi_generic_address *register_a, |
||
585 | struct acpi_generic_address *register_b) |
||
586 | { |
||
587 | u32 value_a = 0; |
||
588 | u32 value_b = 0; |
||
589 | acpi_status status; |
||
590 | |||
591 | /* The first register is always required */ |
||
592 | |||
593 | status = acpi_hw_read(&value_a, register_a); |
||
594 | if (ACPI_FAILURE(status)) { |
||
595 | return (status); |
||
596 | } |
||
597 | |||
598 | /* Second register is optional */ |
||
599 | |||
600 | if (register_b->address) { |
||
601 | status = acpi_hw_read(&value_b, register_b); |
||
602 | if (ACPI_FAILURE(status)) { |
||
603 | return (status); |
||
604 | } |
||
605 | } |
||
606 | |||
607 | /* |
||
608 | * OR the two return values together. No shifting or masking is necessary, |
||
609 | * because of how the PM1 registers are defined in the ACPI specification: |
||
610 | * |
||
611 | * "Although the bits can be split between the two register blocks (each |
||
612 | * register block has a unique pointer within the FADT), the bit positions |
||
613 | * are maintained. The register block with unimplemented bits (that is, |
||
614 | * those implemented in the other register block) always returns zeros, |
||
615 | * and writes have no side effects" |
||
616 | */ |
||
617 | *value = (value_a | value_b); |
||
618 | return (AE_OK); |
||
619 | } |
||
620 | |||
621 | /****************************************************************************** |
||
622 | * |
||
623 | * FUNCTION: acpi_hw_write_multiple |
||
624 | * |
||
625 | * PARAMETERS: value - The value to write |
||
626 | * register_a - First ACPI register (required) |
||
627 | * register_b - Second ACPI register (optional) |
||
628 | * |
||
629 | * RETURN: Status |
||
630 | * |
||
631 | * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B) |
||
632 | * |
||
633 | ******************************************************************************/ |
||
634 | |||
635 | static acpi_status |
||
636 | acpi_hw_write_multiple(u32 value, |
||
637 | struct acpi_generic_address *register_a, |
||
638 | struct acpi_generic_address *register_b) |
||
639 | { |
||
640 | acpi_status status; |
||
641 | |||
642 | /* The first register is always required */ |
||
643 | |||
644 | status = acpi_hw_write(value, register_a); |
||
645 | if (ACPI_FAILURE(status)) { |
||
646 | return (status); |
||
647 | } |
||
648 | |||
649 | /* |
||
650 | * Second register is optional |
||
651 | * |
||
652 | * No bit shifting or clearing is necessary, because of how the PM1 |
||
653 | * registers are defined in the ACPI specification: |
||
654 | * |
||
655 | * "Although the bits can be split between the two register blocks (each |
||
656 | * register block has a unique pointer within the FADT), the bit positions |
||
657 | * are maintained. The register block with unimplemented bits (that is, |
||
658 | * those implemented in the other register block) always returns zeros, |
||
659 | * and writes have no side effects" |
||
660 | */ |
||
661 | if (register_b->address) { |
||
662 | status = acpi_hw_write(value, register_b); |
||
663 | } |
||
664 | |||
665 | return (status); |
||
666 | } |
||
667 | |||
668 | #endif /* !ACPI_REDUCED_HARDWARE */ |