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5191 | serge | 1 | /* ARM assembler/disassembler support. |
6324 | serge | 2 | Copyright (C) 2004-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | |
4 | This file is part of GDB and GAS. |
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5 | |||
6 | GDB and GAS are free software; you can redistribute it and/or |
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7 | modify it under the terms of the GNU General Public License as |
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8 | published by the Free Software Foundation; either version 3, or (at |
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9 | your option) any later version. |
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10 | |||
11 | GDB and GAS are distributed in the hope that it will be useful, but |
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12 | WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | General Public License for more details. |
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15 | |||
16 | You should have received a copy of the GNU General Public License |
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17 | along with GDB or GAS; see the file COPYING3. If not, write to the |
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18 | Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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19 | MA 02110-1301, USA. */ |
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20 | |||
21 | /* The following bitmasks control CPU extensions: */ |
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22 | #define ARM_EXT_V1 0x00000001 /* All processors (core set). */ |
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23 | #define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ |
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24 | #define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ |
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25 | #define ARM_EXT_V3 0x00000008 /* MSR MRS. */ |
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26 | #define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ |
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27 | #define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ |
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28 | #define ARM_EXT_V4T 0x00000040 /* Thumb. */ |
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29 | #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ |
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30 | #define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ |
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31 | #define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ |
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32 | #define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ |
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33 | #define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ |
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34 | #define ARM_EXT_V6 0x00001000 /* ARM V6. */ |
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35 | #define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ |
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36 | /* 0x00004000 Was ARM V6Z. */ |
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37 | #define ARM_EXT_V8 0x00004000 /* is now ARMv8. */ |
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38 | #define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ |
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39 | #define ARM_EXT_DIV 0x00010000 /* Integer division. */ |
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40 | /* The 'M' in Arm V7M stands for Microcontroller. |
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41 | On earlier architecture variants it stands for Multiply. */ |
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42 | #define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ |
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43 | #define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ |
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44 | #define ARM_EXT_V7 0x00080000 /* Arm V7. */ |
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45 | #define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ |
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46 | #define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ |
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47 | #define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ |
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48 | #define ARM_EXT_V6M 0x00800000 /* ARM V6M. */ |
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49 | #define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */ |
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50 | #define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */ |
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51 | #define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related), |
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52 | not in v7-M. */ |
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53 | #define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */ |
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54 | #define ARM_EXT_SEC 0x10000000 /* Security extensions. */ |
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55 | #define ARM_EXT_OS 0x20000000 /* OS Extensions. */ |
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56 | #define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM |
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57 | state. */ |
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58 | #define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */ |
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59 | |||
6324 | serge | 60 | #define ARM_EXT2_PAN 0x00000001 /* PAN extension. */ |
61 | |||
5191 | serge | 62 | /* Co-processor space extensions. */ |
63 | #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ |
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64 | #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ |
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65 | #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ |
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66 | #define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ |
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67 | |||
68 | #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ |
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69 | #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ |
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70 | #define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ |
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71 | #define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ |
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72 | #define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ |
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73 | #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ |
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74 | #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ |
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75 | #define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ |
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76 | #define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */ |
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77 | #define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */ |
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78 | #define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */ |
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79 | #define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */ |
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80 | #define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */ |
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81 | #define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */ |
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82 | #define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */ |
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6324 | serge | 83 | #define FPU_VFP_EXT_ARMV8 0x00020000 /* Double-precision FP for ARMv8. */ |
5191 | serge | 84 | #define FPU_NEON_EXT_ARMV8 0x00010000 /* Neon for ARMv8. */ |
85 | #define FPU_CRYPTO_EXT_ARMV8 0x00008000 /* Crypto for ARMv8. */ |
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86 | #define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */ |
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6324 | serge | 87 | #define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */ |
88 | #define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */ |
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5191 | serge | 89 | |
90 | /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) |
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91 | defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, |
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92 | ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add |
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93 | three more to cover cores prior to ARM6. Finally, there are cores which |
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94 | implement further extensions in the co-processor space. */ |
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95 | #define ARM_AEXT_V1 ARM_EXT_V1 |
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96 | #define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) |
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97 | #define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) |
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98 | #define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) |
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99 | #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) |
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100 | #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) |
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101 | #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) |
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102 | #define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) |
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103 | #define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) |
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104 | #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) |
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105 | #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) |
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106 | #define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) |
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107 | #define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) |
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108 | #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) |
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109 | #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) |
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110 | #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) |
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111 | #define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) |
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112 | #define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) |
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113 | #define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC) |
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6324 | serge | 114 | #define ARM_AEXT_V6KZ (ARM_AEXT_V6K | ARM_EXT_SEC) |
5191 | serge | 115 | #define ARM_AEXT_V6T2 (ARM_AEXT_V6 \ |
116 | | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \ |
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117 | | ARM_EXT_V6_DSP ) |
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118 | #define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) |
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119 | #define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC) |
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6324 | serge | 120 | #define ARM_AEXT_V6KZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC) |
5191 | serge | 121 | #define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER) |
122 | #define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) |
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123 | #define ARM_AEXT_V7VE (ARM_AEXT_V7A | ARM_EXT_DIV | ARM_EXT_ADIV \ |
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124 | | ARM_EXT_VIRT | ARM_EXT_SEC | ARM_EXT_MP) |
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125 | #define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) |
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126 | #define ARM_AEXT_NOTM \ |
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127 | (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \ |
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128 | | ARM_EXT_V6_DSP ) |
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129 | #define ARM_AEXT_V6M_ONLY \ |
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130 | ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM)) |
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131 | #define ARM_AEXT_V6M \ |
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132 | ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM)) |
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133 | #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS) |
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134 | #define ARM_AEXT_V7M \ |
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135 | ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \ |
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136 | & ~(ARM_AEXT_NOTM)) |
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137 | #define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) |
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138 | #define ARM_AEXT_V7EM \ |
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139 | (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP) |
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140 | #define ARM_AEXT_V8A \ |
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141 | (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \ |
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142 | | ARM_EXT_VIRT | ARM_EXT_V8) |
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143 | |||
144 | /* Processors with specific extensions in the co-processor space. */ |
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6324 | serge | 145 | #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) |
5191 | serge | 146 | #define ARM_ARCH_IWMMXT \ |
6324 | serge | 147 | ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) |
5191 | serge | 148 | #define ARM_ARCH_IWMMXT2 \ |
6324 | serge | 149 | ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT \ |
150 | | ARM_CEXT_IWMMXT2) |
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5191 | serge | 151 | |
152 | #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) |
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153 | #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) |
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154 | #define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) |
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155 | #define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3) |
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156 | #define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32) |
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157 | #define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD) |
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158 | #define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) |
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159 | #define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) |
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160 | #define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA) |
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6324 | serge | 161 | #define FPU_VFP_V5D16 (FPU_VFP_V4D16 | FPU_VFP_EXT_ARMV8xD | FPU_VFP_EXT_ARMV8) |
162 | #define FPU_VFP_V5_SP_D16 (FPU_VFP_V4_SP_D16 | FPU_VFP_EXT_ARMV8xD) |
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163 | #define FPU_VFP_ARMV8 (FPU_VFP_V4 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD) |
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5191 | serge | 164 | #define FPU_NEON_ARMV8 (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA | FPU_NEON_EXT_ARMV8) |
165 | #define FPU_CRYPTO_ARMV8 (FPU_CRYPTO_EXT_ARMV8) |
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166 | #define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ |
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167 | | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \ |
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168 | | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32) |
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169 | #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) |
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170 | |||
171 | /* Deprecated. */ |
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6324 | serge | 172 | #define FPU_ARCH_VFP ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) |
5191 | serge | 173 | |
6324 | serge | 174 | #define FPU_ARCH_FPE ARM_FEATURE_COPROC (FPU_FPA_EXT_V1) |
175 | #define FPU_ARCH_FPA ARM_FEATURE_COPROC (FPU_FPA) |
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5191 | serge | 176 | |
6324 | serge | 177 | #define FPU_ARCH_VFP_V1xD ARM_FEATURE_COPROC (FPU_VFP_V1xD) |
178 | #define FPU_ARCH_VFP_V1 ARM_FEATURE_COPROC (FPU_VFP_V1) |
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179 | #define FPU_ARCH_VFP_V2 ARM_FEATURE_COPROC (FPU_VFP_V2) |
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180 | #define FPU_ARCH_VFP_V3D16 ARM_FEATURE_COPROC (FPU_VFP_V3D16) |
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5191 | serge | 181 | #define FPU_ARCH_VFP_V3D16_FP16 \ |
6324 | serge | 182 | ARM_FEATURE_COPROC (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16) |
183 | #define FPU_ARCH_VFP_V3 ARM_FEATURE_COPROC (FPU_VFP_V3) |
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184 | #define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_VFP_EXT_FP16) |
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185 | #define FPU_ARCH_VFP_V3xD ARM_FEATURE_COPROC (FPU_VFP_V3xD) |
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186 | #define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE_COPROC (FPU_VFP_V3xD \ |
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187 | | FPU_VFP_EXT_FP16) |
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188 | #define FPU_ARCH_NEON_V1 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1) |
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5191 | serge | 189 | #define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ |
6324 | serge | 190 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1) |
5191 | serge | 191 | #define FPU_ARCH_NEON_FP16 \ |
6324 | serge | 192 | ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16) |
193 | #define FPU_ARCH_VFP_HARD ARM_FEATURE_COPROC (FPU_VFP_HARD) |
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194 | #define FPU_ARCH_VFP_V4 ARM_FEATURE_COPROC (FPU_VFP_V4) |
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195 | #define FPU_ARCH_VFP_V4D16 ARM_FEATURE_COPROC (FPU_VFP_V4D16) |
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196 | #define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16) |
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197 | #define FPU_ARCH_VFP_V5D16 ARM_FEATURE_COPROC (FPU_VFP_V5D16) |
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198 | #define FPU_ARCH_VFP_V5_SP_D16 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16) |
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5191 | serge | 199 | #define FPU_ARCH_NEON_VFP_V4 \ |
6324 | serge | 200 | ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA) |
201 | #define FPU_ARCH_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_VFP_ARMV8) |
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202 | #define FPU_ARCH_NEON_VFP_ARMV8 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \ |
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203 | | FPU_VFP_ARMV8) |
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5191 | serge | 204 | #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8 \ |
6324 | serge | 205 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8) |
206 | #define ARCH_CRC_ARMV8 ARM_FEATURE_COPROC (CRC_EXT_ARMV8) |
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207 | #define FPU_ARCH_NEON_VFP_ARMV8_1 \ |
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208 | ARM_FEATURE_COPROC (FPU_NEON_ARMV8 \ |
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209 | | FPU_VFP_ARMV8 \ |
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210 | | FPU_NEON_EXT_RDMA) |
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211 | #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \ |
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212 | ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \ |
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213 | | FPU_NEON_EXT_RDMA) |
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5191 | serge | 214 | |
215 | |||
6324 | serge | 216 | #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) |
5191 | serge | 217 | |
6324 | serge | 218 | #define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK) |
5191 | serge | 219 | |
6324 | serge | 220 | #define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1) |
221 | #define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2) |
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222 | #define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S) |
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223 | #define ARM_ARCH_V3 ARM_FEATURE_CORE_LOW (ARM_AEXT_V3) |
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224 | #define ARM_ARCH_V3M ARM_FEATURE_CORE_LOW (ARM_AEXT_V3M) |
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225 | #define ARM_ARCH_V4xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4xM) |
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226 | #define ARM_ARCH_V4 ARM_FEATURE_CORE_LOW (ARM_AEXT_V4) |
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227 | #define ARM_ARCH_V4TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V4TxM) |
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228 | #define ARM_ARCH_V4T ARM_FEATURE_CORE_LOW (ARM_AEXT_V4T) |
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229 | #define ARM_ARCH_V5xM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5xM) |
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230 | #define ARM_ARCH_V5 ARM_FEATURE_CORE_LOW (ARM_AEXT_V5) |
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231 | #define ARM_ARCH_V5TxM ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TxM) |
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232 | #define ARM_ARCH_V5T ARM_FEATURE_CORE_LOW (ARM_AEXT_V5T) |
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233 | #define ARM_ARCH_V5TExP ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TExP) |
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234 | #define ARM_ARCH_V5TE ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TE) |
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235 | #define ARM_ARCH_V5TEJ ARM_FEATURE_CORE_LOW (ARM_AEXT_V5TEJ) |
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236 | #define ARM_ARCH_V6 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6) |
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237 | #define ARM_ARCH_V6K ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K) |
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238 | #define ARM_ARCH_V6Z ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z) |
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239 | #define ARM_ARCH_V6KZ ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ) |
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240 | #define ARM_ARCH_V6T2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6T2) |
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241 | #define ARM_ARCH_V6KT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KT2) |
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242 | #define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZT2) |
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243 | #define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZT2) |
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244 | #define ARM_ARCH_V6M ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M) |
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245 | #define ARM_ARCH_V6SM ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM) |
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246 | #define ARM_ARCH_V7 ARM_FEATURE_CORE_LOW (ARM_AEXT_V7) |
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247 | #define ARM_ARCH_V7A ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A) |
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248 | #define ARM_ARCH_V7VE ARM_FEATURE_CORE_LOW (ARM_AEXT_V7VE) |
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249 | #define ARM_ARCH_V7R ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R) |
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250 | #define ARM_ARCH_V7M ARM_FEATURE_CORE_LOW (ARM_AEXT_V7M) |
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251 | #define ARM_ARCH_V7EM ARM_FEATURE_CORE_LOW (ARM_AEXT_V7EM) |
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252 | #define ARM_ARCH_V8A ARM_FEATURE_CORE_LOW (ARM_AEXT_V8A) |
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253 | #define ARM_ARCH_V8_1A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_EXT2_PAN) |
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254 | |||
5191 | serge | 255 | /* Some useful combinations: */ |
6324 | serge | 256 | #define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0) |
257 | #define FPU_NONE ARM_FEATURE_LOW (0, 0) |
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258 | #define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */ |
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259 | #define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features. */ |
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260 | #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) |
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261 | #define ARM_ARCH_THUMB2 ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2 | ARM_EXT_V7 \ |
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262 | | ARM_EXT_V7A | ARM_EXT_V7R \ |
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263 | | ARM_EXT_V7M | ARM_EXT_DIV \ |
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264 | | ARM_EXT_V8) |
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5191 | serge | 265 | /* v7-a+sec. */ |
6324 | serge | 266 | #define ARM_ARCH_V7A_SEC ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_SEC) |
5191 | serge | 267 | /* v7-a+mp+sec. */ |
268 | #define ARM_ARCH_V7A_MP_SEC \ |
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6324 | serge | 269 | ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC) |
5191 | serge | 270 | /* v7-r+idiv. */ |
6324 | serge | 271 | #define ARM_ARCH_V7R_IDIV ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R | ARM_EXT_ADIV) |
5191 | serge | 272 | /* Features that are present in v6M and v6S-M but not other v6 cores. */ |
6324 | serge | 273 | #define ARM_ARCH_V6M_ONLY ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M_ONLY) |
5191 | serge | 274 | /* v8-a+fp. */ |
6324 | serge | 275 | #define ARM_ARCH_V8A_FP ARM_FEATURE_LOW (ARM_AEXT_V8A, FPU_ARCH_VFP_ARMV8) |
5191 | serge | 276 | /* v8-a+simd (implies fp). */ |
6324 | serge | 277 | #define ARM_ARCH_V8A_SIMD ARM_FEATURE_LOW (ARM_AEXT_V8A, \ |
5191 | serge | 278 | FPU_ARCH_NEON_VFP_ARMV8) |
279 | /* v8-a+crypto (implies simd+fp). */ |
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6324 | serge | 280 | #define ARM_ARCH_V8A_CRYPTOV1 ARM_FEATURE_LOW (ARM_AEXT_V8A, \ |
5191 | serge | 281 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) |
282 | |||
6324 | serge | 283 | /* v8.1-a+fp. */ |
284 | #define ARM_ARCH_V8_1A_FP ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \ |
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285 | FPU_ARCH_VFP_ARMV8) |
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286 | /* v8.1-a+simd (implies fp). */ |
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287 | #define ARM_ARCH_V8_1A_SIMD ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \ |
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288 | FPU_ARCH_NEON_VFP_ARMV8_1) |
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289 | /* v8.1-a+crypto (implies simd+fp). */ |
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290 | #define ARM_ARCH_V8_1A_CRYPTOV1 ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_PAN, \ |
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291 | FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1) |
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292 | |||
293 | |||
5191 | serge | 294 | /* There are too many feature bits to fit in a single word, so use a |
6324 | serge | 295 | structure. For simplicity we put all core features in array CORE |
296 | and everything else in the other. All the bits in element core[0] |
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297 | have been occupied, so new feature should use bit in element core[1] |
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298 | and use macro ARM_FEATURE to initialize the feature set variable. */ |
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5191 | serge | 299 | typedef struct |
300 | { |
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6324 | serge | 301 | unsigned long core[2]; |
5191 | serge | 302 | unsigned long coproc; |
303 | } arm_feature_set; |
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304 | |||
305 | #define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ |
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6324 | serge | 306 | (((CPU).core[0] & (FEAT).core[0]) != 0 \ |
307 | || ((CPU).core[1] & (FEAT).core[1]) != 0 \ |
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308 | || ((CPU).coproc & (FEAT).coproc) != 0) |
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5191 | serge | 309 | |
310 | #define ARM_CPU_IS_ANY(CPU) \ |
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6324 | serge | 311 | ((CPU).core[0] == ((arm_feature_set)ARM_ANY).core[0] \ |
312 | && (CPU).core[1] == ((arm_feature_set)ARM_ANY).core[1]) |
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5191 | serge | 313 | |
314 | #define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ |
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315 | do { \ |
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6324 | serge | 316 | (TARG).core[0] = (F1).core[0] | (F2).core[0];\ |
317 | (TARG).core[1] = (F1).core[1] | (F2).core[1];\ |
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5191 | serge | 318 | (TARG).coproc = (F1).coproc | (F2).coproc; \ |
319 | } while (0) |
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320 | |||
321 | #define ARM_CLEAR_FEATURE(TARG,F1,F2) \ |
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322 | do { \ |
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6324 | serge | 323 | (TARG).core[0] = (F1).core[0] &~ (F2).core[0];\ |
324 | (TARG).core[1] = (F1).core[1] &~ (F2).core[1];\ |
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5191 | serge | 325 | (TARG).coproc = (F1).coproc &~ (F2).coproc; \ |
326 | } while (0) |
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327 | |||
6324 | serge | 328 | #define ARM_FEATURE_COPY(F1, F2) \ |
329 | do { \ |
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330 | (F1).core[0] = (F2).core[0]; \ |
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331 | (F1).core[1] = (F2).core[1]; \ |
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332 | (F1).coproc = (F2).coproc; \ |
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333 | } while (0) |
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334 | |||
335 | #define ARM_FEATURE_EQUAL(T1,T2) \ |
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336 | ((T1).core[0] == (T2).core[0] \ |
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337 | && (T1).core[1] == (T2).core[1] \ |
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338 | && (T1).coproc == (T2).coproc) |
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339 | |||
340 | #define ARM_FEATURE_ZERO(T) \ |
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341 | ((T).core[0] == 0 && (T).core[1] == 0 && (T).coproc == 0) |
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342 | |||
343 | #define ARM_FEATURE_CORE_EQUAL(T1, T2) \ |
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344 | ((T1).core[0] == (T2).core[0] && (T1).core[1] == (T2).core[1]) |
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345 | |||
346 | #define ARM_FEATURE_LOW(core, coproc) {{(core), 0}, (coproc)} |
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347 | #define ARM_FEATURE_CORE(core1, core2) {{(core1), (core2)}, 0} |
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348 | #define ARM_FEATURE_CORE_LOW(core) {{(core), 0}, 0} |
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349 | #define ARM_FEATURE_CORE_HIGH(core) {{0, (core)}, 0} |
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350 | #define ARM_FEATURE_COPROC(coproc) {{0, 0}, (coproc)} |
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351 | #define ARM_FEATURE(core1, core2, coproc) {{(core1), (core2)}, (coproc)} |