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4358 | Serge | 1 | /********************************************************** |
2 | * Copyright 2008-2009 VMware, Inc. All rights reserved. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person |
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5 | * obtaining a copy of this software and associated documentation |
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6 | * files (the "Software"), to deal in the Software without |
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7 | * restriction, including without limitation the rights to use, copy, |
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8 | * modify, merge, publish, distribute, sublicense, and/or sell copies |
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9 | * of the Software, and to permit persons to whom the Software is |
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10 | * furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be |
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13 | * included in all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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18 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
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19 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
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20 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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22 | * SOFTWARE. |
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23 | * |
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24 | **********************************************************/ |
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25 | |||
26 | #include "util/u_format.h" |
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27 | #include "util/u_inlines.h" |
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28 | #include "util/u_memory.h" |
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29 | #include "pipe/p_defines.h" |
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30 | #include "util/u_math.h" |
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31 | |||
32 | #include "svga_context.h" |
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33 | #include "svga_screen.h" |
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34 | #include "svga_state.h" |
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35 | #include "svga_cmd.h" |
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36 | |||
37 | |||
38 | struct rs_queue { |
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39 | unsigned rs_count; |
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40 | SVGA3dRenderState rs[SVGA3D_RS_MAX]; |
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41 | }; |
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42 | |||
43 | |||
44 | #define EMIT_RS(svga, value, token, fail) \ |
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45 | do { \ |
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46 | assert(SVGA3D_RS_##token < Elements(svga->state.hw_draw.rs)); \ |
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47 | if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) { \ |
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48 | svga_queue_rs( &queue, SVGA3D_RS_##token, value ); \ |
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49 | svga->state.hw_draw.rs[SVGA3D_RS_##token] = value; \ |
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50 | } \ |
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51 | } while (0) |
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52 | |||
53 | #define EMIT_RS_FLOAT(svga, fvalue, token, fail) \ |
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54 | do { \ |
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55 | unsigned value = fui(fvalue); \ |
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56 | assert(SVGA3D_RS_##token < Elements(svga->state.hw_draw.rs)); \ |
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57 | if (svga->state.hw_draw.rs[SVGA3D_RS_##token] != value) { \ |
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58 | svga_queue_rs( &queue, SVGA3D_RS_##token, value ); \ |
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59 | svga->state.hw_draw.rs[SVGA3D_RS_##token] = value; \ |
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60 | } \ |
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61 | } while (0) |
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62 | |||
63 | |||
64 | static INLINE void |
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65 | svga_queue_rs( struct rs_queue *q, |
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66 | unsigned rss, |
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67 | unsigned value ) |
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68 | { |
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69 | q->rs[q->rs_count].state = rss; |
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70 | q->rs[q->rs_count].uintValue = value; |
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71 | q->rs_count++; |
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72 | } |
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73 | |||
74 | |||
75 | /* Compare old and new render states and emit differences between them |
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76 | * to hardware. Simplest implementation would be to emit the whole of |
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77 | * the "to" state. |
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78 | */ |
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79 | static enum pipe_error |
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80 | emit_rss(struct svga_context *svga, unsigned dirty) |
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81 | { |
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82 | struct svga_screen *screen = svga_screen(svga->pipe.screen); |
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83 | struct rs_queue queue; |
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84 | float point_size_min; |
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85 | |||
86 | queue.rs_count = 0; |
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87 | |||
88 | if (dirty & SVGA_NEW_BLEND) { |
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89 | const struct svga_blend_state *curr = svga->curr.blend; |
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90 | |||
91 | EMIT_RS( svga, curr->rt[0].writemask, COLORWRITEENABLE, fail ); |
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92 | EMIT_RS( svga, curr->rt[0].blend_enable, BLENDENABLE, fail ); |
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93 | |||
94 | if (curr->rt[0].blend_enable) { |
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95 | EMIT_RS( svga, curr->rt[0].srcblend, SRCBLEND, fail ); |
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96 | EMIT_RS( svga, curr->rt[0].dstblend, DSTBLEND, fail ); |
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97 | EMIT_RS( svga, curr->rt[0].blendeq, BLENDEQUATION, fail ); |
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98 | |||
99 | EMIT_RS( svga, curr->rt[0].separate_alpha_blend_enable, |
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100 | SEPARATEALPHABLENDENABLE, fail ); |
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101 | |||
102 | if (curr->rt[0].separate_alpha_blend_enable) { |
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103 | EMIT_RS( svga, curr->rt[0].srcblend_alpha, SRCBLENDALPHA, fail ); |
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104 | EMIT_RS( svga, curr->rt[0].dstblend_alpha, DSTBLENDALPHA, fail ); |
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105 | EMIT_RS( svga, curr->rt[0].blendeq_alpha, BLENDEQUATIONALPHA, fail ); |
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106 | } |
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107 | } |
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108 | } |
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109 | |||
110 | if (dirty & SVGA_NEW_BLEND_COLOR) { |
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111 | uint32 color; |
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112 | uint32 r = float_to_ubyte(svga->curr.blend_color.color[0]); |
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113 | uint32 g = float_to_ubyte(svga->curr.blend_color.color[1]); |
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114 | uint32 b = float_to_ubyte(svga->curr.blend_color.color[2]); |
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115 | uint32 a = float_to_ubyte(svga->curr.blend_color.color[3]); |
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116 | |||
117 | color = (a << 24) | (r << 16) | (g << 8) | b; |
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118 | |||
119 | EMIT_RS( svga, color, BLENDCOLOR, fail ); |
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120 | } |
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121 | |||
122 | if (dirty & (SVGA_NEW_DEPTH_STENCIL | SVGA_NEW_RAST)) { |
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123 | const struct svga_depth_stencil_state *curr = svga->curr.depth; |
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124 | const struct svga_rasterizer_state *rast = svga->curr.rast; |
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125 | |||
126 | if (!curr->stencil[0].enabled) |
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127 | { |
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128 | /* Stencil disabled |
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129 | */ |
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130 | EMIT_RS( svga, FALSE, STENCILENABLE, fail ); |
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131 | EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail ); |
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132 | } |
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133 | else if (curr->stencil[0].enabled && !curr->stencil[1].enabled) |
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134 | { |
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135 | /* Regular stencil |
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136 | */ |
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137 | EMIT_RS( svga, TRUE, STENCILENABLE, fail ); |
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138 | EMIT_RS( svga, FALSE, STENCILENABLE2SIDED, fail ); |
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139 | |||
140 | EMIT_RS( svga, curr->stencil[0].func, STENCILFUNC, fail ); |
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141 | EMIT_RS( svga, curr->stencil[0].fail, STENCILFAIL, fail ); |
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142 | EMIT_RS( svga, curr->stencil[0].zfail, STENCILZFAIL, fail ); |
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143 | EMIT_RS( svga, curr->stencil[0].pass, STENCILPASS, fail ); |
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144 | |||
145 | EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail ); |
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146 | EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail ); |
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147 | } |
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148 | else |
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149 | { |
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150 | int cw, ccw; |
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151 | |||
152 | /* Hardware frontwinding is always CW, so if ours is also CW, |
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153 | * then our definition of front face agrees with hardware. |
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154 | * Otherwise need to flip. |
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155 | */ |
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156 | if (rast->templ.front_ccw) { |
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157 | ccw = 0; |
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158 | cw = 1; |
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159 | } |
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160 | else { |
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161 | ccw = 1; |
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162 | cw = 0; |
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163 | } |
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164 | |||
165 | /* Twoside stencil |
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166 | */ |
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167 | EMIT_RS( svga, TRUE, STENCILENABLE, fail ); |
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168 | EMIT_RS( svga, TRUE, STENCILENABLE2SIDED, fail ); |
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169 | |||
170 | EMIT_RS( svga, curr->stencil[cw].func, STENCILFUNC, fail ); |
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171 | EMIT_RS( svga, curr->stencil[cw].fail, STENCILFAIL, fail ); |
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172 | EMIT_RS( svga, curr->stencil[cw].zfail, STENCILZFAIL, fail ); |
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173 | EMIT_RS( svga, curr->stencil[cw].pass, STENCILPASS, fail ); |
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174 | |||
175 | EMIT_RS( svga, curr->stencil[ccw].func, CCWSTENCILFUNC, fail ); |
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176 | EMIT_RS( svga, curr->stencil[ccw].fail, CCWSTENCILFAIL, fail ); |
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177 | EMIT_RS( svga, curr->stencil[ccw].zfail, CCWSTENCILZFAIL, fail ); |
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178 | EMIT_RS( svga, curr->stencil[ccw].pass, CCWSTENCILPASS, fail ); |
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179 | |||
180 | EMIT_RS( svga, curr->stencil_mask, STENCILMASK, fail ); |
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181 | EMIT_RS( svga, curr->stencil_writemask, STENCILWRITEMASK, fail ); |
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182 | } |
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183 | |||
184 | EMIT_RS( svga, curr->zenable, ZENABLE, fail ); |
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185 | if (curr->zenable) { |
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186 | EMIT_RS( svga, curr->zfunc, ZFUNC, fail ); |
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187 | EMIT_RS( svga, curr->zwriteenable, ZWRITEENABLE, fail ); |
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188 | } |
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189 | |||
190 | EMIT_RS( svga, curr->alphatestenable, ALPHATESTENABLE, fail ); |
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191 | if (curr->alphatestenable) { |
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192 | EMIT_RS( svga, curr->alphafunc, ALPHAFUNC, fail ); |
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193 | EMIT_RS_FLOAT( svga, curr->alpharef, ALPHAREF, fail ); |
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194 | } |
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195 | } |
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196 | |||
197 | if (dirty & SVGA_NEW_STENCIL_REF) { |
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198 | EMIT_RS( svga, svga->curr.stencil_ref.ref_value[0], STENCILREF, fail ); |
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199 | } |
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200 | |||
201 | if (dirty & (SVGA_NEW_RAST | SVGA_NEW_NEED_PIPELINE)) |
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202 | { |
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203 | const struct svga_rasterizer_state *curr = svga->curr.rast; |
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204 | unsigned cullmode = curr->cullmode; |
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205 | |||
206 | /* Shademode: still need to rearrange index list to move |
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207 | * flat-shading PV first vertex. |
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208 | */ |
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209 | EMIT_RS( svga, curr->shademode, SHADEMODE, fail ); |
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210 | |||
211 | /* Don't do culling while the software pipeline is active. It |
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212 | * does it for us, and additionally introduces potentially |
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213 | * back-facing triangles. |
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214 | */ |
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215 | if (svga->state.sw.need_pipeline) |
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216 | cullmode = SVGA3D_FACE_NONE; |
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217 | |||
218 | point_size_min = util_get_min_point_size(&curr->templ); |
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219 | |||
220 | EMIT_RS( svga, cullmode, CULLMODE, fail ); |
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221 | EMIT_RS( svga, curr->scissortestenable, SCISSORTESTENABLE, fail ); |
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222 | EMIT_RS( svga, curr->multisampleantialias, MULTISAMPLEANTIALIAS, fail ); |
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223 | EMIT_RS( svga, curr->lastpixel, LASTPIXEL, fail ); |
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224 | EMIT_RS( svga, curr->linepattern, LINEPATTERN, fail ); |
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225 | EMIT_RS_FLOAT( svga, curr->pointsize, POINTSIZE, fail ); |
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226 | EMIT_RS_FLOAT( svga, point_size_min, POINTSIZEMIN, fail ); |
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227 | EMIT_RS_FLOAT( svga, screen->maxPointSize, POINTSIZEMAX, fail ); |
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228 | EMIT_RS( svga, curr->pointsprite, POINTSPRITEENABLE, fail); |
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229 | } |
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230 | |||
231 | if (dirty & (SVGA_NEW_RAST | SVGA_NEW_FRAME_BUFFER | SVGA_NEW_NEED_PIPELINE)) |
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232 | { |
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233 | const struct svga_rasterizer_state *curr = svga->curr.rast; |
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234 | float slope = 0.0; |
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235 | float bias = 0.0; |
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236 | |||
237 | /* Need to modify depth bias according to bound depthbuffer |
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238 | * format. Don't do hardware depthbias while the software |
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239 | * pipeline is active. |
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240 | */ |
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241 | if (!svga->state.sw.need_pipeline && |
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242 | svga->curr.framebuffer.zsbuf) |
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243 | { |
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244 | slope = curr->slopescaledepthbias; |
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245 | bias = svga->curr.depthscale * curr->depthbias; |
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246 | } |
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247 | |||
248 | EMIT_RS_FLOAT( svga, slope, SLOPESCALEDEPTHBIAS, fail ); |
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249 | EMIT_RS_FLOAT( svga, bias, DEPTHBIAS, fail ); |
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250 | } |
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251 | |||
252 | if (dirty & SVGA_NEW_FRAME_BUFFER) { |
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253 | /* XXX: we only look at the first color buffer's sRGB state */ |
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254 | float gamma = 1.0f; |
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255 | if (svga->curr.framebuffer.cbufs[0] && |
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256 | util_format_is_srgb(svga->curr.framebuffer.cbufs[0]->format)) { |
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257 | gamma = 2.2f; |
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258 | } |
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259 | EMIT_RS_FLOAT(svga, gamma, OUTPUTGAMMA, fail); |
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260 | } |
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261 | |||
262 | if (dirty & SVGA_NEW_RAST) { |
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263 | /* bitmask of the enabled clip planes */ |
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264 | unsigned enabled = svga->curr.rast->templ.clip_plane_enable; |
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265 | EMIT_RS( svga, enabled, CLIPPLANEENABLE, fail ); |
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266 | } |
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267 | |||
268 | if (queue.rs_count) { |
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269 | SVGA3dRenderState *rs; |
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270 | |||
271 | if (SVGA3D_BeginSetRenderState( svga->swc, |
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272 | &rs, |
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273 | queue.rs_count ) != PIPE_OK) |
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274 | goto fail; |
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275 | |||
276 | memcpy( rs, |
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277 | queue.rs, |
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278 | queue.rs_count * sizeof queue.rs[0]); |
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279 | |||
280 | SVGA_FIFOCommitAll( svga->swc ); |
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281 | } |
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282 | |||
283 | return PIPE_OK; |
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284 | |||
285 | fail: |
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286 | /* XXX: need to poison cached hardware state on failure to ensure |
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287 | * dirty state gets re-emitted. Fix this by re-instating partial |
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288 | * FIFOCommit command and only updating cached hw state once the |
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289 | * initial allocation has succeeded. |
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290 | */ |
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291 | memset(svga->state.hw_draw.rs, 0xcd, sizeof(svga->state.hw_draw.rs)); |
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292 | |||
293 | return PIPE_ERROR_OUT_OF_MEMORY; |
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294 | } |
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295 | |||
296 | |||
297 | struct svga_tracked_state svga_hw_rss = |
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298 | { |
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299 | "hw rss state", |
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300 | |||
301 | (SVGA_NEW_BLEND | |
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302 | SVGA_NEW_BLEND_COLOR | |
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303 | SVGA_NEW_DEPTH_STENCIL | |
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304 | SVGA_NEW_STENCIL_REF | |
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305 | SVGA_NEW_RAST | |
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306 | SVGA_NEW_FRAME_BUFFER | |
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307 | SVGA_NEW_NEED_PIPELINE), |
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308 | |||
309 | emit_rss |
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310 | };><>><>><>>> |