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5563 | serge | 1 | /************************************************************************** |
2 | * |
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3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | |||
28 | #define CMD_MI (0x0 << 29) |
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29 | #define CMD_2D (0x2 << 29) |
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30 | #define CMD_3D (0x3 << 29) |
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31 | |||
32 | #define MI_NOOP (CMD_MI | 0) |
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33 | |||
34 | #define MI_BATCH_BUFFER_END (CMD_MI | 0xA << 23) |
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35 | |||
36 | #define MI_FLUSH (CMD_MI | (4 << 23)) |
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37 | #define FLUSH_MAP_CACHE (1 << 0) |
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38 | #define INHIBIT_FLUSH_RENDER_CACHE (1 << 2) |
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39 | |||
40 | #define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23)) |
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41 | |||
42 | #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2) |
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43 | |||
44 | #define MI_STORE_REGISTER_MEM (CMD_MI | (0x24 << 23)) |
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45 | # define MI_STORE_REGISTER_MEM_USE_GGTT (1 << 22) |
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46 | |||
47 | /** @{ |
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48 | * |
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49 | * PIPE_CONTROL operation, a combination MI_FLUSH and register write with |
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50 | * additional flushing control. |
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51 | */ |
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52 | #define _3DSTATE_PIPE_CONTROL (CMD_3D | (3 << 27) | (2 << 24)) |
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53 | #define PIPE_CONTROL_CS_STALL (1 << 20) |
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54 | #define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (1 << 19) |
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55 | #define PIPE_CONTROL_TLB_INVALIDATE (1 << 18) |
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56 | #define PIPE_CONTROL_SYNC_GFDT (1 << 17) |
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57 | #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1 << 16) |
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58 | #define PIPE_CONTROL_NO_WRITE (0 << 14) |
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59 | #define PIPE_CONTROL_WRITE_IMMEDIATE (1 << 14) |
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60 | #define PIPE_CONTROL_WRITE_DEPTH_COUNT (2 << 14) |
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61 | #define PIPE_CONTROL_WRITE_TIMESTAMP (3 << 14) |
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62 | #define PIPE_CONTROL_DEPTH_STALL (1 << 13) |
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63 | #define PIPE_CONTROL_WRITE_FLUSH (1 << 12) |
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64 | #define PIPE_CONTROL_INSTRUCTION_FLUSH (1 << 11) |
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65 | #define PIPE_CONTROL_TC_FLUSH (1 << 10) /* GM45+ only */ |
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66 | #define PIPE_CONTROL_ISP_DIS (1 << 9) |
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67 | #define PIPE_CONTROL_INTERRUPT_ENABLE (1 << 8) |
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68 | /* GT */ |
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69 | #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1 << 4) |
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70 | #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1 << 3) |
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71 | #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1 << 2) |
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72 | #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1) |
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73 | #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) |
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74 | #define PIPE_CONTROL_PPGTT_WRITE (0 << 2) |
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75 | #define PIPE_CONTROL_GLOBAL_GTT_WRITE (1 << 2) |
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76 | |||
77 | /** @} */ |
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78 | |||
79 | #define XY_SETUP_BLT_CMD (CMD_2D | (0x01 << 22)) |
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80 | |||
81 | #define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22)) |
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82 | |||
83 | #define XY_SRC_COPY_BLT_CMD (CMD_2D | (0x53 << 22)) |
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84 | |||
85 | #define XY_TEXT_IMMEDIATE_BLIT_CMD (CMD_2D | (0x31 << 22)) |
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86 | # define XY_TEXT_BYTE_PACKED (1 << 16) |
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87 | |||
88 | /* BR00 */ |
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89 | #define XY_BLT_WRITE_ALPHA (1 << 21) |
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90 | #define XY_BLT_WRITE_RGB (1 << 20) |
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91 | #define XY_SRC_TILED (1 << 15) |
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92 | #define XY_DST_TILED (1 << 11) |
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93 | |||
94 | /* BR13 */ |
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95 | #define BR13_8 (0x0 << 24) |
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96 | #define BR13_565 (0x1 << 24) |
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97 | #define BR13_8888 (0x3 << 24) |
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98 | |||
99 | /* Pipeline Statistics Counter Registers */ |
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100 | #define IA_VERTICES_COUNT 0x2310 |
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101 | #define IA_PRIMITIVES_COUNT 0x2318 |
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102 | #define VS_INVOCATION_COUNT 0x2320 |
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103 | #define HS_INVOCATION_COUNT 0x2300 |
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104 | #define DS_INVOCATION_COUNT 0x2308 |
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105 | #define GS_INVOCATION_COUNT 0x2328 |
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106 | #define GS_PRIMITIVES_COUNT 0x2330 |
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107 | #define CL_INVOCATION_COUNT 0x2338 |
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108 | #define CL_PRIMITIVES_COUNT 0x2340 |
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109 | #define PS_INVOCATION_COUNT 0x2348 |
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110 | #define PS_DEPTH_COUNT 0x2350 |
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111 | |||
112 | #define SO_NUM_PRIM_STORAGE_NEEDED 0x2280 |
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113 | #define SO_PRIM_STORAGE_NEEDED0_IVB 0x5240 |
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114 | #define SO_PRIM_STORAGE_NEEDED1_IVB 0x5248 |
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115 | #define SO_PRIM_STORAGE_NEEDED2_IVB 0x5250 |
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116 | #define SO_PRIM_STORAGE_NEEDED3_IVB 0x5258 |
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117 | |||
118 | #define SO_NUM_PRIMS_WRITTEN 0x2288 |
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119 | #define SO_NUM_PRIMS_WRITTEN0_IVB 0x5200 |
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120 | #define SO_NUM_PRIMS_WRITTEN1_IVB 0x5208 |
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121 | #define SO_NUM_PRIMS_WRITTEN2_IVB 0x5210 |
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122 | #define SO_NUM_PRIMS_WRITTEN3_IVB 0x5218 |
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123 | |||
124 | #define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4) |
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125 | |||
126 | #define TIMESTAMP 0x2358 |
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127 | |||
128 | #define BCS_SWCTRL 0x22200 |
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129 | # define BCS_SWCTRL_SRC_Y (1 << 0) |
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130 | # define BCS_SWCTRL_DST_Y (1 << 1)><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |