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/*

 Copyright (C) Intel Corp.  2006.  All Rights Reserved.

 Intel funded Tungsten Graphics to

 develop this 3D driver.

 Permission is hereby granted, free of charge, to any person obtaining

 a copy of this software and associated documentation files (the

 "Software"), to deal in the Software without restriction, including

 without limitation the rights to use, copy, modify, merge, publish,

 distribute, sublicense, and/or sell copies of the Software, and to

 permit persons to whom the Software is furnished to do so, subject to

 the following conditions:

 The above copyright notice and this permission notice (including the

 next paragraph) shall be included in all copies or substantial

 portions of the Software.

 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,

 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE

 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION

 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION

 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 **********************************************************************/

 /*

  * Authors:

  *   Keith Whitwell 

  */

#define INTEL_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))

/* Using the GNU statement expression extension */

#define SET_FIELD(value, field)                                         \

   ({                                                                   \

      uint32_t fieldval = (value) << field ## _SHIFT;                   \

      assert((fieldval & ~ field ## _MASK) == 0);                       \

      fieldval & field ## _MASK;                                        \

   })

#define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))

#define GET_FIELD(word, field) (((word)  & field ## _MASK) >> field ## _SHIFT)

#ifndef BRW_DEFINES_H

#define BRW_DEFINES_H

/* 3D state:

 */

#define CMD_3D_PRIM                                 0x7b00 /* 3DPRIMITIVE */

/* DW0 */

# define GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT            10

# define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 15)

# define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM     (1 << 15)

# define GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE      (1 << 10)

# define GEN7_3DPRIM_PREDICATE_ENABLE               (1 << 8)

/* DW1 */

# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8)

# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM     (1 << 8)

#define _3DPRIM_POINTLIST         0x01

#define _3DPRIM_LINELIST          0x02

#define _3DPRIM_LINESTRIP         0x03

#define _3DPRIM_TRILIST           0x04

#define _3DPRIM_TRISTRIP          0x05

#define _3DPRIM_TRIFAN            0x06

#define _3DPRIM_QUADLIST          0x07

#define _3DPRIM_QUADSTRIP         0x08

#define _3DPRIM_LINELIST_ADJ      0x09

#define _3DPRIM_LINESTRIP_ADJ     0x0A

#define _3DPRIM_TRILIST_ADJ       0x0B

#define _3DPRIM_TRISTRIP_ADJ      0x0C

#define _3DPRIM_TRISTRIP_REVERSE  0x0D

#define _3DPRIM_POLYGON           0x0E

#define _3DPRIM_RECTLIST          0x0F

#define _3DPRIM_LINELOOP          0x10

#define _3DPRIM_POINTLIST_BF      0x11

#define _3DPRIM_LINESTRIP_CONT    0x12

#define _3DPRIM_LINESTRIP_BF      0x13

#define _3DPRIM_LINESTRIP_CONT_BF 0x14

#define _3DPRIM_TRIFAN_NOSTIPPLE  0x15

/* We use this offset to be able to pass native primitive types in struct

 * _mesa_prim::mode.  Native primitive types are BRW_PRIM_OFFSET +

 * native_type, which should be different from all GL types and still fit in

 * the 8 bits avialable. */

#define BRW_PRIM_OFFSET           0x80

#define BRW_ANISORATIO_2     0

#define BRW_ANISORATIO_4     1

#define BRW_ANISORATIO_6     2

#define BRW_ANISORATIO_8     3

#define BRW_ANISORATIO_10    4

#define BRW_ANISORATIO_12    5

#define BRW_ANISORATIO_14    6

#define BRW_ANISORATIO_16    7

#define BRW_BLENDFACTOR_ONE                 0x1

#define BRW_BLENDFACTOR_SRC_COLOR           0x2

#define BRW_BLENDFACTOR_SRC_ALPHA           0x3

#define BRW_BLENDFACTOR_DST_ALPHA           0x4

#define BRW_BLENDFACTOR_DST_COLOR           0x5

#define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE  0x6

#define BRW_BLENDFACTOR_CONST_COLOR         0x7

#define BRW_BLENDFACTOR_CONST_ALPHA         0x8

#define BRW_BLENDFACTOR_SRC1_COLOR          0x9

#define BRW_BLENDFACTOR_SRC1_ALPHA          0x0A

#define BRW_BLENDFACTOR_ZERO                0x11

#define BRW_BLENDFACTOR_INV_SRC_COLOR       0x12

#define BRW_BLENDFACTOR_INV_SRC_ALPHA       0x13

#define BRW_BLENDFACTOR_INV_DST_ALPHA       0x14

#define BRW_BLENDFACTOR_INV_DST_COLOR       0x15

#define BRW_BLENDFACTOR_INV_CONST_COLOR     0x17

#define BRW_BLENDFACTOR_INV_CONST_ALPHA     0x18

#define BRW_BLENDFACTOR_INV_SRC1_COLOR      0x19

#define BRW_BLENDFACTOR_INV_SRC1_ALPHA      0x1A

#define BRW_BLENDFUNCTION_ADD               0

#define BRW_BLENDFUNCTION_SUBTRACT          1

#define BRW_BLENDFUNCTION_REVERSE_SUBTRACT  2

#define BRW_BLENDFUNCTION_MIN               3

#define BRW_BLENDFUNCTION_MAX               4

#define BRW_ALPHATEST_FORMAT_UNORM8         0

#define BRW_ALPHATEST_FORMAT_FLOAT32        1

#define BRW_CHROMAKEY_KILL_ON_ANY_MATCH  0

#define BRW_CHROMAKEY_REPLACE_BLACK      1

#define BRW_CLIP_API_OGL     0

#define BRW_CLIP_API_DX      1

#define BRW_CLIPMODE_NORMAL              0

#define BRW_CLIPMODE_CLIP_ALL            1

#define BRW_CLIPMODE_CLIP_NON_REJECTED   2

#define BRW_CLIPMODE_REJECT_ALL          3

#define BRW_CLIPMODE_ACCEPT_ALL          4

#define BRW_CLIPMODE_KERNEL_CLIP         5

#define BRW_CLIP_NDCSPACE     0

#define BRW_CLIP_SCREENSPACE  1

#define BRW_COMPAREFUNCTION_ALWAYS       0

#define BRW_COMPAREFUNCTION_NEVER        1

#define BRW_COMPAREFUNCTION_LESS         2

#define BRW_COMPAREFUNCTION_EQUAL        3

#define BRW_COMPAREFUNCTION_LEQUAL       4

#define BRW_COMPAREFUNCTION_GREATER      5

#define BRW_COMPAREFUNCTION_NOTEQUAL     6

#define BRW_COMPAREFUNCTION_GEQUAL       7

#define BRW_COVERAGE_PIXELS_HALF     0

#define BRW_COVERAGE_PIXELS_1        1

#define BRW_COVERAGE_PIXELS_2        2

#define BRW_COVERAGE_PIXELS_4        3

#define BRW_CULLMODE_BOTH        0

#define BRW_CULLMODE_NONE        1

#define BRW_CULLMODE_FRONT       2

#define BRW_CULLMODE_BACK        3

#define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM      0

#define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT  1

#define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT     0

#define BRW_DEPTHFORMAT_D32_FLOAT                1

#define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT        2

#define BRW_DEPTHFORMAT_D24_UNORM_X8_UINT        3 /* GEN5 */

#define BRW_DEPTHFORMAT_D16_UNORM                5

#define BRW_FLOATING_POINT_IEEE_754        0

#define BRW_FLOATING_POINT_NON_IEEE_754    1

#define BRW_FRONTWINDING_CW      0

#define BRW_FRONTWINDING_CCW     1

#define BRW_SPRITE_POINT_ENABLE  16

#define BRW_CUT_INDEX_ENABLE     (1 << 10)

#define BRW_INDEX_BYTE     0

#define BRW_INDEX_WORD     1

#define BRW_INDEX_DWORD    2

#define BRW_LOGICOPFUNCTION_CLEAR            0

#define BRW_LOGICOPFUNCTION_NOR              1

#define BRW_LOGICOPFUNCTION_AND_INVERTED     2

#define BRW_LOGICOPFUNCTION_COPY_INVERTED    3

#define BRW_LOGICOPFUNCTION_AND_REVERSE      4

#define BRW_LOGICOPFUNCTION_INVERT           5

#define BRW_LOGICOPFUNCTION_XOR              6

#define BRW_LOGICOPFUNCTION_NAND             7

#define BRW_LOGICOPFUNCTION_AND              8

#define BRW_LOGICOPFUNCTION_EQUIV            9

#define BRW_LOGICOPFUNCTION_NOOP             10

#define BRW_LOGICOPFUNCTION_OR_INVERTED      11

#define BRW_LOGICOPFUNCTION_COPY             12

#define BRW_LOGICOPFUNCTION_OR_REVERSE       13

#define BRW_LOGICOPFUNCTION_OR               14

#define BRW_LOGICOPFUNCTION_SET              15

#define BRW_MAPFILTER_NEAREST        0x0

#define BRW_MAPFILTER_LINEAR         0x1

#define BRW_MAPFILTER_ANISOTROPIC    0x2

#define BRW_MIPFILTER_NONE        0

#define BRW_MIPFILTER_NEAREST     1

#define BRW_MIPFILTER_LINEAR      3

#define BRW_ADDRESS_ROUNDING_ENABLE_U_MAG	0x20

#define BRW_ADDRESS_ROUNDING_ENABLE_U_MIN	0x10

#define BRW_ADDRESS_ROUNDING_ENABLE_V_MAG	0x08

#define BRW_ADDRESS_ROUNDING_ENABLE_V_MIN	0x04

#define BRW_ADDRESS_ROUNDING_ENABLE_R_MAG	0x02

#define BRW_ADDRESS_ROUNDING_ENABLE_R_MIN	0x01

#define BRW_POLYGON_FRONT_FACING     0

#define BRW_POLYGON_BACK_FACING      1

#define BRW_PREFILTER_ALWAYS     0x0

#define BRW_PREFILTER_NEVER      0x1

#define BRW_PREFILTER_LESS       0x2

#define BRW_PREFILTER_EQUAL      0x3

#define BRW_PREFILTER_LEQUAL     0x4

#define BRW_PREFILTER_GREATER    0x5

#define BRW_PREFILTER_NOTEQUAL   0x6

#define BRW_PREFILTER_GEQUAL     0x7

#define BRW_PROVOKING_VERTEX_0    0

#define BRW_PROVOKING_VERTEX_1    1

#define BRW_PROVOKING_VERTEX_2    2

#define BRW_RASTRULE_UPPER_LEFT  0

#define BRW_RASTRULE_UPPER_RIGHT 1

/* These are listed as "Reserved, but not seen as useful"

 * in Intel documentation (page 212, "Point Rasterization Rule",

 * section 7.4 "SF Pipeline State Summary", of document

 * "Intel® 965 Express Chipset Family and Intel® G35 Express

 * Chipset Graphics Controller Programmer's Reference Manual,

 * Volume 2: 3D/Media", Revision 1.0b as of January 2008,

 * available at

 *     http://intellinuxgraphics.org/documentation.html

 * at the time of this writing).

 *

 * These appear to be supported on at least some

 * i965-family devices, and the BRW_RASTRULE_LOWER_RIGHT

 * is useful when using OpenGL to render to a FBO

 * (which has the pixel coordinate Y orientation inverted

 * with respect to the normal OpenGL pixel coordinate system).

 */

#define BRW_RASTRULE_LOWER_LEFT  2

#define BRW_RASTRULE_LOWER_RIGHT 3

#define BRW_RENDERTARGET_CLAMPRANGE_UNORM    0

#define BRW_RENDERTARGET_CLAMPRANGE_SNORM    1

#define BRW_RENDERTARGET_CLAMPRANGE_FORMAT   2

#define BRW_STENCILOP_KEEP               0

#define BRW_STENCILOP_ZERO               1

#define BRW_STENCILOP_REPLACE            2

#define BRW_STENCILOP_INCRSAT            3

#define BRW_STENCILOP_DECRSAT            4

#define BRW_STENCILOP_INCR               5

#define BRW_STENCILOP_DECR               6

#define BRW_STENCILOP_INVERT             7

/* Surface state DW0 */

#define GEN8_SURFACE_IS_ARRAY                       (1 << 28)

#define GEN8_SURFACE_VALIGN_4                       (1 << 16)

#define GEN8_SURFACE_VALIGN_8                       (2 << 16)

#define GEN8_SURFACE_VALIGN_16                      (3 << 16)

#define GEN8_SURFACE_HALIGN_4                       (1 << 14)

#define GEN8_SURFACE_HALIGN_8                       (2 << 14)

#define GEN8_SURFACE_HALIGN_16                      (3 << 14)

#define GEN8_SURFACE_TILING_NONE                    (0 << 12)

#define GEN8_SURFACE_TILING_W                       (1 << 12)

#define GEN8_SURFACE_TILING_X                       (2 << 12)

#define GEN8_SURFACE_TILING_Y                       (3 << 12)

#define BRW_SURFACE_RC_READ_WRITE	(1 << 8)

#define BRW_SURFACE_MIPLAYOUT_SHIFT	10

#define BRW_SURFACE_MIPMAPLAYOUT_BELOW   0

#define BRW_SURFACE_MIPMAPLAYOUT_RIGHT   1

#define BRW_SURFACE_CUBEFACE_ENABLES	0x3f

#define BRW_SURFACE_BLEND_ENABLED	(1 << 13)

#define BRW_SURFACE_WRITEDISABLE_B_SHIFT	14

#define BRW_SURFACE_WRITEDISABLE_G_SHIFT	15

#define BRW_SURFACE_WRITEDISABLE_R_SHIFT	16

#define BRW_SURFACE_WRITEDISABLE_A_SHIFT	17

#define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT             0x000

#define BRW_SURFACEFORMAT_R32G32B32A32_SINT              0x001

#define BRW_SURFACEFORMAT_R32G32B32A32_UINT              0x002

#define BRW_SURFACEFORMAT_R32G32B32A32_UNORM             0x003

#define BRW_SURFACEFORMAT_R32G32B32A32_SNORM             0x004

#define BRW_SURFACEFORMAT_R64G64_FLOAT                   0x005

#define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT             0x006

#define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED           0x007

#define BRW_SURFACEFORMAT_R32G32B32A32_USCALED           0x008

#define BRW_SURFACEFORMAT_R32G32B32A32_SFIXED            0x020

#define BRW_SURFACEFORMAT_R64G64_PASSTHRU                0x021

#define BRW_SURFACEFORMAT_R32G32B32_FLOAT                0x040

#define BRW_SURFACEFORMAT_R32G32B32_SINT                 0x041

#define BRW_SURFACEFORMAT_R32G32B32_UINT                 0x042

#define BRW_SURFACEFORMAT_R32G32B32_UNORM                0x043

#define BRW_SURFACEFORMAT_R32G32B32_SNORM                0x044

#define BRW_SURFACEFORMAT_R32G32B32_SSCALED              0x045

#define BRW_SURFACEFORMAT_R32G32B32_USCALED              0x046

#define BRW_SURFACEFORMAT_R32G32B32_SFIXED               0x050

#define BRW_SURFACEFORMAT_R16G16B16A16_UNORM             0x080

#define BRW_SURFACEFORMAT_R16G16B16A16_SNORM             0x081

#define BRW_SURFACEFORMAT_R16G16B16A16_SINT              0x082

#define BRW_SURFACEFORMAT_R16G16B16A16_UINT              0x083

#define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT             0x084

#define BRW_SURFACEFORMAT_R32G32_FLOAT                   0x085

#define BRW_SURFACEFORMAT_R32G32_SINT                    0x086

#define BRW_SURFACEFORMAT_R32G32_UINT                    0x087

#define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS       0x088

#define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT        0x089

#define BRW_SURFACEFORMAT_L32A32_FLOAT                   0x08A

#define BRW_SURFACEFORMAT_R32G32_UNORM                   0x08B

#define BRW_SURFACEFORMAT_R32G32_SNORM                   0x08C

#define BRW_SURFACEFORMAT_R64_FLOAT                      0x08D

#define BRW_SURFACEFORMAT_R16G16B16X16_UNORM             0x08E

#define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT             0x08F

#define BRW_SURFACEFORMAT_A32X32_FLOAT                   0x090

#define BRW_SURFACEFORMAT_L32X32_FLOAT                   0x091

#define BRW_SURFACEFORMAT_I32X32_FLOAT                   0x092

#define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED           0x093

#define BRW_SURFACEFORMAT_R16G16B16A16_USCALED           0x094

#define BRW_SURFACEFORMAT_R32G32_SSCALED                 0x095

#define BRW_SURFACEFORMAT_R32G32_USCALED                 0x096

#define BRW_SURFACEFORMAT_R32G32_FLOAT_LD                0x097

#define BRW_SURFACEFORMAT_R32G32_SFIXED                  0x0A0

#define BRW_SURFACEFORMAT_R64_PASSTHRU                   0x0A1

#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM                 0x0C0

#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB            0x0C1

#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM              0x0C2

#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB         0x0C3

#define BRW_SURFACEFORMAT_R10G10B10A2_UINT               0x0C4

#define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM       0x0C5

#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM                 0x0C7

#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB            0x0C8

#define BRW_SURFACEFORMAT_R8G8B8A8_SNORM                 0x0C9

#define BRW_SURFACEFORMAT_R8G8B8A8_SINT                  0x0CA

#define BRW_SURFACEFORMAT_R8G8B8A8_UINT                  0x0CB

#define BRW_SURFACEFORMAT_R16G16_UNORM                   0x0CC

#define BRW_SURFACEFORMAT_R16G16_SNORM                   0x0CD

#define BRW_SURFACEFORMAT_R16G16_SINT                    0x0CE

#define BRW_SURFACEFORMAT_R16G16_UINT                    0x0CF

#define BRW_SURFACEFORMAT_R16G16_FLOAT                   0x0D0

#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM              0x0D1

#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB         0x0D2

#define BRW_SURFACEFORMAT_R11G11B10_FLOAT                0x0D3

#define BRW_SURFACEFORMAT_R32_SINT                       0x0D6

#define BRW_SURFACEFORMAT_R32_UINT                       0x0D7

#define BRW_SURFACEFORMAT_R32_FLOAT                      0x0D8

#define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS          0x0D9

#define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT           0x0DA

#define BRW_SURFACEFORMAT_L16A16_UNORM                   0x0DF

#define BRW_SURFACEFORMAT_I24X8_UNORM                    0x0E0

#define BRW_SURFACEFORMAT_L24X8_UNORM                    0x0E1

#define BRW_SURFACEFORMAT_A24X8_UNORM                    0x0E2

#define BRW_SURFACEFORMAT_I32_FLOAT                      0x0E3

#define BRW_SURFACEFORMAT_L32_FLOAT                      0x0E4

#define BRW_SURFACEFORMAT_A32_FLOAT                      0x0E5

#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM                 0x0E9

#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB            0x0EA

#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM                 0x0EB

#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB            0x0EC

#define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP             0x0ED

#define BRW_SURFACEFORMAT_B10G10R10X2_UNORM              0x0EE

#define BRW_SURFACEFORMAT_L16A16_FLOAT                   0x0F0

#define BRW_SURFACEFORMAT_R32_UNORM                      0x0F1

#define BRW_SURFACEFORMAT_R32_SNORM                      0x0F2

#define BRW_SURFACEFORMAT_R10G10B10X2_USCALED            0x0F3

#define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED               0x0F4

#define BRW_SURFACEFORMAT_R8G8B8A8_USCALED               0x0F5

#define BRW_SURFACEFORMAT_R16G16_SSCALED                 0x0F6

#define BRW_SURFACEFORMAT_R16G16_USCALED                 0x0F7

#define BRW_SURFACEFORMAT_R32_SSCALED                    0x0F8

#define BRW_SURFACEFORMAT_R32_USCALED                    0x0F9

#define BRW_SURFACEFORMAT_B5G6R5_UNORM                   0x100

#define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB              0x101

#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM                 0x102

#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB            0x103

#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM                 0x104

#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB            0x105

#define BRW_SURFACEFORMAT_R8G8_UNORM                     0x106

#define BRW_SURFACEFORMAT_R8G8_SNORM                     0x107

#define BRW_SURFACEFORMAT_R8G8_SINT                      0x108

#define BRW_SURFACEFORMAT_R8G8_UINT                      0x109

#define BRW_SURFACEFORMAT_R16_UNORM                      0x10A

#define BRW_SURFACEFORMAT_R16_SNORM                      0x10B

#define BRW_SURFACEFORMAT_R16_SINT                       0x10C

#define BRW_SURFACEFORMAT_R16_UINT                       0x10D

#define BRW_SURFACEFORMAT_R16_FLOAT                      0x10E

#define BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE0            0x10F

#define BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE1            0x110

#define BRW_SURFACEFORMAT_I16_UNORM                      0x111

#define BRW_SURFACEFORMAT_L16_UNORM                      0x112

#define BRW_SURFACEFORMAT_A16_UNORM                      0x113

#define BRW_SURFACEFORMAT_L8A8_UNORM                     0x114

#define BRW_SURFACEFORMAT_I16_FLOAT                      0x115

#define BRW_SURFACEFORMAT_L16_FLOAT                      0x116

#define BRW_SURFACEFORMAT_A16_FLOAT                      0x117

#define BRW_SURFACEFORMAT_L8A8_UNORM_SRGB                0x118

#define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM            0x119

#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM                 0x11A

#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB            0x11B

#define BRW_SURFACEFORMAT_R8G8_SSCALED                   0x11C

#define BRW_SURFACEFORMAT_R8G8_USCALED                   0x11D

#define BRW_SURFACEFORMAT_R16_SSCALED                    0x11E

#define BRW_SURFACEFORMAT_R16_USCALED                    0x11F

#define BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE0            0x122

#define BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE1            0x123

#define BRW_SURFACEFORMAT_A1B5G5R5_UNORM                 0x124

#define BRW_SURFACEFORMAT_A4B4G4R4_UNORM                 0x125

#define BRW_SURFACEFORMAT_L8A8_UINT                      0x126

#define BRW_SURFACEFORMAT_L8A8_SINT                      0x127

#define BRW_SURFACEFORMAT_R8_UNORM                       0x140

#define BRW_SURFACEFORMAT_R8_SNORM                       0x141

#define BRW_SURFACEFORMAT_R8_SINT                        0x142

#define BRW_SURFACEFORMAT_R8_UINT                        0x143

#define BRW_SURFACEFORMAT_A8_UNORM                       0x144

#define BRW_SURFACEFORMAT_I8_UNORM                       0x145

#define BRW_SURFACEFORMAT_L8_UNORM                       0x146

#define BRW_SURFACEFORMAT_P4A4_UNORM                     0x147

#define BRW_SURFACEFORMAT_A4P4_UNORM                     0x148

#define BRW_SURFACEFORMAT_R8_SSCALED                     0x149

#define BRW_SURFACEFORMAT_R8_USCALED                     0x14A

#define BRW_SURFACEFORMAT_P8_UNORM_PALETTE0              0x14B

#define BRW_SURFACEFORMAT_L8_UNORM_SRGB                  0x14C

#define BRW_SURFACEFORMAT_P8_UNORM_PALETTE1              0x14D

#define BRW_SURFACEFORMAT_P4A4_UNORM_PALETTE1            0x14E

#define BRW_SURFACEFORMAT_A4P4_UNORM_PALETTE1            0x14F

#define BRW_SURFACEFORMAT_Y8_SNORM                       0x150

#define BRW_SURFACEFORMAT_L8_UINT                        0x152

#define BRW_SURFACEFORMAT_L8_SINT                        0x153

#define BRW_SURFACEFORMAT_I8_UINT                        0x154

#define BRW_SURFACEFORMAT_I8_SINT                        0x155

#define BRW_SURFACEFORMAT_DXT1_RGB_SRGB                  0x180

#define BRW_SURFACEFORMAT_R1_UINT                        0x181

#define BRW_SURFACEFORMAT_YCRCB_NORMAL                   0x182

#define BRW_SURFACEFORMAT_YCRCB_SWAPUVY                  0x183

#define BRW_SURFACEFORMAT_P2_UNORM_PALETTE0              0x184

#define BRW_SURFACEFORMAT_P2_UNORM_PALETTE1              0x185

#define BRW_SURFACEFORMAT_BC1_UNORM                      0x186

#define BRW_SURFACEFORMAT_BC2_UNORM                      0x187

#define BRW_SURFACEFORMAT_BC3_UNORM                      0x188

#define BRW_SURFACEFORMAT_BC4_UNORM                      0x189

#define BRW_SURFACEFORMAT_BC5_UNORM                      0x18A

#define BRW_SURFACEFORMAT_BC1_UNORM_SRGB                 0x18B

#define BRW_SURFACEFORMAT_BC2_UNORM_SRGB                 0x18C

#define BRW_SURFACEFORMAT_BC3_UNORM_SRGB                 0x18D

#define BRW_SURFACEFORMAT_MONO8                          0x18E

#define BRW_SURFACEFORMAT_YCRCB_SWAPUV                   0x18F

#define BRW_SURFACEFORMAT_YCRCB_SWAPY                    0x190

#define BRW_SURFACEFORMAT_DXT1_RGB                       0x191

#define BRW_SURFACEFORMAT_FXT1                           0x192

#define BRW_SURFACEFORMAT_R8G8B8_UNORM                   0x193

#define BRW_SURFACEFORMAT_R8G8B8_SNORM                   0x194

#define BRW_SURFACEFORMAT_R8G8B8_SSCALED                 0x195

#define BRW_SURFACEFORMAT_R8G8B8_USCALED                 0x196

#define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT             0x197

#define BRW_SURFACEFORMAT_R64G64B64_FLOAT                0x198

#define BRW_SURFACEFORMAT_BC4_SNORM                      0x199

#define BRW_SURFACEFORMAT_BC5_SNORM                      0x19A

#define BRW_SURFACEFORMAT_R16G16B16_FLOAT                0x19B

#define BRW_SURFACEFORMAT_R16G16B16_UNORM                0x19C

#define BRW_SURFACEFORMAT_R16G16B16_SNORM                0x19D

#define BRW_SURFACEFORMAT_R16G16B16_SSCALED              0x19E

#define BRW_SURFACEFORMAT_R16G16B16_USCALED              0x19F

#define BRW_SURFACEFORMAT_BC6H_SF16                      0x1A1

#define BRW_SURFACEFORMAT_BC7_UNORM                      0x1A2

#define BRW_SURFACEFORMAT_BC7_UNORM_SRGB                 0x1A3

#define BRW_SURFACEFORMAT_BC6H_UF16                      0x1A4

#define BRW_SURFACEFORMAT_PLANAR_420_8                   0x1A5

#define BRW_SURFACEFORMAT_R8G8B8_UNORM_SRGB              0x1A8

#define BRW_SURFACEFORMAT_ETC1_RGB8                      0x1A9

#define BRW_SURFACEFORMAT_ETC2_RGB8                      0x1AA

#define BRW_SURFACEFORMAT_EAC_R11                        0x1AB

#define BRW_SURFACEFORMAT_EAC_RG11                       0x1AC

#define BRW_SURFACEFORMAT_EAC_SIGNED_R11                 0x1AD

#define BRW_SURFACEFORMAT_EAC_SIGNED_RG11                0x1AE

#define BRW_SURFACEFORMAT_ETC2_SRGB8                     0x1AF

#define BRW_SURFACEFORMAT_R16G16B16_UINT                 0x1B0

#define BRW_SURFACEFORMAT_R16G16B16_SINT                 0x1B1

#define BRW_SURFACEFORMAT_R32_SFIXED                     0x1B2

#define BRW_SURFACEFORMAT_R10G10B10A2_SNORM              0x1B3

#define BRW_SURFACEFORMAT_R10G10B10A2_USCALED            0x1B4

#define BRW_SURFACEFORMAT_R10G10B10A2_SSCALED            0x1B5

#define BRW_SURFACEFORMAT_R10G10B10A2_SINT               0x1B6

#define BRW_SURFACEFORMAT_B10G10R10A2_SNORM              0x1B7

#define BRW_SURFACEFORMAT_B10G10R10A2_USCALED            0x1B8

#define BRW_SURFACEFORMAT_B10G10R10A2_SSCALED            0x1B9

#define BRW_SURFACEFORMAT_B10G10R10A2_UINT               0x1BA

#define BRW_SURFACEFORMAT_B10G10R10A2_SINT               0x1BB

#define BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU          0x1BC

#define BRW_SURFACEFORMAT_R64G64B64_PASSTHRU             0x1BD

#define BRW_SURFACEFORMAT_ETC2_RGB8_PTA                  0x1C0

#define BRW_SURFACEFORMAT_ETC2_SRGB8_PTA                 0x1C1

#define BRW_SURFACEFORMAT_ETC2_EAC_RGBA8                 0x1C2

#define BRW_SURFACEFORMAT_ETC2_EAC_SRGB8_A8              0x1C3

#define BRW_SURFACEFORMAT_R8G8B8_UINT                    0x1C8

#define BRW_SURFACEFORMAT_R8G8B8_SINT                    0x1C9

#define BRW_SURFACEFORMAT_RAW                            0x1FF

#define BRW_SURFACE_FORMAT_SHIFT	18

#define BRW_SURFACE_FORMAT_MASK		INTEL_MASK(26, 18)

#define BRW_SURFACERETURNFORMAT_FLOAT32  0

#define BRW_SURFACERETURNFORMAT_S1       1

#define BRW_SURFACE_TYPE_SHIFT		29

#define BRW_SURFACE_TYPE_MASK		INTEL_MASK(31, 29)

#define BRW_SURFACE_1D      0

#define BRW_SURFACE_2D      1

#define BRW_SURFACE_3D      2

#define BRW_SURFACE_CUBE    3

#define BRW_SURFACE_BUFFER  4

#define BRW_SURFACE_NULL    7

#define GEN7_SURFACE_IS_ARRAY           (1 << 28)

#define GEN7_SURFACE_VALIGN_2           (0 << 16)

#define GEN7_SURFACE_VALIGN_4           (1 << 16)

#define GEN7_SURFACE_HALIGN_4           (0 << 15)

#define GEN7_SURFACE_HALIGN_8           (1 << 15)

#define GEN7_SURFACE_TILING_NONE        (0 << 13)

#define GEN7_SURFACE_TILING_X           (2 << 13)

#define GEN7_SURFACE_TILING_Y           (3 << 13)

#define GEN7_SURFACE_ARYSPC_FULL	(0 << 10)

#define GEN7_SURFACE_ARYSPC_LOD0	(1 << 10)

/* Surface state DW1 */

#define GEN8_SURFACE_MOCS_SHIFT         24

#define GEN8_SURFACE_MOCS_MASK          INTEL_MASK(30, 24)

#define GEN8_SURFACE_QPITCH_SHIFT       0

#define GEN8_SURFACE_QPITCH_MASK        INTEL_MASK(14, 0)

/* Surface state DW2 */

#define BRW_SURFACE_HEIGHT_SHIFT	19

#define BRW_SURFACE_HEIGHT_MASK		INTEL_MASK(31, 19)

#define BRW_SURFACE_WIDTH_SHIFT		6

#define BRW_SURFACE_WIDTH_MASK		INTEL_MASK(18, 6)

#define BRW_SURFACE_LOD_SHIFT		2

#define BRW_SURFACE_LOD_MASK		INTEL_MASK(5, 2)

#define GEN7_SURFACE_HEIGHT_SHIFT       16

#define GEN7_SURFACE_HEIGHT_MASK        INTEL_MASK(29, 16)

#define GEN7_SURFACE_WIDTH_SHIFT        0

#define GEN7_SURFACE_WIDTH_MASK         INTEL_MASK(13, 0)

/* Surface state DW3 */

#define BRW_SURFACE_DEPTH_SHIFT		21

#define BRW_SURFACE_DEPTH_MASK		INTEL_MASK(31, 21)

#define BRW_SURFACE_PITCH_SHIFT		3

#define BRW_SURFACE_PITCH_MASK		INTEL_MASK(19, 3)

#define BRW_SURFACE_TILED		(1 << 1)

#define BRW_SURFACE_TILED_Y		(1 << 0)

#define HSW_SURFACE_IS_INTEGER_FORMAT   (1 << 18)

/* Surface state DW4 */

#define BRW_SURFACE_MIN_LOD_SHIFT	28

#define BRW_SURFACE_MIN_LOD_MASK	INTEL_MASK(31, 28)

#define BRW_SURFACE_MIN_ARRAY_ELEMENT_SHIFT	17

#define BRW_SURFACE_MIN_ARRAY_ELEMENT_MASK	INTEL_MASK(27, 17)

#define BRW_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT	8

#define BRW_SURFACE_RENDER_TARGET_VIEW_EXTENT_MASK	INTEL_MASK(16, 8)

#define BRW_SURFACE_MULTISAMPLECOUNT_1  (0 << 4)

#define BRW_SURFACE_MULTISAMPLECOUNT_4  (2 << 4)

#define GEN7_SURFACE_MULTISAMPLECOUNT_1         (0 << 3)

#define GEN8_SURFACE_MULTISAMPLECOUNT_2         (1 << 3)

#define GEN7_SURFACE_MULTISAMPLECOUNT_4         (2 << 3)

#define GEN7_SURFACE_MULTISAMPLECOUNT_8         (3 << 3)

#define GEN8_SURFACE_MULTISAMPLECOUNT_16        (4 << 3)

#define GEN7_SURFACE_MSFMT_MSS                  (0 << 6)

#define GEN7_SURFACE_MSFMT_DEPTH_STENCIL        (1 << 6)

#define GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT	18

#define GEN7_SURFACE_MIN_ARRAY_ELEMENT_MASK     INTEL_MASK(28, 18)

#define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT	7

#define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_MASK   INTEL_MASK(17, 7)

/* Surface state DW5 */

#define BRW_SURFACE_X_OFFSET_SHIFT		25

#define BRW_SURFACE_X_OFFSET_MASK		INTEL_MASK(31, 25)

#define BRW_SURFACE_VERTICAL_ALIGN_ENABLE	(1 << 24)

#define BRW_SURFACE_Y_OFFSET_SHIFT		20

#define BRW_SURFACE_Y_OFFSET_MASK		INTEL_MASK(23, 20)

#define GEN7_SURFACE_MIN_LOD_SHIFT              4

#define GEN7_SURFACE_MIN_LOD_MASK               INTEL_MASK(7, 4)

#define GEN8_SURFACE_Y_OFFSET_SHIFT		21

#define GEN8_SURFACE_Y_OFFSET_MASK		INTEL_MASK(23, 21)

#define GEN7_SURFACE_MOCS_SHIFT                 16

#define GEN7_SURFACE_MOCS_MASK                  INTEL_MASK(19, 16)

/* Surface state DW6 */

#define GEN7_SURFACE_MCS_ENABLE                 (1 << 0)

#define GEN7_SURFACE_MCS_PITCH_SHIFT            3

#define GEN7_SURFACE_MCS_PITCH_MASK             INTEL_MASK(11, 3)

#define GEN8_SURFACE_AUX_QPITCH_SHIFT           16

#define GEN8_SURFACE_AUX_QPITCH_MASK            INTEL_MASK(30, 16)

#define GEN8_SURFACE_AUX_PITCH_SHIFT            3

#define GEN8_SURFACE_AUX_PITCH_MASK             INTEL_MASK(11, 3)

#define GEN8_SURFACE_AUX_MODE_MASK              INTEL_MASK(2, 0)

#define GEN8_SURFACE_AUX_MODE_NONE              0

#define GEN8_SURFACE_AUX_MODE_MCS               1

#define GEN8_SURFACE_AUX_MODE_APPEND            2

#define GEN8_SURFACE_AUX_MODE_HIZ               3

/* Surface state DW7 */

#define GEN9_SURFACE_RT_COMPRESSION_SHIFT       30

#define GEN9_SURFACE_RT_COMPRESSION_MASK        INTEL_MASK(30, 30)

#define GEN7_SURFACE_CLEAR_COLOR_SHIFT		28

#define GEN7_SURFACE_SCS_R_SHIFT                25

#define GEN7_SURFACE_SCS_R_MASK                 INTEL_MASK(27, 25)

#define GEN7_SURFACE_SCS_G_SHIFT                22

#define GEN7_SURFACE_SCS_G_MASK                 INTEL_MASK(24, 22)

#define GEN7_SURFACE_SCS_B_SHIFT                19

#define GEN7_SURFACE_SCS_B_MASK                 INTEL_MASK(21, 19)

#define GEN7_SURFACE_SCS_A_SHIFT                16

#define GEN7_SURFACE_SCS_A_MASK                 INTEL_MASK(18, 16)

/* The actual swizzle values/what channel to use */

#define HSW_SCS_ZERO                     0

#define HSW_SCS_ONE                      1

#define HSW_SCS_RED                      4

#define HSW_SCS_GREEN                    5

#define HSW_SCS_BLUE                     6

#define HSW_SCS_ALPHA                    7

/* SAMPLER_STATE DW0 */

#define BRW_SAMPLER_DISABLE                     (1 << 31)

#define BRW_SAMPLER_LOD_PRECLAMP_ENABLE         (1 << 28)

#define GEN6_SAMPLER_MIN_MAG_NOT_EQUAL          (1 << 27) /* Gen6 only */

#define BRW_SAMPLER_BASE_MIPLEVEL_MASK          INTEL_MASK(26, 22)

#define BRW_SAMPLER_BASE_MIPLEVEL_SHIFT         22

#define BRW_SAMPLER_MIP_FILTER_MASK             INTEL_MASK(21, 20)

#define BRW_SAMPLER_MIP_FILTER_SHIFT            20

#define BRW_SAMPLER_MAG_FILTER_MASK             INTEL_MASK(19, 17)

#define BRW_SAMPLER_MAG_FILTER_SHIFT            17

#define BRW_SAMPLER_MIN_FILTER_MASK             INTEL_MASK(16, 14)

#define BRW_SAMPLER_MIN_FILTER_SHIFT            14

#define GEN4_SAMPLER_LOD_BIAS_MASK              INTEL_MASK(13, 3)

#define GEN4_SAMPLER_LOD_BIAS_SHIFT             3

#define GEN4_SAMPLER_SHADOW_FUNCTION_MASK       INTEL_MASK(2, 0)

#define GEN4_SAMPLER_SHADOW_FUNCTION_SHIFT      0

#define GEN7_SAMPLER_LOD_BIAS_MASK              INTEL_MASK(13, 1)

#define GEN7_SAMPLER_LOD_BIAS_SHIFT             1

#define GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHM  (1 << 0)

/* SAMPLER_STATE DW1 */

#define GEN4_SAMPLER_MIN_LOD_MASK               INTEL_MASK(31, 22)

#define GEN4_SAMPLER_MIN_LOD_SHIFT              22

#define GEN4_SAMPLER_MAX_LOD_MASK               INTEL_MASK(21, 12)

#define GEN4_SAMPLER_MAX_LOD_SHIFT              12

#define GEN4_SAMPLER_CUBE_CONTROL_OVERRIDE      (1 << 9)

/* Wrap modes are in DW1 on Gen4-6 and DW3 on Gen7+ */

#define BRW_SAMPLER_TCX_WRAP_MODE_MASK          INTEL_MASK(8, 6)

#define BRW_SAMPLER_TCX_WRAP_MODE_SHIFT         6

#define BRW_SAMPLER_TCY_WRAP_MODE_MASK          INTEL_MASK(5, 3)

#define BRW_SAMPLER_TCY_WRAP_MODE_SHIFT         3

#define BRW_SAMPLER_TCZ_WRAP_MODE_MASK          INTEL_MASK(2, 0)

#define BRW_SAMPLER_TCZ_WRAP_MODE_SHIFT         0

#define GEN7_SAMPLER_MIN_LOD_MASK               INTEL_MASK(31, 20)

#define GEN7_SAMPLER_MIN_LOD_SHIFT              20

#define GEN7_SAMPLER_MAX_LOD_MASK               INTEL_MASK(19, 8)

#define GEN7_SAMPLER_MAX_LOD_SHIFT              8

#define GEN7_SAMPLER_SHADOW_FUNCTION_MASK       INTEL_MASK(3, 1)

#define GEN7_SAMPLER_SHADOW_FUNCTION_SHIFT      1

#define GEN7_SAMPLER_CUBE_CONTROL_OVERRIDE      (1 << 0)

/* SAMPLER_STATE DW2 - border color pointer */

/* SAMPLER_STATE DW3 */

#define BRW_SAMPLER_MAX_ANISOTROPY_MASK         INTEL_MASK(21, 19)

#define BRW_SAMPLER_MAX_ANISOTROPY_SHIFT        19

#define BRW_SAMPLER_ADDRESS_ROUNDING_MASK       INTEL_MASK(18, 13)

#define BRW_SAMPLER_ADDRESS_ROUNDING_SHIFT      13

#define GEN7_SAMPLER_NON_NORMALIZED_COORDINATES (1 << 10)

/* Gen7+ wrap modes reuse the same BRW_SAMPLER_TC*_WRAP_MODE enums. */

#define GEN6_SAMPLER_NON_NORMALIZED_COORDINATES (1 << 0)

enum brw_wrap_mode {

   BRW_TEXCOORDMODE_WRAP         = 0,

   BRW_TEXCOORDMODE_MIRROR       = 1,

   BRW_TEXCOORDMODE_CLAMP        = 2,

   BRW_TEXCOORDMODE_CUBE         = 3,

   BRW_TEXCOORDMODE_CLAMP_BORDER = 4,

   BRW_TEXCOORDMODE_MIRROR_ONCE  = 5,

   GEN8_TEXCOORDMODE_HALF_BORDER = 6,

};

#define BRW_THREAD_PRIORITY_NORMAL   0

#define BRW_THREAD_PRIORITY_HIGH     1

#define BRW_TILEWALK_XMAJOR                 0

#define BRW_TILEWALK_YMAJOR                 1

#define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS  0

#define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS  1

/* Execution Unit (EU) defines

 */

#define BRW_ALIGN_1   0

#define BRW_ALIGN_16  1

#define BRW_ADDRESS_DIRECT                        0

#define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER    1

#define BRW_CHANNEL_X     0

#define BRW_CHANNEL_Y     1

#define BRW_CHANNEL_Z     2

#define BRW_CHANNEL_W     3

enum brw_compression {

   BRW_COMPRESSION_NONE       = 0,

   BRW_COMPRESSION_2NDHALF    = 1,

   BRW_COMPRESSION_COMPRESSED = 2,

};

#define GEN6_COMPRESSION_1Q		0

#define GEN6_COMPRESSION_2Q		1

#define GEN6_COMPRESSION_3Q		2

#define GEN6_COMPRESSION_4Q		3

#define GEN6_COMPRESSION_1H		0

#define GEN6_COMPRESSION_2H		2

enum PACKED brw_conditional_mod {

   BRW_CONDITIONAL_NONE = 0,

   BRW_CONDITIONAL_Z    = 1,

   BRW_CONDITIONAL_NZ   = 2,

   BRW_CONDITIONAL_EQ   = 1,	/* Z */

   BRW_CONDITIONAL_NEQ  = 2,	/* NZ */

   BRW_CONDITIONAL_G    = 3,

   BRW_CONDITIONAL_GE   = 4,

   BRW_CONDITIONAL_L    = 5,

   BRW_CONDITIONAL_LE   = 6,

   BRW_CONDITIONAL_R    = 7,    /* Gen <= 5 */

   BRW_CONDITIONAL_O    = 8,

   BRW_CONDITIONAL_U    = 9,

};

#define BRW_DEBUG_NONE        0

#define BRW_DEBUG_BREAKPOINT  1

#define BRW_DEPENDENCY_NORMAL         0

#define BRW_DEPENDENCY_NOTCLEARED     1

#define BRW_DEPENDENCY_NOTCHECKED     2

#define BRW_DEPENDENCY_DISABLE        3

enum PACKED brw_execution_size {

   BRW_EXECUTE_1  = 0,

   BRW_EXECUTE_2  = 1,

   BRW_EXECUTE_4  = 2,

   BRW_EXECUTE_8  = 3,

   BRW_EXECUTE_16 = 4,

   BRW_EXECUTE_32 = 5,

};

enum PACKED brw_horizontal_stride {

   BRW_HORIZONTAL_STRIDE_0 = 0,

   BRW_HORIZONTAL_STRIDE_1 = 1,

   BRW_HORIZONTAL_STRIDE_2 = 2,

   BRW_HORIZONTAL_STRIDE_4 = 3,

};

#define BRW_INSTRUCTION_NORMAL    0

#define BRW_INSTRUCTION_SATURATE  1

#define BRW_MASK_ENABLE   0

#define BRW_MASK_DISABLE  1

/** @{

 *

 * Gen6 has replaced "mask enable/disable" with WECtrl, which is

 * effectively the same but much simpler to think about.  Now, there

 * are two contributors ANDed together to whether channels are

 * executed: The predication on the instruction, and the channel write

 * enable.

 */

/**

 * This is the default value.  It means that a channel's write enable is set

 * if the per-channel IP is pointing at this instruction.

 */

#define BRW_WE_NORMAL		0

/**

 * This is used like BRW_MASK_DISABLE, and causes all channels to have

 * their write enable set.  Note that predication still contributes to

 * whether the channel actually gets written.

 */

#define BRW_WE_ALL		1

/** @} */

enum opcode {

   /* These are the actual hardware opcodes. */

   BRW_OPCODE_MOV =	1,

   BRW_OPCODE_SEL =	2,

   BRW_OPCODE_NOT =	4,

   BRW_OPCODE_AND =	5,

   BRW_OPCODE_OR =	6,

   BRW_OPCODE_XOR =	7,

   BRW_OPCODE_SHR =	8,

   BRW_OPCODE_SHL =	9,

   BRW_OPCODE_ASR =	12,

   BRW_OPCODE_CMP =	16,

   BRW_OPCODE_CMPN =	17,

   BRW_OPCODE_CSEL =	18,  /**< Gen8+ */

   BRW_OPCODE_F32TO16 = 19,  /**< Gen7 only */

   BRW_OPCODE_F16TO32 = 20,  /**< Gen7 only */

   BRW_OPCODE_BFREV =	23,  /**< Gen7+ */

   BRW_OPCODE_BFE =	24,  /**< Gen7+ */

   BRW_OPCODE_BFI1 =	25,  /**< Gen7+ */

   BRW_OPCODE_BFI2 =	26,  /**< Gen7+ */

   BRW_OPCODE_JMPI =	32,

   BRW_OPCODE_IF =	34,

   BRW_OPCODE_IFF =	35,  /**< Pre-Gen6 */

   BRW_OPCODE_ELSE =	36,

   BRW_OPCODE_ENDIF =	37,

   BRW_OPCODE_DO =	38,

   BRW_OPCODE_WHILE =	39,

   BRW_OPCODE_BREAK =	40,

   BRW_OPCODE_CONTINUE = 41,

   BRW_OPCODE_HALT =	42,

   BRW_OPCODE_MSAVE =	44,  /**< Pre-Gen6 */

   BRW_OPCODE_MRESTORE = 45, /**< Pre-Gen6 */

   BRW_OPCODE_PUSH =	46,  /**< Pre-Gen6 */

   BRW_OPCODE_GOTO =	46,  /**< Gen8+    */

   BRW_OPCODE_POP =	47,  /**< Pre-Gen6 */

   BRW_OPCODE_WAIT =	48,

   BRW_OPCODE_SEND =	49,

   BRW_OPCODE_SENDC =	50,

   BRW_OPCODE_MATH =	56,  /**< Gen6+ */

   BRW_OPCODE_ADD =	64,

   BRW_OPCODE_MUL =	65,

   BRW_OPCODE_AVG =	66,

   BRW_OPCODE_FRC =	67,

   BRW_OPCODE_RNDU =	68,

   BRW_OPCODE_RNDD =	69,

   BRW_OPCODE_RNDE =	70,

   BRW_OPCODE_RNDZ =	71,

   BRW_OPCODE_MAC =	72,

   BRW_OPCODE_MACH =	73,

   BRW_OPCODE_LZD =	74,

   BRW_OPCODE_FBH =	75,  /**< Gen7+ */

   BRW_OPCODE_FBL =	76,  /**< Gen7+ */

   BRW_OPCODE_CBIT =	77,  /**< Gen7+ */

   BRW_OPCODE_ADDC =	78,  /**< Gen7+ */

   BRW_OPCODE_SUBB =	79,  /**< Gen7+ */

   BRW_OPCODE_SAD2 =	80,

   BRW_OPCODE_SADA2 =	81,

   BRW_OPCODE_DP4 =	84,

   BRW_OPCODE_DPH =	85,

   BRW_OPCODE_DP3 =	86,

   BRW_OPCODE_DP2 =	87,

   BRW_OPCODE_LINE =	89,

   BRW_OPCODE_PLN =	90,  /**< G45+ */

   BRW_OPCODE_MAD =	91,  /**< Gen6+ */

   BRW_OPCODE_LRP =	92,  /**< Gen6+ */

   BRW_OPCODE_NENOP =	125, /**< G45 only */

   BRW_OPCODE_NOP =	126,

   /* These are compiler backend opcodes that get translated into other

    * instructions.

    */

   FS_OPCODE_FB_WRITE = 128,

   FS_OPCODE_BLORP_FB_WRITE,

   FS_OPCODE_REP_FB_WRITE,

   SHADER_OPCODE_RCP,

   SHADER_OPCODE_RSQ,

   SHADER_OPCODE_SQRT,

   SHADER_OPCODE_EXP2,

   SHADER_OPCODE_LOG2,

   SHADER_OPCODE_POW,

   SHADER_OPCODE_INT_QUOTIENT,

   SHADER_OPCODE_INT_REMAINDER,

   SHADER_OPCODE_SIN,

   SHADER_OPCODE_COS,

   SHADER_OPCODE_TEX,

   SHADER_OPCODE_TXD,

   SHADER_OPCODE_TXF,

   SHADER_OPCODE_TXL,

   SHADER_OPCODE_TXS,

   FS_OPCODE_TXB,

   SHADER_OPCODE_TXF_CMS,

   SHADER_OPCODE_TXF_UMS,

   SHADER_OPCODE_TXF_MCS,

   SHADER_OPCODE_LOD,

   SHADER_OPCODE_TG4,

   SHADER_OPCODE_TG4_OFFSET,

   /**

    * Combines multiple sources of size 1 into a larger virtual GRF.

    * For example, parameters for a send-from-GRF message.  Or, updating

    * channels of a size 4 VGRF used to store vec4s such as texturing results.

    *

    * This will be lowered into MOVs from each source to consecutive reg_offsets

    * of the destination VGRF.

    *

    * src[0] may be BAD_FILE.  If so, the lowering pass skips emitting the MOV,

    * but still reserves the first channel of the destination VGRF.  This can be

    * used to reserve space for, say, a message header set up by the generators.

    */

   SHADER_OPCODE_LOAD_PAYLOAD,

   SHADER_OPCODE_SHADER_TIME_ADD,

   SHADER_OPCODE_UNTYPED_ATOMIC,

   SHADER_OPCODE_UNTYPED_SURFACE_READ,

   SHADER_OPCODE_UNTYPED_SURFACE_WRITE,

   SHADER_OPCODE_TYPED_ATOMIC,

   SHADER_OPCODE_TYPED_SURFACE_READ,

   SHADER_OPCODE_TYPED_SURFACE_WRITE,

   SHADER_OPCODE_MEMORY_FENCE,

   SHADER_OPCODE_GEN4_SCRATCH_READ,

   SHADER_OPCODE_GEN4_SCRATCH_WRITE,

   SHADER_OPCODE_GEN7_SCRATCH_READ,

   SHADER_OPCODE_URB_WRITE_SIMD8,

   /**

    * Return the index of an arbitrary live channel (i.e. one of the channels

    * enabled in the current execution mask) and assign it to the first

    * component of the destination.  Expected to be used as input for the

    * BROADCAST pseudo-opcode.

    */

   SHADER_OPCODE_FIND_LIVE_CHANNEL,

   /**

    * Pick the channel from its first source register given by the index

    * specified as second source.  Useful for variable indexing of surfaces.

    */

   SHADER_OPCODE_BROADCAST,

   VEC4_OPCODE_MOV_BYTES,

   VEC4_OPCODE_PACK_BYTES,

   VEC4_OPCODE_UNPACK_UNIFORM,

   FS_OPCODE_DDX_COARSE,

   FS_OPCODE_DDX_FINE,

   /**

    * Compute dFdy(), dFdyCoarse(), or dFdyFine().

    * src1 is an immediate storing the key->render_to_fbo boolean.

    */

   FS_OPCODE_DDY_COARSE,

   FS_OPCODE_DDY_FINE,

   FS_OPCODE_CINTERP,

   FS_OPCODE_LINTERP,

   FS_OPCODE_PIXEL_X,

   FS_OPCODE_PIXEL_Y,

   FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,

   FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,

   FS_OPCODE_VARYING_PULL_CONSTANT_LOAD,

   FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,

   FS_OPCODE_MOV_DISPATCH_TO_FLAGS,

   FS_OPCODE_DISCARD_JUMP,

   FS_OPCODE_SET_OMASK,

   FS_OPCODE_SET_SAMPLE_ID,

   FS_OPCODE_SET_SIMD4X2_OFFSET,

   FS_OPCODE_PACK_HALF_2x16_SPLIT,

   FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X,

   FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y,

   FS_OPCODE_PLACEHOLDER_HALT,

   FS_OPCODE_INTERPOLATE_AT_CENTROID,

   FS_OPCODE_INTERPOLATE_AT_SAMPLE,

   FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,

   FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,

   VS_OPCODE_URB_WRITE,

   VS_OPCODE_PULL_CONSTANT_LOAD,

   VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,

   VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,

   VS_OPCODE_UNPACK_FLAGS_SIMD4X2,

   /**

    * Write geometry shader output data to the URB.

    *

    * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from

    * R0 to the first MRF.  This allows the geometry shader to override the

    * "Slot {0,1} Offset" fields in the message header.

    */

   GS_OPCODE_URB_WRITE,

   /**

    * Write geometry shader output data to the URB and request a new URB

    * handle (gen6).

    *

    * This opcode doesn't do an implied move from R0 to the first MRF.

    */

   GS_OPCODE_URB_WRITE_ALLOCATE,

   /**

    * Terminate the geometry shader thread by doing an empty URB write.

    *

    * This opcode doesn't do an implied move from R0 to the first MRF.  This

    * allows the geometry shader to override the "GS Number of Output Vertices

    * for Slot {0,1}" fields in the message header.

    */

   GS_OPCODE_THREAD_END,

   /**

    * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.

    *

    * - dst is the MRF containing the message header.

    *

    * - src0.x indicates which portion of the URB should be written to (e.g. a

    *   vertex number)

    *

    * - src1 is an immediate multiplier which will be applied to src0

    *   (e.g. the size of a single vertex in the URB).

    *

    * Note: the hardware will apply this offset *in addition to* the offset in

    * vec4_instruction::offset.

    */

   GS_OPCODE_SET_WRITE_OFFSET,

   /**

    * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a

    * URB_WRITE message header.

    *

    * - dst is the MRF containing the message header.

    *

    * - src0.x is the vertex count.  The upper 16 bits will be ignored.

    */

   GS_OPCODE_SET_VERTEX_COUNT,

   /**

    * Set DWORD 2 of dst to the value in src.

    */

   GS_OPCODE_SET_DWORD_2,

   /**

    * Prepare the dst register for storage in the "Channel Mask" fields of a

    * URB_WRITE message header.

    *

    * DWORD 4 of dst is shifted left by 4 bits, so that later,

    * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the

    * final channel mask.

    *

    * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to

    * form the final channel mask, DWORDs 0 and 4 of the dst register must not

    * have any extraneous bits set prior to execution of this opcode (that is,

    * they should be in the range 0x0 to 0xf).

    */

   GS_OPCODE_PREPARE_CHANNEL_MASKS,

   /**

    * Set the "Channel Mask" fields of a URB_WRITE message header.

    *

    * - dst is the MRF containing the message header.

    *

    * - src.x is the channel mask, as prepared by

    *   GS_OPCODE_PREPARE_CHANNEL_MASKS.  DWORDs 0 and 4 are OR'ed together to

    *   form the final channel mask.

    */

   GS_OPCODE_SET_CHANNEL_MASKS,

   /**

    * Get the "Instance ID" fields from the payload.

    *

    * - dst is the GRF for gl_InvocationID.

    */

   GS_OPCODE_GET_INSTANCE_ID,

   /**

    * Send a FF_SYNC message to allocate initial URB handles (gen6).

    *

    * - dst will be used as the writeback register for the FF_SYNC operation.

    *

    * - src0 is the number of primitives written.

    *

    * - src1 is the value to hold in M0.0: number of SO vertices to write

    *   and number of SO primitives needed. Its value will be overwritten

    *   with the SVBI values if transform feedback is enabled.

    *

    * Note: This opcode uses an implicit MRF register for the ff_sync message

    * header, so the caller is expected to set inst->base_mrf and initialize

    * that MRF register to r0. This opcode will also write to this MRF register

    * to include the allocated URB handle so it can then be reused directly as

    * the header in the URB write operation we are allocating the handle for.

    */

   GS_OPCODE_FF_SYNC,

   /**

    * Move r0.1 (which holds PrimitiveID information in gen6) to a separate

    * register.

    *

    * - dst is the GRF where PrimitiveID information will be moved.

    */

   GS_OPCODE_SET_PRIMITIVE_ID,

   /**

    * Write transform feedback data to the SVB by sending a SVB WRITE message.

    * Used in gen6.

    *

    * - dst is the MRF register containing the message header.

    *

    * - src0 is the register where the vertex data is going to be copied from.

    *

    * - src1 is the destination register when write commit occurs.

    */

   GS_OPCODE_SVB_WRITE,

   /**

    * Set destination index in the SVB write message payload (M0.5). Used

    * in gen6 for transform feedback.

    *

    * - dst is the header to save the destination indices for SVB WRITE.

    * - src is the register that holds the destination indices value.

    */

   GS_OPCODE_SVB_SET_DST_INDEX,

   /**

    * Prepare Mx.0 subregister for being used in the FF_SYNC message header.

    * Used in gen6 for transform feedback.

    *

    * - dst will hold the register with the final Mx.0 value.

    *

    * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)

    *

    * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)

    *

    * - src2 is the value to hold in M0: number of SO vertices to write