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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5564 | serge | 1 | /* |
| 2 | * Copyright © 2014 Broadcom |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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| 21 | * IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |||
| 24 | #include "vc4_qpu.h" |
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| 25 | |||
| 26 | static bool |
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| 27 | writes_reg(uint64_t inst, uint32_t w) |
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| 28 | { |
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| 29 | return (QPU_GET_FIELD(inst, QPU_WADDR_ADD) == w || |
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| 30 | QPU_GET_FIELD(inst, QPU_WADDR_MUL) == w); |
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| 31 | } |
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| 32 | |||
| 33 | static bool |
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| 34 | _reads_reg(uint64_t inst, uint32_t r, bool ignore_a, bool ignore_b) |
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| 35 | { |
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| 36 | struct { |
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| 37 | uint32_t mux, addr; |
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| 38 | } src_regs[] = { |
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| 39 | { QPU_GET_FIELD(inst, QPU_ADD_A) }, |
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| 40 | { QPU_GET_FIELD(inst, QPU_ADD_B) }, |
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| 41 | { QPU_GET_FIELD(inst, QPU_MUL_A) }, |
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| 42 | { QPU_GET_FIELD(inst, QPU_MUL_B) }, |
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| 43 | }; |
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| 44 | |||
| 45 | for (int i = 0; i < ARRAY_SIZE(src_regs); i++) { |
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| 46 | if (!ignore_a && |
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| 47 | src_regs[i].mux == QPU_MUX_A && |
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| 48 | (QPU_GET_FIELD(inst, QPU_RADDR_A) == r)) |
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| 49 | return true; |
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| 50 | |||
| 51 | if (!ignore_b && |
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| 52 | QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM && |
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| 53 | src_regs[i].mux == QPU_MUX_B && |
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| 54 | (QPU_GET_FIELD(inst, QPU_RADDR_B) == r)) |
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| 55 | return true; |
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| 56 | } |
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| 57 | |||
| 58 | return false; |
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| 59 | } |
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| 60 | |||
| 61 | static bool |
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| 62 | reads_reg(uint64_t inst, uint32_t r) |
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| 63 | { |
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| 64 | return _reads_reg(inst, r, false, false); |
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| 65 | } |
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| 66 | |||
| 67 | static bool |
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| 68 | reads_a_reg(uint64_t inst, uint32_t r) |
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| 69 | { |
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| 70 | return _reads_reg(inst, r, false, true); |
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| 71 | } |
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| 72 | |||
| 73 | static bool |
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| 74 | reads_b_reg(uint64_t inst, uint32_t r) |
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| 75 | { |
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| 76 | return _reads_reg(inst, r, true, false); |
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| 77 | } |
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| 78 | |||
| 79 | static bool |
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| 80 | writes_sfu(uint64_t inst) |
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| 81 | { |
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| 82 | return (writes_reg(inst, QPU_W_SFU_RECIP) || |
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| 83 | writes_reg(inst, QPU_W_SFU_RECIPSQRT) || |
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| 84 | writes_reg(inst, QPU_W_SFU_EXP) || |
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| 85 | writes_reg(inst, QPU_W_SFU_LOG)); |
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| 86 | } |
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| 87 | |||
| 88 | /** |
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| 89 | * Checks for the instruction restrictions from page 37 ("Summary of |
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| 90 | * Instruction Restrictions"). |
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| 91 | */ |
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| 92 | void |
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| 93 | vc4_qpu_validate(uint64_t *insts, uint32_t num_inst) |
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| 94 | { |
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| 95 | bool scoreboard_locked = false; |
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| 96 | |||
| 97 | for (int i = 0; i < num_inst; i++) { |
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| 98 | uint64_t inst = insts[i]; |
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| 99 | |||
| 100 | if (QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_PROG_END) { |
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| 101 | if (qpu_inst_is_tlb(inst)) |
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| 102 | scoreboard_locked = true; |
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| 103 | |||
| 104 | continue; |
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| 105 | } |
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| 106 | |||
| 107 | /* "The Thread End instruction must not write to either physical |
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| 108 | * regfile A or B." |
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| 109 | */ |
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| 110 | assert(QPU_GET_FIELD(inst, QPU_WADDR_ADD) >= 32); |
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| 111 | assert(QPU_GET_FIELD(inst, QPU_WADDR_MUL) >= 32); |
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| 112 | |||
| 113 | /* Can't trigger an implicit wait on scoreboard in the program |
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| 114 | * end instruction. |
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| 115 | */ |
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| 116 | assert(!qpu_inst_is_tlb(inst) || scoreboard_locked); |
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| 117 | |||
| 118 | /* Two delay slots will be executed. */ |
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| 119 | assert(i + 2 <= num_inst); |
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| 120 | |||
| 121 | for (int j = i; j < i + 2; j++) { |
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| 122 | /* "The last three instructions of any program |
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| 123 | * (Thread End plus the following two delay-slot |
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| 124 | * instructions) must not do varyings read, uniforms |
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| 125 | * read or any kind of VPM, VDR, or VDW read or |
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| 126 | * write." |
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| 127 | */ |
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| 128 | assert(!writes_reg(insts[j], QPU_W_VPM)); |
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| 129 | assert(!reads_reg(insts[j], QPU_R_VARY)); |
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| 130 | assert(!reads_reg(insts[j], QPU_R_UNIF)); |
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| 131 | assert(!reads_reg(insts[j], QPU_R_VPM)); |
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| 132 | |||
| 133 | /* "The Thread End instruction and the following two |
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| 134 | * delay slot instructions must not write or read |
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| 135 | * address 14 in either regfile A or B." |
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| 136 | */ |
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| 137 | assert(!writes_reg(insts[j], 14)); |
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| 138 | assert(!reads_reg(insts[j], 14)); |
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| 139 | |||
| 140 | } |
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| 141 | |||
| 142 | /* "The final program instruction (the second delay slot |
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| 143 | * instruction) must not do a TLB Z write." |
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| 144 | */ |
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| 145 | assert(!writes_reg(insts[i + 2], QPU_W_TLB_Z)); |
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| 146 | } |
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| 147 | |||
| 148 | /* "A scoreboard wait must not occur in the first two instructions of |
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| 149 | * a fragment shader. This is either the explicit Wait for Scoreboard |
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| 150 | * signal or an implicit wait with the first tile-buffer read or |
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| 151 | * write instruction." |
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| 152 | */ |
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| 153 | for (int i = 0; i < 2; i++) { |
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| 154 | uint64_t inst = insts[i]; |
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| 155 | |||
| 156 | assert(!qpu_inst_is_tlb(inst)); |
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| 157 | } |
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| 158 | |||
| 159 | /* "If TMU_NOSWAP is written, the write must be three instructions |
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| 160 | * before the first TMU write instruction. For example, if |
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| 161 | * TMU_NOSWAP is written in the first shader instruction, the first |
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| 162 | * TMU write cannot occur before the 4th shader instruction." |
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| 163 | */ |
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| 164 | int last_tmu_noswap = -10; |
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| 165 | for (int i = 0; i < num_inst; i++) { |
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| 166 | uint64_t inst = insts[i]; |
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| 167 | |||
| 168 | assert((i - last_tmu_noswap) > 3 || |
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| 169 | (!writes_reg(inst, QPU_W_TMU0_S) && |
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| 170 | !writes_reg(inst, QPU_W_TMU1_S))); |
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| 171 | |||
| 172 | if (writes_reg(inst, QPU_W_TMU_NOSWAP)) |
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| 173 | last_tmu_noswap = i; |
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| 174 | } |
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| 175 | |||
| 176 | /* "An instruction must not read from a location in physical regfile A |
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| 177 | * or B that was written to by the previous instruction." |
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| 178 | */ |
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| 179 | for (int i = 0; i < num_inst - 1; i++) { |
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| 180 | uint64_t inst = insts[i]; |
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| 181 | uint32_t add_waddr = QPU_GET_FIELD(inst, QPU_WADDR_ADD); |
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| 182 | uint32_t mul_waddr = QPU_GET_FIELD(inst, QPU_WADDR_MUL); |
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| 183 | uint32_t waddr_a, waddr_b; |
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| 184 | |||
| 185 | if (inst & QPU_WS) { |
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| 186 | waddr_b = add_waddr; |
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| 187 | waddr_a = mul_waddr; |
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| 188 | } else { |
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| 189 | waddr_a = add_waddr; |
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| 190 | waddr_b = mul_waddr; |
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| 191 | } |
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| 192 | |||
| 193 | assert(waddr_a >= 32 || !reads_a_reg(insts[i + 1], waddr_a)); |
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| 194 | assert(waddr_b >= 32 || !reads_b_reg(insts[i + 1], waddr_b)); |
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| 195 | } |
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| 196 | |||
| 197 | /* "After an SFU lookup instruction, accumulator r4 must not be read |
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| 198 | * in the following two instructions. Any other instruction that |
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| 199 | * results in r4 being written (that is, TMU read, TLB read, SFU |
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| 200 | * lookup) cannot occur in the two instructions following an SFU |
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| 201 | * lookup." |
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| 202 | */ |
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| 203 | int last_sfu_inst = -10; |
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| 204 | for (int i = 0; i < num_inst - 1; i++) { |
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| 205 | uint64_t inst = insts[i]; |
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| 206 | uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG); |
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| 207 | |||
| 208 | assert(i - last_sfu_inst > 2 || |
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| 209 | (!writes_sfu(inst) && |
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| 210 | sig != QPU_SIG_LOAD_TMU0 && |
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| 211 | sig != QPU_SIG_LOAD_TMU1 && |
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| 212 | sig != QPU_SIG_COLOR_LOAD)); |
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| 213 | |||
| 214 | if (writes_sfu(inst)) |
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| 215 | last_sfu_inst = i; |
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| 216 | } |
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| 217 | |||
| 218 | int last_r5_write = -10; |
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| 219 | for (int i = 0; i < num_inst - 1; i++) { |
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| 220 | uint64_t inst = insts[i]; |
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| 221 | |||
| 222 | /* "An instruction that does a vector rotate by r5 must not |
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| 223 | * immediately follow an instruction that writes to r5." |
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| 224 | */ |
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| 225 | assert(last_r5_write != i - 1 || |
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| 226 | QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM || |
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| 227 | QPU_GET_FIELD(inst, QPU_SMALL_IMM) != 48); |
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| 228 | } |
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| 229 | |||
| 230 | /* "An instruction that does a vector rotate must not immediately |
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| 231 | * follow an instruction that writes to the accumulator that is being |
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| 232 | * rotated. |
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| 233 | * |
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| 234 | * XXX: TODO. |
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| 235 | */ |
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| 236 | |||
| 237 | /* "After an instruction that does a TLB Z write, the multisample mask |
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| 238 | * must not be read as an instruction input argument in the following |
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| 239 | * two instruction. The TLB Z write instruction can, however, be |
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| 240 | * followed immediately by a TLB color write." |
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| 241 | */ |
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| 242 | for (int i = 0; i < num_inst - 1; i++) { |
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| 243 | uint64_t inst = insts[i]; |
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| 244 | if (writes_reg(inst, QPU_W_TLB_Z)) { |
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| 245 | assert(!reads_a_reg(insts[i + 1], QPU_R_MS_REV_FLAGS)); |
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| 246 | assert(!reads_a_reg(insts[i + 2], QPU_R_MS_REV_FLAGS)); |
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| 247 | } |
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| 248 | } |
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| 249 | |||
| 250 | /* |
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| 251 | * "A single instruction can only perform a maximum of one of the |
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| 252 | * following closely coupled peripheral accesses in a single |
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| 253 | * instruction: TMU write, TMU read, TLB write, TLB read, TLB |
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| 254 | * combined color read and write, SFU write, Mutex read or Semaphore |
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| 255 | * access." |
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| 256 | */ |
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| 257 | for (int i = 0; i < num_inst - 1; i++) { |
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| 258 | uint64_t inst = insts[i]; |
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| 259 | |||
| 260 | assert(qpu_num_sf_accesses(inst) <= 1); |
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| 261 | } |
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| 262 | } |