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Rev | Author | Line No. | Line |
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5564 | serge | 1 | /* |
2 | * Copyright 2012 Nouveau Project |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Christoph Bumiller |
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23 | */ |
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24 | |||
25 | #include "nvc0/nvc0_context.h" |
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26 | #include "nvc0/nvc0_compute.h" |
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27 | #include "nvc0/nve4_compute.h" |
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28 | |||
29 | #include "codegen/nv50_ir_driver.h" |
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30 | |||
31 | #ifdef DEBUG |
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32 | static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *); |
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33 | #endif |
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34 | |||
35 | |||
36 | int |
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37 | nve4_screen_compute_setup(struct nvc0_screen *screen, |
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38 | struct nouveau_pushbuf *push) |
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39 | { |
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40 | struct nouveau_device *dev = screen->base.device; |
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41 | struct nouveau_object *chan = screen->base.channel; |
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42 | unsigned i; |
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43 | int ret; |
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44 | uint32_t obj_class; |
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45 | |||
46 | switch (dev->chipset & ~0xf) { |
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47 | case 0x100: |
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48 | case 0xf0: |
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49 | obj_class = NVF0_COMPUTE_CLASS; /* GK110 */ |
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50 | break; |
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51 | case 0xe0: |
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52 | obj_class = NVE4_COMPUTE_CLASS; /* GK104 */ |
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53 | break; |
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54 | default: |
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55 | NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset); |
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56 | return -1; |
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57 | } |
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58 | |||
59 | ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0, |
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60 | &screen->compute); |
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61 | if (ret) { |
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62 | NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret); |
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63 | return ret; |
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64 | } |
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65 | |||
66 | ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, NVE4_CP_PARAM_SIZE, NULL, |
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67 | &screen->parm); |
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68 | if (ret) |
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69 | return ret; |
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70 | |||
71 | BEGIN_NVC0(push, SUBC_COMPUTE(NV01_SUBCHAN_OBJECT), 1); |
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72 | PUSH_DATA (push, screen->compute->oclass); |
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73 | |||
74 | BEGIN_NVC0(push, NVE4_COMPUTE(TEMP_ADDRESS_HIGH), 2); |
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75 | PUSH_DATAh(push, screen->tls->offset); |
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76 | PUSH_DATA (push, screen->tls->offset); |
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77 | /* No idea why there are 2. Divide size by 2 to be safe. |
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78 | * Actually this might be per-MP TEMP size and looks like I'm only using |
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79 | * 2 MPs instead of all 8. |
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80 | */ |
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81 | BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(0)), 3); |
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82 | PUSH_DATAh(push, screen->tls->size / screen->mp_count); |
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83 | PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff); |
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84 | PUSH_DATA (push, 0xff); |
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85 | BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(1)), 3); |
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86 | PUSH_DATAh(push, screen->tls->size / screen->mp_count); |
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87 | PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff); |
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88 | PUSH_DATA (push, 0xff); |
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89 | |||
90 | /* Unified address space ? Who needs that ? Certainly not OpenCL. |
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91 | * |
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92 | * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be |
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93 | * accessible. We cannot prevent that at the moment, so expect failure. |
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94 | */ |
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95 | BEGIN_NVC0(push, NVE4_COMPUTE(LOCAL_BASE), 1); |
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96 | PUSH_DATA (push, 1 << 24); |
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97 | BEGIN_NVC0(push, NVE4_COMPUTE(SHARED_BASE), 1); |
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98 | PUSH_DATA (push, 2 << 24); |
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99 | |||
100 | BEGIN_NVC0(push, NVE4_COMPUTE(CODE_ADDRESS_HIGH), 2); |
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101 | PUSH_DATAh(push, screen->text->offset); |
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102 | PUSH_DATA (push, screen->text->offset); |
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103 | |||
104 | BEGIN_NVC0(push, SUBC_COMPUTE(0x0310), 1); |
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105 | PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300); |
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106 | |||
107 | /* NOTE: these do not affect the state used by the 3D object */ |
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108 | BEGIN_NVC0(push, NVE4_COMPUTE(TIC_ADDRESS_HIGH), 3); |
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109 | PUSH_DATAh(push, screen->txc->offset); |
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110 | PUSH_DATA (push, screen->txc->offset); |
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111 | PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1); |
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112 | BEGIN_NVC0(push, NVE4_COMPUTE(TSC_ADDRESS_HIGH), 3); |
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113 | PUSH_DATAh(push, screen->txc->offset + 65536); |
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114 | PUSH_DATA (push, screen->txc->offset + 65536); |
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115 | PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1); |
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116 | |||
117 | if (obj_class >= NVF0_COMPUTE_CLASS) { |
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118 | BEGIN_NVC0(push, SUBC_COMPUTE(0x0248), 1); |
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119 | PUSH_DATA (push, 0x100); |
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120 | BEGIN_NIC0(push, SUBC_COMPUTE(0x0248), 63); |
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121 | for (i = 63; i >= 1; --i) |
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122 | PUSH_DATA(push, 0x38000 | i); |
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123 | IMMED_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 0); |
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124 | IMMED_NVC0(push, SUBC_COMPUTE(0x518), 0); |
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125 | } |
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126 | |||
127 | BEGIN_NVC0(push, NVE4_COMPUTE(TEX_CB_INDEX), 1); |
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128 | PUSH_DATA (push, 0); /* does not interefere with 3D */ |
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129 | |||
130 | if (obj_class >= NVF0_COMPUTE_CLASS) |
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131 | IMMED_NVC0(push, SUBC_COMPUTE(0x02c4), 1); |
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132 | |||
133 | /* MS sample coordinate offsets: these do not work with _ALT modes ! */ |
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134 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2); |
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135 | PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS); |
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136 | PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS); |
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137 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2); |
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138 | PUSH_DATA (push, 64); |
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139 | PUSH_DATA (push, 1); |
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140 | BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17); |
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141 | PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1)); |
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142 | PUSH_DATA (push, 0); /* 0 */ |
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143 | PUSH_DATA (push, 0); |
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144 | PUSH_DATA (push, 1); /* 1 */ |
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145 | PUSH_DATA (push, 0); |
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146 | PUSH_DATA (push, 0); /* 2 */ |
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147 | PUSH_DATA (push, 1); |
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148 | PUSH_DATA (push, 1); /* 3 */ |
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149 | PUSH_DATA (push, 1); |
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150 | PUSH_DATA (push, 2); /* 4 */ |
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151 | PUSH_DATA (push, 0); |
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152 | PUSH_DATA (push, 3); /* 5 */ |
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153 | PUSH_DATA (push, 0); |
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154 | PUSH_DATA (push, 2); /* 6 */ |
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155 | PUSH_DATA (push, 1); |
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156 | PUSH_DATA (push, 3); /* 7 */ |
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157 | PUSH_DATA (push, 1); |
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158 | |||
159 | #ifdef DEBUG |
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160 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2); |
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161 | PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR); |
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162 | PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR); |
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163 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2); |
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164 | PUSH_DATA (push, 28); |
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165 | PUSH_DATA (push, 1); |
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166 | BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 8); |
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167 | PUSH_DATA (push, 1); |
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168 | PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO); |
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169 | PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO); |
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170 | PUSH_DATA (push, screen->tls->offset); |
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171 | PUSH_DATAh(push, screen->tls->offset); |
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172 | PUSH_DATA (push, screen->tls->size / 2); /* MP TEMP block size */ |
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173 | PUSH_DATA (push, screen->tls->size / 2 / 64); /* warp TEMP block size */ |
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174 | PUSH_DATA (push, 0); /* warp cfstack size */ |
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175 | #endif |
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176 | |||
177 | BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1); |
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178 | PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB); |
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179 | |||
180 | return 0; |
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181 | } |
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182 | |||
183 | |||
184 | static void |
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185 | nve4_compute_validate_surfaces(struct nvc0_context *nvc0) |
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186 | { |
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187 | struct nvc0_screen *screen = nvc0->screen; |
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188 | struct nouveau_pushbuf *push = nvc0->base.pushbuf; |
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189 | struct nv50_surface *sf; |
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190 | struct nv04_resource *res; |
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191 | uint32_t mask; |
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192 | unsigned i; |
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193 | const unsigned t = 1; |
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194 | |||
195 | mask = nvc0->surfaces_dirty[t]; |
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196 | while (mask) { |
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197 | i = ffs(mask) - 1; |
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198 | mask &= ~(1 << i); |
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199 | |||
200 | /* |
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201 | * NVE4's surface load/store instructions receive all the information |
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202 | * directly instead of via binding points, so we have to supply them. |
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203 | */ |
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204 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2); |
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205 | PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_SUF(i)); |
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206 | PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_SUF(i)); |
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207 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2); |
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208 | PUSH_DATA (push, 64); |
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209 | PUSH_DATA (push, 1); |
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210 | BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17); |
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211 | PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1)); |
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212 | |||
213 | nve4_set_surface_info(push, nvc0->surfaces[t][i], screen); |
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214 | |||
215 | sf = nv50_surface(nvc0->surfaces[t][i]); |
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216 | if (sf) { |
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217 | res = nv04_resource(sf->base.texture); |
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218 | |||
219 | if (sf->base.writable) |
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220 | BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR); |
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221 | else |
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222 | BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD); |
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223 | } |
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224 | } |
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225 | if (nvc0->surfaces_dirty[t]) { |
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226 | BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1); |
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227 | PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB); |
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228 | } |
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229 | |||
230 | /* re-reference non-dirty surfaces */ |
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231 | mask = nvc0->surfaces_valid[t] & ~nvc0->surfaces_dirty[t]; |
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232 | while (mask) { |
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233 | i = ffs(mask) - 1; |
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234 | mask &= ~(1 << i); |
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235 | |||
236 | sf = nv50_surface(nvc0->surfaces[t][i]); |
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237 | res = nv04_resource(sf->base.texture); |
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238 | |||
239 | if (sf->base.writable) |
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240 | BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR); |
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241 | else |
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242 | BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD); |
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243 | } |
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244 | |||
245 | nvc0->surfaces_dirty[t] = 0; |
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246 | } |
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247 | |||
248 | |||
249 | /* Thankfully, textures with samplers follow the normal rules. */ |
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250 | static void |
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251 | nve4_compute_validate_samplers(struct nvc0_context *nvc0) |
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252 | { |
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253 | boolean need_flush = nve4_validate_tsc(nvc0, 5); |
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254 | if (need_flush) { |
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255 | BEGIN_NVC0(nvc0->base.pushbuf, NVE4_COMPUTE(TSC_FLUSH), 1); |
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256 | PUSH_DATA (nvc0->base.pushbuf, 0); |
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257 | } |
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258 | } |
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259 | /* (Code duplicated at bottom for various non-convincing reasons. |
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260 | * E.g. we might want to use the COMPUTE subchannel to upload TIC/TSC |
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261 | * entries to avoid a subchannel switch. |
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262 | * Same for texture cache flushes. |
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263 | * Also, the bufctx differs, and more IFs in the 3D version looks ugly.) |
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264 | */ |
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265 | static void nve4_compute_validate_textures(struct nvc0_context *); |
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266 | |||
267 | static void |
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268 | nve4_compute_set_tex_handles(struct nvc0_context *nvc0) |
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269 | { |
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270 | struct nouveau_pushbuf *push = nvc0->base.pushbuf; |
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271 | uint64_t address; |
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272 | const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE); |
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273 | unsigned i, n; |
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274 | uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s]; |
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275 | |||
276 | if (!dirty) |
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277 | return; |
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278 | i = ffs(dirty) - 1; |
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279 | n = util_logbase2(dirty) + 1 - i; |
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280 | assert(n); |
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281 | |||
282 | address = nvc0->screen->parm->offset + NVE4_CP_INPUT_TEX(i); |
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283 | |||
284 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2); |
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285 | PUSH_DATAh(push, address); |
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286 | PUSH_DATA (push, address); |
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287 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2); |
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288 | PUSH_DATA (push, n * 4); |
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289 | PUSH_DATA (push, 0x1); |
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290 | BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + n); |
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291 | PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1)); |
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292 | PUSH_DATAp(push, &nvc0->tex_handles[s][i], n); |
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293 | |||
294 | BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1); |
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295 | PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB); |
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296 | |||
297 | nvc0->textures_dirty[s] = 0; |
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298 | nvc0->samplers_dirty[s] = 0; |
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299 | } |
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300 | |||
301 | |||
302 | static boolean |
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303 | nve4_compute_state_validate(struct nvc0_context *nvc0) |
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304 | { |
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305 | if (!nvc0_compute_validate_program(nvc0)) |
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306 | return FALSE; |
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307 | if (nvc0->dirty_cp & NVC0_NEW_CP_TEXTURES) |
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308 | nve4_compute_validate_textures(nvc0); |
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309 | if (nvc0->dirty_cp & NVC0_NEW_CP_SAMPLERS) |
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310 | nve4_compute_validate_samplers(nvc0); |
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311 | if (nvc0->dirty_cp & (NVC0_NEW_CP_TEXTURES | NVC0_NEW_CP_SAMPLERS)) |
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312 | nve4_compute_set_tex_handles(nvc0); |
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313 | if (nvc0->dirty_cp & NVC0_NEW_CP_SURFACES) |
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314 | nve4_compute_validate_surfaces(nvc0); |
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315 | if (nvc0->dirty_cp & NVC0_NEW_CP_GLOBALS) |
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316 | nvc0_validate_global_residents(nvc0, |
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317 | nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL); |
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318 | |||
319 | nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, FALSE); |
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320 | |||
321 | nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_cp); |
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322 | if (unlikely(nouveau_pushbuf_validate(nvc0->base.pushbuf))) |
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323 | return FALSE; |
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324 | if (unlikely(nvc0->state.flushed)) |
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325 | nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, TRUE); |
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326 | |||
327 | return TRUE; |
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328 | } |
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329 | |||
330 | |||
331 | static void |
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332 | nve4_compute_upload_input(struct nvc0_context *nvc0, const void *input, |
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333 | const uint *block_layout, |
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334 | const uint *grid_layout) |
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335 | { |
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336 | struct nvc0_screen *screen = nvc0->screen; |
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337 | struct nouveau_pushbuf *push = nvc0->base.pushbuf; |
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338 | struct nvc0_program *cp = nvc0->compprog; |
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339 | |||
340 | if (cp->parm_size) { |
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341 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2); |
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342 | PUSH_DATAh(push, screen->parm->offset); |
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343 | PUSH_DATA (push, screen->parm->offset); |
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344 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2); |
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345 | PUSH_DATA (push, cp->parm_size); |
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346 | PUSH_DATA (push, 0x1); |
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347 | BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (cp->parm_size / 4)); |
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348 | PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1)); |
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349 | PUSH_DATAp(push, input, cp->parm_size / 4); |
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350 | } |
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351 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2); |
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352 | PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0)); |
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353 | PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0)); |
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354 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2); |
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355 | PUSH_DATA (push, 7 * 4); |
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356 | PUSH_DATA (push, 0x1); |
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357 | BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + 7); |
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358 | PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1)); |
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359 | PUSH_DATAp(push, block_layout, 3); |
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360 | PUSH_DATAp(push, grid_layout, 3); |
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361 | PUSH_DATA (push, 0); |
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362 | |||
363 | BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1); |
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364 | PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB); |
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365 | } |
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366 | |||
367 | static INLINE uint8_t |
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368 | nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size) |
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369 | { |
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370 | if (shared_size > (32 << 10)) |
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371 | return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1; |
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372 | if (shared_size > (16 << 10)) |
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373 | return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1; |
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374 | return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1; |
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375 | } |
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376 | |||
377 | static void |
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378 | nve4_compute_setup_launch_desc(struct nvc0_context *nvc0, |
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379 | struct nve4_cp_launch_desc *desc, |
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380 | uint32_t label, |
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381 | const uint *block_layout, |
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382 | const uint *grid_layout) |
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383 | { |
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384 | const struct nvc0_screen *screen = nvc0->screen; |
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385 | const struct nvc0_program *cp = nvc0->compprog; |
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386 | unsigned i; |
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387 | |||
388 | nve4_cp_launch_desc_init_default(desc); |
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389 | |||
390 | desc->entry = nvc0_program_symbol_offset(cp, label); |
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391 | |||
392 | desc->griddim_x = grid_layout[0]; |
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393 | desc->griddim_y = grid_layout[1]; |
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394 | desc->griddim_z = grid_layout[2]; |
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395 | desc->blockdim_x = block_layout[0]; |
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396 | desc->blockdim_y = block_layout[1]; |
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397 | desc->blockdim_z = block_layout[2]; |
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398 | |||
399 | desc->shared_size = align(cp->cp.smem_size, 0x100); |
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400 | desc->local_size_p = align(cp->cp.lmem_size, 0x10); |
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401 | desc->local_size_n = 0; |
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402 | desc->cstack_size = 0x800; |
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403 | desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size); |
||
404 | |||
405 | desc->gpr_alloc = cp->num_gprs; |
||
406 | desc->bar_alloc = cp->num_barriers; |
||
407 | |||
408 | for (i = 0; i < 7; ++i) { |
||
409 | const unsigned s = 5; |
||
410 | if (nvc0->constbuf[s][i].u.buf) |
||
411 | nve4_cp_launch_desc_set_ctx_cb(desc, i + 1, &nvc0->constbuf[s][i]); |
||
412 | } |
||
413 | nve4_cp_launch_desc_set_cb(desc, 0, screen->parm, 0, NVE4_CP_INPUT_SIZE); |
||
414 | } |
||
415 | |||
416 | static INLINE struct nve4_cp_launch_desc * |
||
417 | nve4_compute_alloc_launch_desc(struct nouveau_context *nv, |
||
418 | struct nouveau_bo **pbo, uint64_t *pgpuaddr) |
||
419 | { |
||
420 | uint8_t *ptr = nouveau_scratch_get(nv, 512, pgpuaddr, pbo); |
||
421 | if (!ptr) |
||
422 | return NULL; |
||
423 | if (*pgpuaddr & 255) { |
||
424 | unsigned adj = 256 - (*pgpuaddr & 255); |
||
425 | ptr += adj; |
||
426 | *pgpuaddr += adj; |
||
427 | } |
||
428 | return (struct nve4_cp_launch_desc *)ptr; |
||
429 | } |
||
430 | |||
431 | void |
||
432 | nve4_launch_grid(struct pipe_context *pipe, |
||
433 | const uint *block_layout, const uint *grid_layout, |
||
434 | uint32_t label, |
||
435 | const void *input) |
||
436 | { |
||
437 | struct nvc0_context *nvc0 = nvc0_context(pipe); |
||
438 | struct nouveau_pushbuf *push = nvc0->base.pushbuf; |
||
439 | struct nve4_cp_launch_desc *desc; |
||
440 | uint64_t desc_gpuaddr; |
||
441 | struct nouveau_bo *desc_bo; |
||
442 | int ret; |
||
443 | |||
444 | desc = nve4_compute_alloc_launch_desc(&nvc0->base, &desc_bo, &desc_gpuaddr); |
||
445 | if (!desc) { |
||
446 | ret = -1; |
||
447 | goto out; |
||
448 | } |
||
449 | BCTX_REFN_bo(nvc0->bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD, |
||
450 | desc_bo); |
||
451 | |||
452 | ret = !nve4_compute_state_validate(nvc0); |
||
453 | if (ret) |
||
454 | goto out; |
||
455 | |||
456 | nve4_compute_setup_launch_desc(nvc0, desc, label, block_layout, grid_layout); |
||
457 | #ifdef DEBUG |
||
458 | if (debug_get_num_option("NV50_PROG_DEBUG", 0)) |
||
459 | nve4_compute_dump_launch_desc(desc); |
||
460 | #endif |
||
461 | |||
462 | nve4_compute_upload_input(nvc0, input, block_layout, grid_layout); |
||
463 | |||
464 | /* upload descriptor and flush */ |
||
465 | #if 0 |
||
466 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2); |
||
467 | PUSH_DATAh(push, desc_gpuaddr); |
||
468 | PUSH_DATA (push, desc_gpuaddr); |
||
469 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2); |
||
470 | PUSH_DATA (push, 256); |
||
471 | PUSH_DATA (push, 1); |
||
472 | BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (256 / 4)); |
||
473 | PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1)); |
||
474 | PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4); |
||
475 | BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1); |
||
476 | PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB | NVE4_COMPUTE_FLUSH_CODE); |
||
477 | #endif |
||
478 | BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH_DESC_ADDRESS), 1); |
||
479 | PUSH_DATA (push, desc_gpuaddr >> 8); |
||
480 | BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH), 1); |
||
481 | PUSH_DATA (push, 0x3); |
||
482 | BEGIN_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 1); |
||
483 | PUSH_DATA (push, 0); |
||
484 | |||
485 | out: |
||
486 | if (ret) |
||
487 | NOUVEAU_ERR("Failed to launch grid !\n"); |
||
488 | nouveau_scratch_done(&nvc0->base); |
||
489 | nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_DESC); |
||
490 | } |
||
491 | |||
492 | |||
493 | #define NVE4_TIC_ENTRY_INVALID 0x000fffff |
||
494 | |||
495 | static void |
||
496 | nve4_compute_validate_textures(struct nvc0_context *nvc0) |
||
497 | { |
||
498 | struct nouveau_bo *txc = nvc0->screen->txc; |
||
499 | struct nouveau_pushbuf *push = nvc0->base.pushbuf; |
||
500 | const unsigned s = 5; |
||
501 | unsigned i; |
||
502 | uint32_t commands[2][NVE4_CP_INPUT_TEX_MAX]; |
||
503 | unsigned n[2] = { 0, 0 }; |
||
504 | |||
505 | for (i = 0; i < nvc0->num_textures[s]; ++i) { |
||
506 | struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]); |
||
507 | struct nv04_resource *res; |
||
508 | const boolean dirty = !!(nvc0->textures_dirty[s] & (1 << i)); |
||
509 | |||
510 | if (!tic) { |
||
511 | nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID; |
||
512 | continue; |
||
513 | } |
||
514 | res = nv04_resource(tic->pipe.texture); |
||
515 | |||
516 | if (tic->id < 0) { |
||
517 | tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic); |
||
518 | |||
519 | PUSH_SPACE(push, 16); |
||
520 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2); |
||
521 | PUSH_DATAh(push, txc->offset + (tic->id * 32)); |
||
522 | PUSH_DATA (push, txc->offset + (tic->id * 32)); |
||
523 | BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2); |
||
524 | PUSH_DATA (push, 32); |
||
525 | PUSH_DATA (push, 1); |
||
526 | BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 9); |
||
527 | PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1)); |
||
528 | PUSH_DATAp(push, &tic->tic[0], 8); |
||
529 | |||
530 | commands[0][n[0]++] = (tic->id << 4) | 1; |
||
531 | } else |
||
532 | if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { |
||
533 | commands[1][n[1]++] = (tic->id << 4) | 1; |
||
534 | } |
||
535 | nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32); |
||
536 | |||
537 | res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING; |
||
538 | res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING; |
||
539 | |||
540 | nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID; |
||
541 | nvc0->tex_handles[s][i] |= tic->id; |
||
542 | if (dirty) |
||
543 | BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD); |
||
544 | } |
||
545 | for (; i < nvc0->state.num_textures[s]; ++i) |
||
546 | nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID; |
||
547 | |||
548 | if (n[0]) { |
||
549 | BEGIN_NIC0(push, NVE4_COMPUTE(TIC_FLUSH), n[0]); |
||
550 | PUSH_DATAp(push, commands[0], n[0]); |
||
551 | } |
||
552 | if (n[1]) { |
||
553 | BEGIN_NIC0(push, NVE4_COMPUTE(TEX_CACHE_CTL), n[1]); |
||
554 | PUSH_DATAp(push, commands[1], n[1]); |
||
555 | } |
||
556 | |||
557 | nvc0->state.num_textures[s] = nvc0->num_textures[s]; |
||
558 | } |
||
559 | |||
560 | |||
561 | #ifdef DEBUG |
||
562 | static const char *nve4_cache_split_name(unsigned value) |
||
563 | { |
||
564 | switch (value) { |
||
565 | case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1"; |
||
566 | case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1"; |
||
567 | case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1"; |
||
568 | default: |
||
569 | return "(invalid)"; |
||
570 | } |
||
571 | } |
||
572 | |||
573 | static void |
||
574 | nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc) |
||
575 | { |
||
576 | const uint32_t *data = (const uint32_t *)desc; |
||
577 | unsigned i; |
||
578 | boolean zero = FALSE; |
||
579 | |||
580 | debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n"); |
||
581 | |||
582 | for (i = 0; i < sizeof(*desc); i += 4) { |
||
583 | if (data[i / 4]) { |
||
584 | debug_printf("[%x]: 0x%08x\n", i, data[i / 4]); |
||
585 | zero = FALSE; |
||
586 | } else |
||
587 | if (!zero) { |
||
588 | debug_printf("...\n"); |
||
589 | zero = TRUE; |
||
590 | } |
||
591 | } |
||
592 | |||
593 | debug_printf("entry = 0x%x\n", desc->entry); |
||
594 | debug_printf("grid dimensions = %ux%ux%u\n", |
||
595 | desc->griddim_x, desc->griddim_y, desc->griddim_z); |
||
596 | debug_printf("block dimensions = %ux%ux%u\n", |
||
597 | desc->blockdim_x, desc->blockdim_y, desc->blockdim_z); |
||
598 | debug_printf("s[] size: 0x%x\n", desc->shared_size); |
||
599 | debug_printf("l[] size: -0x%x / +0x%x\n", |
||
600 | desc->local_size_n, desc->local_size_p); |
||
601 | debug_printf("stack size: 0x%x\n", desc->cstack_size); |
||
602 | debug_printf("barrier count: %u\n", desc->bar_alloc); |
||
603 | debug_printf("$r count: %u\n", desc->gpr_alloc); |
||
604 | debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split)); |
||
605 | |||
606 | for (i = 0; i < 8; ++i) { |
||
607 | uint64_t address; |
||
608 | uint32_t size = desc->cb[i].size; |
||
609 | boolean valid = !!(desc->cb_mask & (1 << i)); |
||
610 | |||
611 | address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l; |
||
612 | |||
613 | if (!valid && !address && !size) |
||
614 | continue; |
||
615 | debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n", |
||
616 | i, address, size, valid ? "" : " (invalid)"); |
||
617 | } |
||
618 | } |
||
619 | #endif |
||
620 | |||
621 | #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER |
||
622 | static void |
||
623 | nve4_compute_trap_info(struct nvc0_context *nvc0) |
||
624 | { |
||
625 | struct nvc0_screen *screen = nvc0->screen; |
||
626 | struct nouveau_bo *bo = screen->parm; |
||
627 | int ret, i; |
||
628 | volatile struct nve4_mp_trap_info *info; |
||
629 | uint8_t *map; |
||
630 | |||
631 | ret = nouveau_bo_map(bo, NOUVEAU_BO_RDWR, nvc0->base.client); |
||
632 | if (ret) |
||
633 | return; |
||
634 | map = (uint8_t *)bo->map; |
||
635 | info = (volatile struct nve4_mp_trap_info *)(map + NVE4_CP_PARAM_TRAP_INFO); |
||
636 | |||
637 | if (info->lock) { |
||
638 | debug_printf("trapstat = %08x\n", info->trapstat); |
||
639 | debug_printf("warperr = %08x\n", info->warperr); |
||
640 | debug_printf("PC = %x\n", info->pc); |
||
641 | debug_printf("tid = %u %u %u\n", |
||
642 | info->tid[0], info->tid[1], info->tid[2]); |
||
643 | debug_printf("ctaid = %u %u %u\n", |
||
644 | info->ctaid[0], info->ctaid[1], info->ctaid[2]); |
||
645 | for (i = 0; i <= 63; ++i) |
||
646 | debug_printf("$r%i = %08x\n", i, info->r[i]); |
||
647 | for (i = 0; i <= 6; ++i) |
||
648 | debug_printf("$p%i = %i\n", i, (info->flags >> i) & 1); |
||
649 | debug_printf("$c = %x\n", info->flags >> 12); |
||
650 | } |
||
651 | info->lock = 0; |
||
652 | } |
||
653 | #endif=>=>><>><>>>>><>><>><>><>>><>>><>>><>><>><>><>><>><>><>><>><>><>><> |