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5564 | serge | 1 | #ifndef GEN_MI_XML |
2 | #define GEN_MI_XML |
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3 | |||
4 | /* Autogenerated file, DO NOT EDIT manually! |
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5 | |||
6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
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7 | https://github.com/olvaffe/envytools/ |
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8 | git clone https://github.com/olvaffe/envytools.git |
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9 | |||
10 | Copyright (C) 2014-2015 by the following authors: |
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11 | - Chia-I Wu |
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12 | |||
13 | Permission is hereby granted, free of charge, to any person obtaining |
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14 | a copy of this software and associated documentation files (the |
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15 | "Software"), to deal in the Software without restriction, including |
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16 | without limitation the rights to use, copy, modify, merge, publish, |
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17 | distribute, sublicense, and/or sell copies of the Software, and to |
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18 | permit persons to whom the Software is furnished to do so, subject to |
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19 | the following conditions: |
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20 | |||
21 | The above copyright notice and this permission notice (including the |
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22 | next paragraph) shall be included in all copies or substantial |
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23 | portions of the Software. |
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24 | |||
25 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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26 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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27 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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28 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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29 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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30 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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31 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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32 | */ |
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33 | |||
34 | |||
35 | enum gen_mi_alu_opcode { |
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36 | GEN75_MI_ALU_NOOP = 0x0, |
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37 | GEN75_MI_ALU_LOAD = 0x80, |
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38 | GEN75_MI_ALU_LOADINV = 0x480, |
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39 | GEN75_MI_ALU_LOAD0 = 0x81, |
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40 | GEN75_MI_ALU_LOAD1 = 0x481, |
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41 | GEN75_MI_ALU_ADD = 0x100, |
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42 | GEN75_MI_ALU_SUB = 0x101, |
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43 | GEN75_MI_ALU_AND = 0x102, |
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44 | GEN75_MI_ALU_OR = 0x103, |
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45 | GEN75_MI_ALU_XOR = 0x104, |
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46 | GEN75_MI_ALU_STORE = 0x180, |
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47 | GEN75_MI_ALU_STOREINV = 0x580, |
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48 | }; |
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49 | |||
50 | enum gen_mi_alu_operand { |
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51 | GEN75_MI_ALU_R0 = 0x0, |
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52 | GEN75_MI_ALU_R1 = 0x1, |
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53 | GEN75_MI_ALU_R2 = 0x2, |
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54 | GEN75_MI_ALU_R3 = 0x3, |
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55 | GEN75_MI_ALU_R4 = 0x4, |
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56 | GEN75_MI_ALU_R5 = 0x5, |
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57 | GEN75_MI_ALU_R6 = 0x6, |
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58 | GEN75_MI_ALU_R7 = 0x7, |
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59 | GEN75_MI_ALU_R8 = 0x8, |
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60 | GEN75_MI_ALU_R9 = 0x9, |
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61 | GEN75_MI_ALU_R10 = 0xa, |
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62 | GEN75_MI_ALU_R11 = 0xb, |
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63 | GEN75_MI_ALU_R12 = 0xc, |
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64 | GEN75_MI_ALU_R13 = 0xd, |
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65 | GEN75_MI_ALU_R14 = 0xe, |
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66 | GEN75_MI_ALU_R15 = 0xf, |
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67 | GEN75_MI_ALU_SRCA = 0x20, |
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68 | GEN75_MI_ALU_SRCB = 0x21, |
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69 | GEN75_MI_ALU_ACCU = 0x31, |
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70 | GEN75_MI_ALU_ZF = 0x32, |
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71 | GEN75_MI_ALU_CF = 0x33, |
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72 | }; |
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73 | |||
74 | #define GEN6_MI_TYPE__MASK 0xe0000000 |
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75 | #define GEN6_MI_TYPE__SHIFT 29 |
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76 | #define GEN6_MI_TYPE_MI (0x0 << 29) |
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77 | #define GEN6_MI_OPCODE__MASK 0x1f800000 |
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78 | #define GEN6_MI_OPCODE__SHIFT 23 |
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79 | #define GEN6_MI_OPCODE_MI_NOOP (0x0 << 23) |
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80 | #define GEN75_MI_OPCODE_MI_SET_PREDICATE (0x1 << 23) |
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81 | #define GEN75_MI_OPCODE_MI_RS_CONTROL (0x6 << 23) |
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82 | #define GEN75_MI_OPCODE_MI_URB_ATOMIC_ALLOC (0x9 << 23) |
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83 | #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_END (0xa << 23) |
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84 | #define GEN7_MI_OPCODE_MI_PREDICATE (0xc << 23) |
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85 | #define GEN7_MI_OPCODE_MI_URB_CLEAR (0x19 << 23) |
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86 | #define GEN75_MI_OPCODE_MI_MATH (0x1a << 23) |
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87 | #define GEN6_MI_OPCODE_MI_STORE_DATA_IMM (0x20 << 23) |
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88 | #define GEN6_MI_OPCODE_MI_LOAD_REGISTER_IMM (0x22 << 23) |
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89 | #define GEN6_MI_OPCODE_MI_STORE_REGISTER_MEM (0x24 << 23) |
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90 | #define GEN6_MI_OPCODE_MI_FLUSH_DW (0x26 << 23) |
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91 | #define GEN6_MI_OPCODE_MI_REPORT_PERF_COUNT (0x28 << 23) |
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92 | #define GEN7_MI_OPCODE_MI_LOAD_REGISTER_MEM (0x29 << 23) |
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93 | #define GEN75_MI_OPCODE_MI_LOAD_REGISTER_REG (0x2a << 23) |
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94 | #define GEN75_MI_OPCODE_MI_LOAD_URB_MEM (0x2c << 23) |
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95 | #define GEN75_MI_OPCODE_MI_STORE_URB_MEM (0x2d << 23) |
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96 | #define GEN6_MI_OPCODE_MI_BATCH_BUFFER_START (0x31 << 23) |
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97 | #define GEN6_MI_LENGTH__MASK 0x0000003f |
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98 | #define GEN6_MI_LENGTH__SHIFT 0 |
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99 | #define GEN6_MI_NOOP__SIZE 1 |
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100 | |||
101 | #define GEN75_MI_SET_PREDICATE__SIZE 1 |
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102 | #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE__MASK 0x00000003 |
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103 | #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE__SHIFT 0 |
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104 | #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ALWAYS 0x0 |
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105 | #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ON_CLEAR 0x1 |
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106 | #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_ON_SET 0x2 |
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107 | #define GEN75_MI_SET_PREDICATE_DW0_PREDICATE_DISABLE 0x3 |
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108 | |||
109 | #define GEN75_MI_RS_CONTROL__SIZE 1 |
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110 | #define GEN75_MI_RS_CONTROL_DW0_ENABLE (0x1 << 0) |
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111 | |||
112 | #define GEN75_MI_URB_ATOMIC_ALLOC__SIZE 1 |
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113 | #define GEN75_MI_URB_ATOMIC_ALLOC_DW0_OFFSET__MASK 0x000ff000 |
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114 | #define GEN75_MI_URB_ATOMIC_ALLOC_DW0_OFFSET__SHIFT 12 |
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115 | #define GEN75_MI_URB_ATOMIC_ALLOC_DW0_SIZE__MASK 0x000001ff |
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116 | #define GEN75_MI_URB_ATOMIC_ALLOC_DW0_SIZE__SHIFT 0 |
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117 | |||
118 | #define GEN6_MI_BATCH_BUFFER_END__SIZE 1 |
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119 | |||
120 | #define GEN7_MI_PREDICATE__SIZE 1 |
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121 | #define GEN7_MI_PREDICATE_DW0_LOADOP__MASK 0x000000c0 |
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122 | #define GEN7_MI_PREDICATE_DW0_LOADOP__SHIFT 6 |
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123 | #define GEN7_MI_PREDICATE_DW0_LOADOP_KEEP (0x0 << 6) |
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124 | #define GEN7_MI_PREDICATE_DW0_LOADOP_LOAD (0x2 << 6) |
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125 | #define GEN7_MI_PREDICATE_DW0_LOADOP_LOADINV (0x3 << 6) |
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126 | #define GEN7_MI_PREDICATE_DW0_COMBINEOP__MASK 0x00000018 |
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127 | #define GEN7_MI_PREDICATE_DW0_COMBINEOP__SHIFT 3 |
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128 | #define GEN7_MI_PREDICATE_DW0_COMBINEOP_SET (0x0 << 3) |
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129 | #define GEN7_MI_PREDICATE_DW0_COMBINEOP_AND (0x1 << 3) |
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130 | #define GEN7_MI_PREDICATE_DW0_COMBINEOP_OR (0x2 << 3) |
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131 | #define GEN7_MI_PREDICATE_DW0_COMBINEOP_XOR (0x3 << 3) |
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132 | #define GEN7_MI_PREDICATE_DW0_COMPAREOP__MASK 0x00000003 |
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133 | #define GEN7_MI_PREDICATE_DW0_COMPAREOP__SHIFT 0 |
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134 | #define GEN7_MI_PREDICATE_DW0_COMPAREOP_TRUE 0x0 |
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135 | #define GEN7_MI_PREDICATE_DW0_COMPAREOP_FALSE 0x1 |
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136 | #define GEN7_MI_PREDICATE_DW0_COMPAREOP_SRCS_EQUAL 0x2 |
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137 | #define GEN7_MI_PREDICATE_DW0_COMPAREOP_DELTAS_EQUAL 0x3 |
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138 | |||
139 | #define GEN7_MI_URB_CLEAR__SIZE 2 |
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140 | |||
141 | #define GEN7_MI_URB_CLEAR_DW1_LENGTH__MASK 0x3fff0000 |
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142 | #define GEN7_MI_URB_CLEAR_DW1_LENGTH__SHIFT 16 |
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143 | #define GEN7_MI_URB_CLEAR_DW1_OFFSET__MASK 0x00007fff |
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144 | #define GEN7_MI_URB_CLEAR_DW1_OFFSET__SHIFT 0 |
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145 | |||
146 | #define GEN75_MI_MATH__SIZE 65 |
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147 | |||
148 | #define GEN75_MI_MATH_DW_OP__MASK 0xfff00000 |
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149 | #define GEN75_MI_MATH_DW_OP__SHIFT 20 |
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150 | #define GEN75_MI_MATH_DW_SRC1__MASK 0x000ffc00 |
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151 | #define GEN75_MI_MATH_DW_SRC1__SHIFT 10 |
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152 | #define GEN75_MI_MATH_DW_SRC2__MASK 0x000007ff |
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153 | #define GEN75_MI_MATH_DW_SRC2__SHIFT 0 |
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154 | |||
155 | #define GEN6_MI_STORE_DATA_IMM__SIZE 6 |
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156 | #define GEN6_MI_STORE_DATA_IMM_DW0_USE_GGTT (0x1 << 22) |
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157 | |||
158 | |||
159 | #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__MASK 0xfffffffc |
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160 | #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHIFT 2 |
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161 | #define GEN6_MI_STORE_DATA_IMM_DW2_ADDR__SHR 2 |
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162 | |||
163 | |||
164 | |||
165 | |||
166 | #define GEN6_MI_LOAD_REGISTER_IMM__SIZE 3 |
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167 | #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__MASK 0x00000f00 |
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168 | #define GEN6_MI_LOAD_REGISTER_IMM_DW0_WRITE_DISABLES__SHIFT 8 |
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169 | |||
170 | #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__MASK 0x007ffffc |
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171 | #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHIFT 2 |
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172 | #define GEN6_MI_LOAD_REGISTER_IMM_DW1_REG__SHR 2 |
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173 | |||
174 | |||
175 | #define GEN6_MI_STORE_REGISTER_MEM__SIZE 4 |
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176 | #define GEN6_MI_STORE_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22) |
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177 | #define GEN75_MI_STORE_REGISTER_MEM_DW0_PREDICATE_ENABLE (0x1 << 21) |
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178 | |||
179 | #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__MASK 0x007ffffc |
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180 | #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHIFT 2 |
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181 | #define GEN6_MI_STORE_REGISTER_MEM_DW1_REG__SHR 2 |
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182 | |||
183 | #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__MASK 0xfffffffc |
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184 | #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHIFT 2 |
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185 | #define GEN6_MI_STORE_REGISTER_MEM_DW2_ADDR__SHR 2 |
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186 | |||
187 | |||
188 | #define GEN6_MI_FLUSH_DW__SIZE 4 |
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189 | |||
190 | |||
191 | |||
192 | |||
193 | #define GEN6_MI_REPORT_PERF_COUNT__SIZE 3 |
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194 | |||
195 | #define GEN6_MI_REPORT_PERF_COUNT_DW1_CORE_MODE_ENABLE (0x1 << 4) |
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196 | #define GEN6_MI_REPORT_PERF_COUNT_DW1_USE_GGTT (0x1 << 0) |
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197 | #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__MASK 0xffffffc0 |
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198 | #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHIFT 6 |
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199 | #define GEN6_MI_REPORT_PERF_COUNT_DW1_ADDR__SHR 6 |
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200 | |||
201 | |||
202 | #define GEN7_MI_LOAD_REGISTER_MEM__SIZE 4 |
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203 | #define GEN7_MI_LOAD_REGISTER_MEM_DW0_USE_GGTT (0x1 << 22) |
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204 | #define GEN7_MI_LOAD_REGISTER_MEM_DW0_ASYNC_MODE_ENABLE (0x1 << 21) |
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205 | |||
206 | #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__MASK 0x007ffffc |
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207 | #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHIFT 2 |
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208 | #define GEN7_MI_LOAD_REGISTER_MEM_DW1_REG__SHR 2 |
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209 | |||
210 | #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__MASK 0xfffffffc |
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211 | #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHIFT 2 |
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212 | #define GEN7_MI_LOAD_REGISTER_MEM_DW2_ADDR__SHR 2 |
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213 | |||
214 | |||
215 | #define GEN75_MI_LOAD_REGISTER_REG__SIZE 3 |
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216 | |||
217 | #define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__MASK 0x007ffffc |
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218 | #define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__SHIFT 2 |
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219 | #define GEN75_MI_LOAD_REGISTER_REG_DW1_SRC_REG__SHR 2 |
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220 | |||
221 | #define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__MASK 0x007ffffc |
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222 | #define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHIFT 2 |
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223 | #define GEN75_MI_LOAD_REGISTER_REG_DW2_DST_REG__SHR 2 |
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224 | |||
225 | #define GEN75_MI_LOAD_URB_MEM__SIZE 4 |
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226 | |||
227 | #define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__MASK 0x00007ffc |
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228 | #define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__SHIFT 2 |
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229 | #define GEN75_MI_LOAD_URB_MEM_DW1_ADDR__SHR 2 |
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230 | |||
231 | #define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__MASK 0xffffffc0 |
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232 | #define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__SHIFT 6 |
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233 | #define GEN75_MI_LOAD_URB_MEM_DW2_ADDR__SHR 6 |
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234 | |||
235 | |||
236 | #define GEN75_MI_STORE_URB_MEM__SIZE 4 |
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237 | |||
238 | #define GEN75_MI_STORE_URB_MEM_DW1_ADDR__MASK 0x00007ffc |
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239 | #define GEN75_MI_STORE_URB_MEM_DW1_ADDR__SHIFT 2 |
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240 | #define GEN75_MI_STORE_URB_MEM_DW1_ADDR__SHR 2 |
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241 | |||
242 | #define GEN75_MI_STORE_URB_MEM_DW2_ADDR__MASK 0xffffffc0 |
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243 | #define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHIFT 6 |
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244 | #define GEN75_MI_STORE_URB_MEM_DW2_ADDR__SHR 6 |
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245 | |||
246 | |||
247 | #define GEN6_MI_BATCH_BUFFER_START__SIZE 3 |
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248 | #define GEN75_MI_BATCH_BUFFER_START_DW0_SECOND_LEVEL (0x1 << 22) |
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249 | #define GEN75_MI_BATCH_BUFFER_START_DW0_ADD_OFFSET_ENABLE (0x1 << 16) |
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250 | #define GEN75_MI_BATCH_BUFFER_START_DW0_PREDICATION_ENABLE (0x1 << 15) |
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251 | #define GEN75_MI_BATCH_BUFFER_START_DW0_NON_PRIVILEGED (0x1 << 13) |
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252 | #define GEN6_MI_BATCH_BUFFER_START_DW0_CLEAR_COMMAND_BUFFER (0x1 << 11) |
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253 | #define GEN6_MI_BATCH_BUFFER_START_DW0_USE_PPGTT (0x1 << 8) |
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254 | |||
255 | #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__MASK 0xfffffffc |
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256 | #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHIFT 2 |
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257 | #define GEN6_MI_BATCH_BUFFER_START_DW1_ADDR__SHR 2 |
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258 | |||
259 | |||
260 | |||
261 | #endif /* GEN_MI_XML */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |