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  1.  
  2. #define R300_TEST
  3.  
  4. #include "r5xx_regs.h"
  5.  
  6. #define RADEON_BUS_CNTL                 0x0030
  7. #       define RADEON_BUS_MASTER_DIS            (1 << 6)
  8.  
  9.  
  10. #define RADEON_SCRATCH_UMSK             0x0770
  11. #define RADEON_SCRATCH_ADDR             0x0774
  12.  
  13. #define RADEON_CP_ME_RAM_ADDR           0x07d4
  14. #define RADEON_CP_ME_RAM_RADDR          0x07d8
  15. #define RADEON_CP_ME_RAM_DATAH          0x07dc
  16. #define RADEON_CP_ME_RAM_DATAL          0x07e0
  17.  
  18. #define RADEON_AIC_CNTL                 0x01d0
  19. #define RADEON_PCIGART_TRANSLATE_EN      (1 << 0)
  20.  
  21.  
  22. #define RADEON_CP_RB_BASE               0x0700
  23. #define RADEON_CP_RB_CNTL               0x0704
  24. #       define RADEON_BUF_SWAP_32BIT            (2 << 16)
  25. #       define RADEON_RB_NO_UPDATE              (1 << 27)
  26. #define RADEON_CP_RB_RPTR_ADDR          0x070c
  27. #define RADEON_CP_RB_RPTR               0x0710
  28. #define RADEON_CP_RB_WPTR               0x0714
  29.  
  30. #define RADEON_CP_RB_WPTR_DELAY         0x0718
  31. #       define RADEON_PRE_WRITE_TIMER_SHIFT     0
  32. #       define RADEON_PRE_WRITE_LIMIT_SHIFT     23
  33.  
  34. #define RADEON_CP_IB_BASE               0x0738
  35.  
  36. #define RADEON_CP_CSQ_CNTL              0x0740
  37. #       define RADEON_CSQ_CNT_PRIMARY_MASK      (0xff << 0)
  38. #       define RADEON_CSQ_PRIDIS_INDDIS         (0 << 28)
  39. #       define RADEON_CSQ_PRIPIO_INDDIS         (1 << 28)
  40. #       define RADEON_CSQ_PRIBM_INDDIS          (2 << 28)
  41. #       define RADEON_CSQ_PRIPIO_INDBM          (3 << 28)
  42. #       define RADEON_CSQ_PRIBM_INDBM           (4 << 28)
  43. #       define RADEON_CSQ_PRIPIO_INDPIO         (15 << 28)
  44.  
  45. #define RADEON_ISYNC_CNTL               0x1724
  46. #       define RADEON_ISYNC_ANY2D_IDLE3D        (1 << 0)
  47. #       define RADEON_ISYNC_ANY3D_IDLE2D        (1 << 1)
  48. #       define RADEON_ISYNC_TRIG2D_IDLE3D       (1 << 2)
  49. #       define RADEON_ISYNC_TRIG3D_IDLE2D       (1 << 3)
  50. #       define RADEON_ISYNC_WAIT_IDLEGUI        (1 << 4)
  51. #       define RADEON_ISYNC_CPSCRATCH_IDLEGUI   (1 << 5)
  52.  
  53. #define R5XX_LOOP_COUNT 2000000
  54.  
  55. #include "microcode.h"
  56.  
  57. static Bool
  58. R5xxFIFOWaitLocal(CARD32 required)             //R100-R500
  59. {
  60.   int i;
  61.  
  62.   for (i = 0; i < R5XX_LOOP_COUNT; i++)
  63.     if (required <= (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK))
  64.             return TRUE;
  65.  
  66.   dbgprintf("%s: Timeout 0x%08X.\n", __func__,
  67.          (unsigned int) INREG(R5XX_RBBM_STATUS));
  68.   return FALSE;
  69. }
  70.  
  71. /*
  72.  * Flush all dirty data in the Pixel Cache to memory.
  73.  */
  74.  
  75. static Bool
  76. R5xx2DFlush()
  77. {
  78.     int i;
  79.  
  80.     MASKREG(R5XX_DSTCACHE_CTLSTAT,
  81.                 R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL);
  82.  
  83.     for (i = 0; i < R5XX_LOOP_COUNT; i++)
  84.       if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY))
  85.         return TRUE;
  86.  
  87.     dbgprintf("%s: Timeout 0x%08x.\n", __func__,
  88.          (unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT));
  89.     return FALSE;
  90. }
  91.  
  92. static Bool
  93. R5xx2DIdleLocal()                                //R100-R500
  94. {
  95.     int i;
  96.  
  97.       /* wait for fifo to clear */
  98.     for (i = 0; i < R5XX_LOOP_COUNT; i++)
  99.       if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK))
  100.         break;
  101.  
  102.     if (i == R5XX_LOOP_COUNT) {
  103.       dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));
  104.       return FALSE;
  105.     }
  106.  
  107.       /* wait for engine to go idle */
  108.     for (i = 0; i < R5XX_LOOP_COUNT; i++) {
  109.       if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) {
  110.         R5xx2DFlush();
  111.         return TRUE;
  112.       }
  113.     }
  114.     dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));
  115.     return FALSE;
  116.  
  117. }
  118.  
  119. static void
  120. R5xx2DReset()
  121. {
  122.     CARD32 save, tmp;
  123.  
  124.       /* The following RBBM_SOFT_RESET sequence can help un-wedge
  125.        * an R300 after the command processor got stuck. */
  126.     save = INREG(R5XX_RBBM_SOFT_RESET);
  127.     tmp = save | R5XX_SOFT_RESET_CP |
  128.       R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_SE |
  129.       R5XX_SOFT_RESET_RE | R5XX_SOFT_RESET_PP |
  130.       R5XX_SOFT_RESET_E2 | R5XX_SOFT_RESET_RB;
  131.     OUTREG(R5XX_RBBM_SOFT_RESET, tmp);
  132.  
  133.     INREG(R5XX_RBBM_SOFT_RESET);
  134.     tmp &= ~(R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI |
  135.          R5XX_SOFT_RESET_SE | R5XX_SOFT_RESET_RE |
  136.          R5XX_SOFT_RESET_PP | R5XX_SOFT_RESET_E2 |
  137.          R5XX_SOFT_RESET_RB);
  138.     OUTREG(R5XX_RBBM_SOFT_RESET, tmp);
  139.  
  140.     INREG(R5XX_RBBM_SOFT_RESET);
  141.     OUTREG(R5XX_RBBM_SOFT_RESET, save);
  142.     INREG(R5XX_RBBM_SOFT_RESET);
  143.  
  144.     R5xx2DFlush();
  145.  
  146.       /* Soft resetting HDP thru RBBM_SOFT_RESET register can cause some
  147.        * unexpected behaviour on some machines.  Here we use
  148.        * R5XX_HOST_PATH_CNTL to reset it. */
  149.     save = INREG(R5XX_HOST_PATH_CNTL);
  150.  
  151.     tmp = INREG(R5XX_RBBM_SOFT_RESET);
  152.     tmp |= R5XX_SOFT_RESET_CP | R5XX_SOFT_RESET_HI | R5XX_SOFT_RESET_E2;
  153.     OUTREG(R5XX_RBBM_SOFT_RESET, tmp);
  154.  
  155.     INREG(R5XX_RBBM_SOFT_RESET);
  156.     OUTREG(R5XX_RBBM_SOFT_RESET, 0);
  157.  
  158.     MASKREG(R5XX_RB2D_DSTCACHE_MODE,
  159.                R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE,
  160.                R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE);
  161.  
  162.     OUTREG(R5XX_HOST_PATH_CNTL, save | R5XX_HDP_SOFT_RESET);
  163.     INREG(R5XX_HOST_PATH_CNTL);
  164.     OUTREG(R5XX_HOST_PATH_CNTL, save);
  165. }
  166.  
  167. void
  168. R5xx2DSetup()
  169. {
  170.  
  171.     /* Setup engine location. This shouldn't be necessary since we
  172.     * set them appropriately before any accel ops, but let's avoid
  173.      * random bogus DMA in case we inadvertently trigger the engine
  174.      * in the wrong place (happened). */
  175.     R5xxFIFOWaitLocal(2);
  176.     OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);
  177.     OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset);
  178.  
  179.     R5xxFIFOWaitLocal(1);
  180.     MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);
  181.  
  182.     OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl);
  183.  
  184.     R5xxFIFOWaitLocal(1);
  185.     OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT,
  186.            R5XX_DEFAULT_SC_RIGHT_MAX | R5XX_DEFAULT_SC_BOTTOM_MAX);
  187.     R5xxFIFOWaitLocal(1);
  188.     OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control |
  189.            R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR);
  190.  
  191.     R5xxFIFOWaitLocal(5);
  192.     OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF);
  193.     OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000);
  194.     OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF);
  195.     OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000);
  196.     OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF);
  197.  
  198.     R5xx2DIdleLocal();
  199. }
  200.  
  201. void R5xxFIFOWait(CARD32 required)
  202. {
  203.     if (!R5xxFIFOWaitLocal(required)) {
  204.       R5xx2DReset();
  205.       R5xx2DSetup();
  206.     }
  207. }
  208.  
  209. void R5xx2DIdle()
  210. {
  211.     if (!R5xx2DIdleLocal()) {
  212.       R5xx2DReset();
  213.       R5xx2DSetup();
  214.     }
  215. }
  216.  
  217. static void load_microcode()
  218. {
  219.   u32 ifl;
  220.   int i;
  221.  
  222.   ifl = safe_cli();
  223.  
  224.   OUTREG(RADEON_CP_ME_RAM_ADDR,0);
  225.  
  226.   R5xx2DIdleLocal();
  227.  
  228.   switch(rhd.ChipSet)
  229.   {
  230.     case RHD_R300:
  231.     case RHD_R350:
  232.     case RHD_RV350:
  233.     case RHD_RV370:
  234.     case RHD_RV380:
  235.       dbgprintf("Loading R300 microcode\n");
  236.       for (i = 0; i < 256; i++)
  237.       {
  238.         OUTREG(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
  239.         OUTREG(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
  240.       }
  241.       break;
  242.  
  243.     case RHD_RV505:
  244.     case RHD_RV515:
  245.     case RHD_RV516:
  246.     case RHD_R520:
  247.     case RHD_RV530:
  248.     case RHD_RV535:
  249.     case RHD_RV550:
  250.     case RHD_RV560:
  251.     case RHD_RV570:
  252.     case RHD_R580:
  253.       dbgprintf("Loading R500 microcode\n");
  254.       for (i = 0; i < 256; i++)
  255.       {
  256.         OUTREG(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
  257.         OUTREG(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
  258.       }
  259.   }
  260.   safe_sti(ifl);
  261. };
  262.  
  263.  
  264. void  R5xx2DInit()
  265. {
  266.     u32 base;
  267.  
  268. #ifdef R300_TEST
  269.     rhd.displayWidth  = 800;
  270.     rhd.displayHeight = 600;
  271. #else
  272.     rhd.displayWidth  = INREG(D1GRPH_X_END);
  273.     rhd.displayHeight = INREG(D1GRPH_Y_END);
  274. #endif
  275.  
  276.     rhd.__xmin = 0;
  277.     rhd.__ymin = 0;
  278.     rhd.__xmax = rhd.displayWidth  - 1;
  279.     rhd.__ymax = rhd.displayHeight - 1;
  280.  
  281.     clip.xmin = 0;
  282.     clip.ymin = 0;
  283.     clip.xmax = rhd.displayWidth  - 1;
  284.     clip.ymax = rhd.displayHeight - 1;
  285.  
  286.     dbgprintf("width  %d \n", rhd.displayWidth);
  287.     dbgprintf("height %d \n", rhd.displayHeight);
  288.  
  289.     rhd.gui_control = (R5XX_DATATYPE_ARGB8888 << R5XX_GMC_DST_DATATYPE_SHIFT) |
  290.                        R5XX_GMC_CLR_CMP_CNTL_DIS | R5XX_GMC_DST_PITCH_OFFSET_CNTL;
  291.  
  292.     dbgprintf("gui_control %x \n", rhd.gui_control);
  293.  
  294.     rhd.surface_cntl = 0;
  295.     rhd.dst_pitch_offset = (((rhd.displayWidth * 4) / 64) << 22) |
  296.                             ((rhd.FbIntAddress + rhd.FbScanoutStart) >> 10);
  297.  
  298.     dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset);
  299.  
  300.     MASKREG(R5XX_GB_TILE_CONFIG, 0, R5XX_ENABLE_TILING);
  301.     OUTREG (R5XX_WAIT_UNTIL, R5XX_WAIT_2D_IDLECLEAN | R5XX_WAIT_3D_IDLECLEAN);
  302.     MASKREG(R5XX_DST_PIPE_CONFIG, R5XX_PIPE_AUTO_CONFIG, R5XX_PIPE_AUTO_CONFIG);
  303.     MASKREG(R5XX_RB2D_DSTCACHE_MODE,
  304.             R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE,
  305.             R5XX_RB2D_DC_AUTOFLUSH_ENABLE | R5XX_RB2D_DC_DISABLE_IGNORE_PE);
  306.  
  307.  
  308.     R5xx2DReset();
  309.     R5xx2DSetup();
  310.  
  311.     MASKREG( RADEON_AIC_CNTL,0, RADEON_PCIGART_TRANSLATE_EN);
  312.  
  313.     load_microcode();
  314.  
  315.     rhd.ring_base = CreateRingBuffer(0x8000, PG_SW | PG_NOCACHE);
  316.     dbgprintf("create cp ring buffer %x\n", rhd.ring_base);
  317.     base = GetPgAddr(rhd.ring_base);
  318.  
  319.     OUTREG(RADEON_CP_RB_BASE, base);
  320.     dbgprintf("ring base %x\n", base);
  321.  
  322.     OUTREG(RADEON_CP_RB_WPTR_DELAY, 0);
  323.  
  324.     rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR);
  325.     OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp);
  326.  
  327.     OUTREG(RADEON_CP_RB_RPTR_ADDR, 0); // ring buffer read pointer no update
  328.  
  329.     OUTREG(RADEON_CP_RB_CNTL, RADEON_RB_NO_UPDATE | 12);
  330.     OUTREG(RADEON_SCRATCH_UMSK, 0);          // no scratch update
  331.  
  332.     MASKREG(RADEON_BUS_CNTL,0,RADEON_BUS_MASTER_DIS);
  333.  
  334.     R5xx2DIdleLocal();
  335.  
  336.     OUTREG(RADEON_ISYNC_CNTL, RADEON_ISYNC_ANY2D_IDLE3D |
  337.                               RADEON_ISYNC_ANY3D_IDLE2D |
  338.                               RADEON_ISYNC_WAIT_IDLEGUI |
  339.                               RADEON_ISYNC_CPSCRATCH_IDLEGUI);
  340.  
  341.     OUTREG(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);    // run
  342.  
  343.  
  344.  //   OUTREG(D1CUR_SIZE, (31<<16)|31);
  345.  //   OUTREG(D1CUR_CONTROL, 0x300);
  346. }
  347.  
  348.  
  349.  
  350.