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  1.  
  2. #define R300_TEST
  3.  
  4. #include "r5xx_regs.h"
  5.  
  6.  
  7. #define R5XX_LOOP_COUNT 2000000
  8.  
  9. #define RADEON_CLOCK_CNTL_DATA              0x000c
  10.  
  11. #define RADEON_CLOCK_CNTL_INDEX             0x0008
  12. #       define RADEON_PLL_WR_EN             (1 << 7)
  13. #       define RADEON_PLL_DIV_SEL           (3 << 8)
  14. #       define RADEON_PLL2_DIV_SEL_MASK     ~(3 << 8)
  15.  
  16. #define RADEON_MCLK_CNTL                    0x0012 /* PLL */
  17. #       define RADEON_FORCEON_MCLKA         (1 << 16)
  18. #       define RADEON_FORCEON_MCLKB         (1 << 17)
  19. #       define RADEON_FORCEON_YCLKA         (1 << 18)
  20. #       define RADEON_FORCEON_YCLKB         (1 << 19)
  21. #       define RADEON_FORCEON_MC            (1 << 20)
  22. #       define RADEON_FORCEON_AIC           (1 << 21)
  23. #       define R300_DISABLE_MC_MCLKA        (1 << 21)
  24. #       define R300_DISABLE_MC_MCLKB        (1 << 21)
  25.  
  26.  
  27.  
  28.  
  29. /*
  30.  * Flush all dirty data in the Pixel Cache to memory.
  31.  */
  32.  
  33. static Bool
  34. R5xx2DFlush()
  35. {
  36.     int i;
  37.  
  38.     MASKREG(R5XX_DSTCACHE_CTLSTAT,
  39.                 R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL);
  40.  
  41.     for (i = 0; i < R5XX_LOOP_COUNT; i++)
  42.       if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY))
  43.         return TRUE;
  44.  
  45.     dbgprintf("%s: Timeout 0x%08x.\n", __func__,
  46.          (unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT));
  47.     return FALSE;
  48. }
  49.  
  50. static Bool
  51. R5xx2DIdleLocal()                                //R100-R500
  52. {
  53.     int i;
  54.  
  55.       /* wait for fifo to clear */
  56.     for (i = 0; i < R5XX_LOOP_COUNT; i++)
  57.       if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK))
  58.         break;
  59.  
  60.     if (i == R5XX_LOOP_COUNT) {
  61.       dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));
  62.       return FALSE;
  63.     }
  64.  
  65.       /* wait for engine to go idle */
  66.     for (i = 0; i < R5XX_LOOP_COUNT; i++) {
  67.       if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) {
  68.         R5xx2DFlush();
  69.         return TRUE;
  70.       }
  71.     }
  72.     dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));
  73.     return FALSE;
  74.  
  75. }
  76.  
  77.  
  78. void
  79. R5xx2DSetup()
  80. {
  81.  
  82.     /* Setup engine location. This shouldn't be necessary since we
  83.     * set them appropriately before any accel ops, but let's avoid
  84.      * random bogus DMA in case we inadvertently trigger the engine
  85.      * in the wrong place (happened). */
  86.     R5xxFIFOWaitLocal(2);
  87.     OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);
  88.     OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset);
  89.  
  90.     R5xxFIFOWaitLocal(1);
  91.     MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);
  92.  
  93.     OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl);
  94.  
  95.     R5xxFIFOWaitLocal(3);
  96.     OUTREG(R5XX_SC_TOP_LEFT, 0);
  97.     OUTREG(R5XX_SC_BOTTOM_RIGHT,
  98.            RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
  99.     OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT,
  100.            RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
  101.  
  102.     R5xxFIFOWaitLocal(1);
  103. //    OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control |
  104. //           R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR);
  105.     OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM);
  106.  
  107.     R5xxFIFOWaitLocal(5);
  108.     OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF);
  109.     OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000);
  110.     OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF);
  111.     OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000);
  112.     OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF);
  113.  
  114.     R5xx2DIdleLocal();
  115. }
  116.  
  117. void R5xxFIFOWait(u32_t required)
  118. {
  119.     if (!R5xxFIFOWaitLocal(required)) {
  120.  //     R5xx2DReset();
  121.       R5xx2DSetup();
  122.     }
  123. }
  124.  
  125. void R5xx2DIdle()
  126. {
  127.     if (!R5xx2DIdleLocal()) {
  128.   //    R5xx2DReset();
  129.       R5xx2DSetup();
  130.     }
  131. }
  132.  
  133.  
  134.  
  135. void  R5xx2DInit()
  136. {
  137.     u32_t base;
  138.     int screensize;
  139.     int screenpitch;
  140.  
  141.     screensize = GetScreenSize();
  142.     screenpitch = GetScreenPitch();
  143.  
  144.     rhd.displayWidth  = screensize >> 16;
  145.     rhd.displayHeight = screensize & 0xFFFF;
  146.  
  147.     rhd.__xmin = 0;
  148.     rhd.__ymin = 0;
  149.     rhd.__xmax = rhd.displayWidth  - 1;
  150.     rhd.__ymax = rhd.displayHeight - 1;
  151.  
  152.     clip.xmin = 0;
  153.     clip.ymin = 0;
  154.     clip.xmax = rhd.displayWidth  - 1;
  155.     clip.ymax = rhd.displayHeight - 1;
  156.  
  157.     dbgprintf("screen width  %d height %d\n",
  158.                rhd.displayWidth, rhd.displayHeight);
  159.  
  160.     rhd.gui_control = ((6 << RADEON_GMC_DST_DATATYPE_SHIFT)
  161.                       | RADEON_GMC_CLR_CMP_CNTL_DIS
  162.                       | RADEON_GMC_DST_PITCH_OFFSET_CNTL);
  163.  
  164.     dbgprintf("gui_control %x \n", rhd.gui_control);
  165.  
  166.     rhd.surface_cntl = 0;
  167.  
  168.     rhd.dst_pitch_offset = (((rhd.displayWidth * 4 / 64)<< 22) |
  169.                                (rhd.fbLocation  >> 10));
  170.  
  171.  
  172.     dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset);
  173.  
  174.     scr_pixmap.width  = rhd.displayWidth;
  175.     scr_pixmap.height = rhd.displayHeight;
  176.     scr_pixmap.format = PICT_a8r8g8b8;
  177.     scr_pixmap.pitch  = rhd.displayWidth * 4     ;//screenpitch;
  178.     scr_pixmap.local  = (void*)rhd.fbLocation;
  179.     scr_pixmap.pitch_offset =  rhd.dst_pitch_offset;
  180.     scr_pixmap.mapped = (void*)0;
  181.  
  182.     R5xxFIFOWaitLocal(2);
  183.     OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);
  184.     OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset);
  185.  
  186.     R5xxFIFOWaitLocal(1);
  187.     MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);
  188.  
  189.     OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl);
  190.  
  191. #if R300_PIO
  192. #else
  193.     init_cp(&rhd);
  194. #endif
  195.  
  196.     R5xx2DSetup();
  197.  
  198. }
  199.  
  200.  
  201.  
  202.