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  1.  
  2. #define R300_TEST
  3.  
  4. #include "r5xx_regs.h"
  5.  
  6. #define RADEON_BUS_CNTL                 0x0030
  7. #       define RADEON_BUS_MASTER_DIS            (1 << 6)
  8.  
  9.  
  10. #define RADEON_SCRATCH_UMSK             0x0770
  11. #define RADEON_SCRATCH_ADDR             0x0774
  12.  
  13. #define RADEON_CP_ME_RAM_ADDR           0x07d4
  14. #define RADEON_CP_ME_RAM_RADDR          0x07d8
  15. #define RADEON_CP_ME_RAM_DATAH          0x07dc
  16. #define RADEON_CP_ME_RAM_DATAL          0x07e0
  17.  
  18. #define RADEON_AIC_CNTL                 0x01d0
  19. #define RADEON_PCIGART_TRANSLATE_EN      (1 << 0)
  20.  
  21.  
  22. #define RADEON_CP_RB_BASE               0x0700
  23. #define RADEON_CP_RB_CNTL               0x0704
  24. #       define RADEON_BUF_SWAP_32BIT            (2 << 16)
  25. #       define RADEON_RB_NO_UPDATE              (1 << 27)
  26. #define RADEON_CP_RB_RPTR_ADDR          0x070c
  27. #define RADEON_CP_RB_RPTR               0x0710
  28. #define RADEON_CP_RB_WPTR               0x0714
  29.  
  30. #define RADEON_CP_RB_WPTR_DELAY         0x0718
  31. #       define RADEON_PRE_WRITE_TIMER_SHIFT     0
  32. #       define RADEON_PRE_WRITE_LIMIT_SHIFT     23
  33.  
  34. #define RADEON_CP_IB_BASE               0x0738
  35.  
  36. #define RADEON_CP_CSQ_CNTL              0x0740
  37. #       define RADEON_CSQ_CNT_PRIMARY_MASK      (0xff << 0)
  38. #       define RADEON_CSQ_PRIDIS_INDDIS         (0 << 28)
  39. #       define RADEON_CSQ_PRIPIO_INDDIS         (1 << 28)
  40. #       define RADEON_CSQ_PRIBM_INDDIS          (2 << 28)
  41. #       define RADEON_CSQ_PRIPIO_INDBM          (3 << 28)
  42. #       define RADEON_CSQ_PRIBM_INDBM           (4 << 28)
  43. #       define RADEON_CSQ_PRIPIO_INDPIO         (15 << 28)
  44.  
  45. #define RADEON_ISYNC_CNTL               0x1724
  46. #       define RADEON_ISYNC_ANY2D_IDLE3D        (1 << 0)
  47. #       define RADEON_ISYNC_ANY3D_IDLE2D        (1 << 1)
  48. #       define RADEON_ISYNC_TRIG2D_IDLE3D       (1 << 2)
  49. #       define RADEON_ISYNC_TRIG3D_IDLE2D       (1 << 3)
  50. #       define RADEON_ISYNC_WAIT_IDLEGUI        (1 << 4)
  51. #       define RADEON_ISYNC_CPSCRATCH_IDLEGUI   (1 << 5)
  52.  
  53. #define R5XX_LOOP_COUNT 2000000
  54.  
  55. #define RADEON_CLOCK_CNTL_DATA              0x000c
  56.  
  57. #define RADEON_CLOCK_CNTL_INDEX             0x0008
  58. #       define RADEON_PLL_WR_EN             (1 << 7)
  59. #       define RADEON_PLL_DIV_SEL           (3 << 8)
  60. #       define RADEON_PLL2_DIV_SEL_MASK     ~(3 << 8)
  61.  
  62. #define RADEON_MCLK_CNTL                    0x0012 /* PLL */
  63. #       define RADEON_FORCEON_MCLKA         (1 << 16)
  64. #       define RADEON_FORCEON_MCLKB         (1 << 17)
  65. #       define RADEON_FORCEON_YCLKA         (1 << 18)
  66. #       define RADEON_FORCEON_YCLKB         (1 << 19)
  67. #       define RADEON_FORCEON_MC            (1 << 20)
  68. #       define RADEON_FORCEON_AIC           (1 << 21)
  69. #       define R300_DISABLE_MC_MCLKA        (1 << 21)
  70. #       define R300_DISABLE_MC_MCLKB        (1 << 21)
  71.  
  72.  
  73.  
  74.  
  75. /*
  76.  * Flush all dirty data in the Pixel Cache to memory.
  77.  */
  78.  
  79. static Bool
  80. R5xx2DFlush()
  81. {
  82.     int i;
  83.  
  84.     MASKREG(R5XX_DSTCACHE_CTLSTAT,
  85.                 R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL);
  86.  
  87.     for (i = 0; i < R5XX_LOOP_COUNT; i++)
  88.       if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY))
  89.         return TRUE;
  90.  
  91.     dbgprintf("%s: Timeout 0x%08x.\n", __func__,
  92.          (unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT));
  93.     return FALSE;
  94. }
  95.  
  96. static Bool
  97. R5xx2DIdleLocal()                                //R100-R500
  98. {
  99.     int i;
  100.  
  101.       /* wait for fifo to clear */
  102.     for (i = 0; i < R5XX_LOOP_COUNT; i++)
  103.       if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK))
  104.         break;
  105.  
  106.     if (i == R5XX_LOOP_COUNT) {
  107.       dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));
  108.       return FALSE;
  109.     }
  110.  
  111.       /* wait for engine to go idle */
  112.     for (i = 0; i < R5XX_LOOP_COUNT; i++) {
  113.       if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) {
  114.         R5xx2DFlush();
  115.         return TRUE;
  116.       }
  117.     }
  118.     dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));
  119.     return FALSE;
  120.  
  121. }
  122.  
  123.  
  124. void
  125. R5xx2DSetup()
  126. {
  127.  
  128.     /* Setup engine location. This shouldn't be necessary since we
  129.     * set them appropriately before any accel ops, but let's avoid
  130.      * random bogus DMA in case we inadvertently trigger the engine
  131.      * in the wrong place (happened). */
  132.     R5xxFIFOWaitLocal(2);
  133.     OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);
  134.     OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset);
  135.  
  136.     R5xxFIFOWaitLocal(1);
  137.     MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);
  138.  
  139.     OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl);
  140.  
  141.     R5xxFIFOWaitLocal(3);
  142.     OUTREG(R5XX_SC_TOP_LEFT, 0);
  143.     OUTREG(R5XX_SC_BOTTOM_RIGHT,
  144.            RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
  145.     OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT,
  146.            RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX);
  147.  
  148.     R5xxFIFOWaitLocal(1);
  149. //    OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control |
  150. //           R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR);
  151.     OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM);
  152.  
  153.     R5xxFIFOWaitLocal(5);
  154.     OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF);
  155.     OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000);
  156.     OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF);
  157.     OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000);
  158.     OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF);
  159.  
  160.     R5xx2DIdleLocal();
  161. }
  162.  
  163. void R5xxFIFOWait(u32_t required)
  164. {
  165.     if (!R5xxFIFOWaitLocal(required)) {
  166.  //     R5xx2DReset();
  167.       R5xx2DSetup();
  168.     }
  169. }
  170.  
  171. void R5xx2DIdle()
  172. {
  173.     if (!R5xx2DIdleLocal()) {
  174.   //    R5xx2DReset();
  175.       R5xx2DSetup();
  176.     }
  177. }
  178.  
  179.  
  180.  
  181. void  R5xx2DInit()
  182. {
  183.     u32_t base;
  184.     int screensize;
  185.     int screenpitch;
  186.  
  187.     screensize = GetScreenSize();
  188.     screenpitch = GetScreenPitch();
  189.  
  190.     rhd.displayWidth  = screensize >> 16;
  191.     rhd.displayHeight = screensize & 0xFFFF;
  192.  
  193.     rhd.__xmin = 0;
  194.     rhd.__ymin = 0;
  195.     rhd.__xmax = rhd.displayWidth  - 1;
  196.     rhd.__ymax = rhd.displayHeight - 1;
  197.  
  198.     clip.xmin = 0;
  199.     clip.ymin = 0;
  200.     clip.xmax = rhd.displayWidth  - 1;
  201.     clip.ymax = rhd.displayHeight - 1;
  202.  
  203.     dbgprintf("screen width  %d height %d\n",
  204.                rhd.displayWidth, rhd.displayHeight);
  205.  
  206.     rhd.gui_control = ((6 << RADEON_GMC_DST_DATATYPE_SHIFT)
  207.                       | RADEON_GMC_CLR_CMP_CNTL_DIS
  208.                       | RADEON_GMC_DST_PITCH_OFFSET_CNTL);
  209.  
  210.     dbgprintf("gui_control %x \n", rhd.gui_control);
  211.  
  212.     rhd.surface_cntl = 0;
  213. //    rhd.dst_pitch_offset = ((screenpitch / 64) << 22) | (rhd.fbLocation >> 10);
  214.  
  215.     rhd.dst_pitch_offset = (((rhd.displayWidth * 4 / 64)<< 22) |
  216.                                (rhd.fbLocation  >> 10));
  217.  
  218.  
  219.     dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset);
  220.  
  221.     scr_pixmap.width  = rhd.displayWidth;
  222.     scr_pixmap.height = rhd.displayHeight;
  223.     scr_pixmap.format = PICT_a8r8g8b8;
  224.     scr_pixmap.pitch  = screenpitch;
  225.     scr_pixmap.local  = (void*)rhd.fbLocation;
  226.     scr_pixmap.pitch_offset =  rhd.dst_pitch_offset;
  227.     scr_pixmap.mapped = (void*)0;
  228.  
  229.     R5xxFIFOWaitLocal(2);
  230.     OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);
  231.     OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset);
  232.  
  233.     R5xxFIFOWaitLocal(1);
  234.     MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN);
  235.  
  236.     OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl);
  237.  
  238. #if R300_PIO
  239. #else
  240.     init_cp(&rhd);
  241. #endif
  242.  
  243.     R5xx2DSetup();
  244.  
  245. }
  246.  
  247.  
  248.  
  249.