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  1.  
  2. SymTabRec RHDChipsets[] = {
  3.     /* R500 */
  4.     { RHD_RV505, "RV505" },
  5.     { RHD_RV515, "RV515" },
  6.     { RHD_RV516, "RV516" },
  7.     { RHD_R520,  "R520" },
  8.     { RHD_RV530, "RV530" },
  9.     { RHD_RV535, "RV535" },
  10.     { RHD_RV550, "RV550" },
  11.     { RHD_RV560, "RV560" },
  12.     { RHD_RV570, "RV570" },
  13.     { RHD_R580,  "R580" },
  14.     /* R500 Mobility */
  15.     { RHD_M52,   "M52" },
  16.     { RHD_M54,   "M54" },
  17.     { RHD_M56,   "M56" },
  18.     { RHD_M58,   "M58" },
  19.     { RHD_M62,   "M62" },
  20.     { RHD_M64,   "M64" },
  21.     { RHD_M66,   "M66" },
  22.     { RHD_M68,   "M68" },
  23.     { RHD_M71,   "M71" },
  24.     /* R500 integrated */
  25.     { RHD_RS600, "RS600" },
  26.     { RHD_RS690, "RS690" },
  27.     { RHD_RS740, "RS740" },
  28.     /* R600 */
  29.     { RHD_R600,  "R600" },
  30.     { RHD_RV610, "RV610" },
  31.     { RHD_RV630, "RV630" },
  32.     /* R600 Mobility */
  33.     { RHD_M72,   "M72" },
  34.     { RHD_M74,   "M74" },
  35.     { RHD_M76,   "M76" },
  36.     /* RV670 came into existence after RV6x0 and M7x */
  37.     { RHD_RV670, "RV670" },
  38.     { RHD_R680,  "R680"  },
  39.     { RHD_RV620, "RV620" },
  40.     { RHD_RV635, "RV635" },
  41.     { -1,      NULL }
  42. };
  43.  
  44.  
  45.  
  46. static struct rhdChipsetMapStruct {
  47.     enum RHD_FAMILIES family;
  48.     Bool IGP;
  49. } rhdChipsetMap[] = {
  50.     { RHD_FAMILY_UNKNOWN, 0 }, /* RHD_UNKNOWN */
  51.  
  52.     { RHD_FAMILY_R300,  0 },     /* RHD_R300 */
  53.     { RHD_FAMILY_R350,  0 },     /* RHD_R350 */
  54.     { RHD_FAMILY_RV350, 0 },     /* RHD_RV350 */
  55.     { RHD_FAMILY_RV380, 0 },     /* RHD_RV370 */
  56.     { RHD_FAMILY_RV380, 0 },     /* RHD_RV380 */
  57.  
  58.  
  59.     { RHD_FAMILY_RV515, 0 },     /* RHD_RV505 */
  60.     { RHD_FAMILY_RV515, 0 },     /* RHD_RV515 */
  61.     { RHD_FAMILY_RV515, 0 },     /* RHD_RV516 */
  62.     { RHD_FAMILY_R520,  0 },     /* RHD_R520 */
  63.     { RHD_FAMILY_RV530, 0 },     /* RHD_RV530 */
  64.     { RHD_FAMILY_RV530, 0 },     /* RHD_RV535 */
  65.     { RHD_FAMILY_RV515, 0 },     /* RHD_RV550 */
  66.     { RHD_FAMILY_RV560, 0 },     /* RHD_RV560 */
  67.     { RHD_FAMILY_RV570, 0 },     /* RHD_RV570 */
  68.     { RHD_FAMILY_R580,  0 },     /* RHD_R580 */
  69.     { RHD_FAMILY_RV515, 0 },     /* RHD_M52 */
  70.     { RHD_FAMILY_RV515, 0 },     /* RHD_M54 */
  71.     { RHD_FAMILY_RV530, 0 },     /* RHD_M56 */
  72.     { RHD_FAMILY_R520,  0 },     /* RHD_M58 */
  73.     { RHD_FAMILY_RV515, 0 },     /* RHD_M62 */
  74.     { RHD_FAMILY_RV515, 0 },     /* RHD_M64 */
  75.     { RHD_FAMILY_RV530, 0 },     /* RHD_M66 */
  76.     { RHD_FAMILY_R580,  0 },     /* RHD_M68 */
  77.     { RHD_FAMILY_RV515, 0 },     /* RHD_M71 */
  78.     { RHD_FAMILY_RS690, 1 },     /* RHD_RS600 */
  79.     { RHD_FAMILY_RS690, 1 },     /* RHD_RS690 */
  80.     { RHD_FAMILY_RS690, 1 },     /* RHD_RS740 */
  81.     { RHD_FAMILY_R600,  0 },     /* RHD_R600 */
  82.     { RHD_FAMILY_RV610, 0 },     /* RHD_RV610 */
  83.     { RHD_FAMILY_RV630, 0 },     /* RHD_RV630 */
  84.     { RHD_FAMILY_RV610, 0 },     /* RHD_M72 */
  85.     { RHD_FAMILY_RV610, 0 },     /* RHD_M74 */
  86.     { RHD_FAMILY_RV630, 0 },     /* RHD_M76 */
  87.     { RHD_FAMILY_RV670, 0 },     /* RHD_RV670 */
  88.     { RHD_FAMILY_RV670, 0 },     /* RHD_R680 */
  89.     { RHD_FAMILY_RV620, 0 },     /* RHD_RV620 */
  90.     { RHD_FAMILY_RV620, 0 },     /* RHD_M82 */
  91.     { RHD_FAMILY_RV635, 0 },     /* RHD_RV635 */
  92.     { RHD_FAMILY_UNKNOWN, 0 },   /* RHD_M86 */
  93.     { RHD_FAMILY_RS780, 1 }      /* RHD_RS780 */
  94.     /* RHD_CHIP_END */
  95. };
  96.  
  97.  
  98. # define RHD_DEVICE_MATCH(d, i) { (d),(i) }
  99. # define PCI_ID_LIST PciChipset_t RHDPCIchipsets[]
  100. # define LIST_END { 0,  0}
  101.  
  102. const PCI_ID_LIST = {
  103.  
  104.     RHD_DEVICE_MATCH(  0x4144, RHD_R300  ), /* ATI Radeon 9500    */
  105.     RHD_DEVICE_MATCH(  0x4145, RHD_R300  ), /* ATI Radeon 9500    */
  106.     RHD_DEVICE_MATCH(  0x4146, RHD_R300  ), /* ATI Radeon 9600TX  */
  107.     RHD_DEVICE_MATCH(  0x4147, RHD_R300  ), /* ATI FireGL Z1      */
  108.     RHD_DEVICE_MATCH(  0x4148, RHD_R350  ), /* ATI Radeon 9800SE  */
  109.     RHD_DEVICE_MATCH(  0x4149, RHD_R350  ), /* ATI Radeon 9800    */
  110.     RHD_DEVICE_MATCH(  0x414A, RHD_R350  ), /* ATI Radeon 9800    */
  111.     RHD_DEVICE_MATCH(  0x414B, RHD_R350  ), /* ATI FireGL X2      */
  112.  
  113.     RHD_DEVICE_MATCH(  0x4150, RHD_RV350 ), /* ATI Radeon 9600    */
  114.     RHD_DEVICE_MATCH(  0x4151, RHD_RV350 ), /* ATI Radeon 9600SE  */
  115.     RHD_DEVICE_MATCH(  0x4152, RHD_RV350 ), /* ATI Radeon 9600XT  */
  116.     RHD_DEVICE_MATCH(  0x4153, RHD_RV350 ), /* ATI Radeon 9600    */
  117.     RHD_DEVICE_MATCH(  0x4154, RHD_RV350 ), /* ATI FireGL T2      */
  118.     RHD_DEVICE_MATCH(  0x4155, RHD_RV350 ), /* ATI Radeon 9650    */
  119.     RHD_DEVICE_MATCH(  0x4156, RHD_RV350 ), /* ATI FireGL RV360   */
  120.  
  121.     RHD_DEVICE_MATCH(  0x4E44, RHD_R300  ),
  122.     RHD_DEVICE_MATCH(  0x4E45, RHD_R300  ),
  123.     RHD_DEVICE_MATCH(  0x4E46, RHD_R300  ),
  124.     RHD_DEVICE_MATCH(  0x4E47, RHD_R300  ),
  125.     RHD_DEVICE_MATCH(  0x4E48, RHD_R350  ),
  126.     RHD_DEVICE_MATCH(  0x4E49, RHD_R350  ),
  127.     RHD_DEVICE_MATCH(  0x4E4A, RHD_R350  ),
  128.     RHD_DEVICE_MATCH(  0x4E4B, RHD_R350  ),
  129.     RHD_DEVICE_MATCH(  0x4E50, RHD_RV350 ),
  130.     RHD_DEVICE_MATCH(  0x4E51, RHD_RV350 ),
  131.     RHD_DEVICE_MATCH(  0x4E52, RHD_RV350 ),
  132.     RHD_DEVICE_MATCH(  0x4E53, RHD_RV350 ),
  133.     RHD_DEVICE_MATCH(  0x4E54, RHD_RV350 ),
  134.     RHD_DEVICE_MATCH(  0x4E56, RHD_RV350 ),
  135.  
  136.  
  137.     RHD_DEVICE_MATCH(  0x5B60, RHD_RV380 ),
  138.     RHD_DEVICE_MATCH(  0x5B62, RHD_RV380 ),
  139.     RHD_DEVICE_MATCH(  0x5B63, RHD_RV380 ),
  140.     RHD_DEVICE_MATCH(  0x5B64, RHD_RV380 ),
  141.     RHD_DEVICE_MATCH(  0x5B65, RHD_RV380 ),
  142.  
  143.     RHD_DEVICE_MATCH(  0x7100, RHD_R520  ), /* Radeon X1800 */
  144.     RHD_DEVICE_MATCH(  0x7101, RHD_M58   ), /* Mobility Radeon X1800 XT */
  145.     RHD_DEVICE_MATCH(  0x7102, RHD_M58   ), /* Mobility Radeon X1800 */
  146.     RHD_DEVICE_MATCH(  0x7103, RHD_M58   ), /* Mobility FireGL V7200 */
  147.     RHD_DEVICE_MATCH(  0x7104, RHD_R520  ), /* FireGL V7200 */
  148.     RHD_DEVICE_MATCH(  0x7105, RHD_R520  ), /* FireGL V5300 */
  149.     RHD_DEVICE_MATCH(  0x7106, RHD_M58   ), /* Mobility FireGL V7100 */
  150.     RHD_DEVICE_MATCH(  0x7108, RHD_R520  ), /* Radeon X1800 */
  151.     RHD_DEVICE_MATCH(  0x7109, RHD_R520  ), /* Radeon X1800 */
  152.     RHD_DEVICE_MATCH(  0x710A, RHD_R520  ), /* Radeon X1800 */
  153.     RHD_DEVICE_MATCH(  0x710B, RHD_R520  ), /* Radeon X1800 */
  154.     RHD_DEVICE_MATCH(  0x710C, RHD_R520  ), /* Radeon X1800 */
  155.     RHD_DEVICE_MATCH(  0x710E, RHD_R520  ), /* FireGL V7300 */
  156.     RHD_DEVICE_MATCH(  0x710F, RHD_R520  ), /* FireGL V7350 */
  157.     RHD_DEVICE_MATCH(  0x7140, RHD_RV515 ), /* Radeon X1600/X1550 */
  158.     RHD_DEVICE_MATCH(  0x7141, RHD_RV505 ), /* RV505 */
  159.     RHD_DEVICE_MATCH(  0x7142, RHD_RV515 ), /* Radeon X1300/X1550 */
  160.     RHD_DEVICE_MATCH(  0x7143, RHD_RV505 ), /* Radeon X1550 */
  161.     RHD_DEVICE_MATCH(  0x7144, RHD_M54   ), /* M54-GL */
  162.     RHD_DEVICE_MATCH(  0x7145, RHD_M54   ), /* Mobility Radeon X1400 */
  163.     RHD_DEVICE_MATCH(  0x7146, RHD_RV515 ), /* Radeon X1300/X1550 */
  164.     RHD_DEVICE_MATCH(  0x7147, RHD_RV505 ), /* Radeon X1550 64-bit */
  165.     RHD_DEVICE_MATCH(  0x7149, RHD_M52   ), /* Mobility Radeon X1300 */
  166.     RHD_DEVICE_MATCH(  0x714A, RHD_M52   ), /* Mobility Radeon X1300 */
  167.     RHD_DEVICE_MATCH(  0x714B, RHD_M52   ), /* Mobility Radeon X1300 */
  168.     RHD_DEVICE_MATCH(  0x714C, RHD_M52   ), /* Mobility Radeon X1300 */
  169.     RHD_DEVICE_MATCH(  0x714D, RHD_RV515 ), /* Radeon X1300 */
  170.     RHD_DEVICE_MATCH(  0x714E, RHD_RV515 ), /* Radeon X1300 */
  171.     RHD_DEVICE_MATCH(  0x714F, RHD_RV505 ), /* RV505 */
  172.     RHD_DEVICE_MATCH(  0x7151, RHD_RV505 ), /* RV505 */
  173.     RHD_DEVICE_MATCH(  0x7152, RHD_RV515 ), /* FireGL V3300 */
  174.     RHD_DEVICE_MATCH(  0x7153, RHD_RV515 ), /* FireGL V3350 */
  175.     RHD_DEVICE_MATCH(  0x715E, RHD_RV515 ), /* Radeon X1300 */
  176.     RHD_DEVICE_MATCH(  0x715F, RHD_RV505 ), /* Radeon X1550 64-bit */
  177.     RHD_DEVICE_MATCH(  0x7180, RHD_RV516 ), /* Radeon X1300/X1550 */
  178.     RHD_DEVICE_MATCH(  0x7181, RHD_RV516 ), /* Radeon X1600 */
  179.     RHD_DEVICE_MATCH(  0x7183, RHD_RV516 ), /* Radeon X1300/X1550 */
  180.     RHD_DEVICE_MATCH(  0x7186, RHD_M64   ), /* Mobility Radeon X1450 */
  181.     RHD_DEVICE_MATCH(  0x7187, RHD_RV516 ), /* Radeon X1300/X1550 */
  182.     RHD_DEVICE_MATCH(  0x7188, RHD_M64   ), /* Mobility Radeon X2300 */
  183.     RHD_DEVICE_MATCH(  0x718A, RHD_M64   ), /* Mobility Radeon X2300 */
  184.     RHD_DEVICE_MATCH(  0x718B, RHD_M62   ), /* Mobility Radeon X1350 */
  185.     RHD_DEVICE_MATCH(  0x718C, RHD_M62   ), /* Mobility Radeon X1350 */
  186.     RHD_DEVICE_MATCH(  0x718D, RHD_M64   ), /* Mobility Radeon X1450 */
  187.     RHD_DEVICE_MATCH(  0x718F, RHD_RV516 ), /* Radeon X1300 */
  188.     RHD_DEVICE_MATCH(  0x7193, RHD_RV516 ), /* Radeon X1550 */
  189.     RHD_DEVICE_MATCH(  0x7196, RHD_M62   ), /* Mobility Radeon X1350 */
  190.     RHD_DEVICE_MATCH(  0x719B, RHD_RV516 ), /* FireMV 2250 */
  191.     RHD_DEVICE_MATCH(  0x719F, RHD_RV516 ), /* Radeon X1550 64-bit */
  192.     RHD_DEVICE_MATCH(  0x71C0, RHD_RV530 ), /* Radeon X1600 */
  193.     RHD_DEVICE_MATCH(  0x71C1, RHD_RV535 ), /* Radeon X1650 */
  194.     RHD_DEVICE_MATCH(  0x71C2, RHD_RV530 ), /* Radeon X1600 */
  195.     RHD_DEVICE_MATCH(  0x71C3, RHD_RV535 ), /* Radeon X1600 */
  196.     RHD_DEVICE_MATCH(  0x71C4, RHD_M56   ), /* Mobility FireGL V5200 */
  197.     RHD_DEVICE_MATCH(  0x71C5, RHD_M56   ), /* Mobility Radeon X1600 */
  198.     RHD_DEVICE_MATCH(  0x71C6, RHD_RV530 ), /* Radeon X1650 */
  199.     RHD_DEVICE_MATCH(  0x71C7, RHD_RV535 ), /* Radeon X1650 */
  200.     RHD_DEVICE_MATCH(  0x71CD, RHD_RV530 ), /* Radeon X1600 */
  201.     RHD_DEVICE_MATCH(  0x71CE, RHD_RV530 ), /* Radeon X1300 XT/X1600 Pro */
  202.     RHD_DEVICE_MATCH(  0x71D2, RHD_RV530 ), /* FireGL V3400 */
  203.     RHD_DEVICE_MATCH(  0x71D4, RHD_M66   ), /* Mobility FireGL V5250 */
  204.     RHD_DEVICE_MATCH(  0x71D5, RHD_M66   ), /* Mobility Radeon X1700 */
  205.     RHD_DEVICE_MATCH(  0x71D6, RHD_M66   ), /* Mobility Radeon X1700 XT */
  206.     RHD_DEVICE_MATCH(  0x71DA, RHD_RV530 ), /* FireGL V5200 */
  207.     RHD_DEVICE_MATCH(  0x71DE, RHD_M66   ), /* Mobility Radeon X1700 */
  208.     RHD_DEVICE_MATCH(  0x7200, RHD_RV550 ), /*  Radeon X2300HD  */
  209.     RHD_DEVICE_MATCH(  0x7210, RHD_M71   ), /* Mobility Radeon HD 2300 */
  210.     RHD_DEVICE_MATCH(  0x7211, RHD_M71   ), /* Mobility Radeon HD 2300 */
  211.     RHD_DEVICE_MATCH(  0x7240, RHD_R580  ), /* Radeon X1950 */
  212.     RHD_DEVICE_MATCH(  0x7243, RHD_R580  ), /* Radeon X1900 */
  213.     RHD_DEVICE_MATCH(  0x7244, RHD_R580  ), /* Radeon X1950 */
  214.     RHD_DEVICE_MATCH(  0x7245, RHD_R580  ), /* Radeon X1900 */
  215.     RHD_DEVICE_MATCH(  0x7246, RHD_R580  ), /* Radeon X1900 */
  216.     RHD_DEVICE_MATCH(  0x7247, RHD_R580  ), /* Radeon X1900 */
  217.     RHD_DEVICE_MATCH(  0x7248, RHD_R580  ), /* Radeon X1900 */
  218.     RHD_DEVICE_MATCH(  0x7249, RHD_R580  ), /* Radeon X1900 */
  219.     RHD_DEVICE_MATCH(  0x724A, RHD_R580  ), /* Radeon X1900 */
  220.     RHD_DEVICE_MATCH(  0x724B, RHD_R580  ), /* Radeon X1900 */
  221.     RHD_DEVICE_MATCH(  0x724C, RHD_R580  ), /* Radeon X1900 */
  222.     RHD_DEVICE_MATCH(  0x724D, RHD_R580  ), /* Radeon X1900 */
  223.     RHD_DEVICE_MATCH(  0x724E, RHD_R580  ), /* AMD Stream Processor */
  224.     RHD_DEVICE_MATCH(  0x724F, RHD_R580  ), /* Radeon X1900 */
  225.     RHD_DEVICE_MATCH(  0x7280, RHD_RV570 ), /* Radeon X1950 */
  226.     RHD_DEVICE_MATCH(  0x7281, RHD_RV560 ), /* RV560 */
  227.     RHD_DEVICE_MATCH(  0x7283, RHD_RV560 ), /* RV560 */
  228.     RHD_DEVICE_MATCH(  0x7284, RHD_M68   ), /* Mobility Radeon X1900 */
  229.     RHD_DEVICE_MATCH(  0x7287, RHD_RV560 ), /* RV560 */
  230.     RHD_DEVICE_MATCH(  0x7288, RHD_RV570 ), /* Radeon X1950 GT */
  231.     RHD_DEVICE_MATCH(  0x7289, RHD_RV570 ), /* RV570 */
  232.     RHD_DEVICE_MATCH(  0x728B, RHD_RV570 ), /* RV570 */
  233.     RHD_DEVICE_MATCH(  0x728C, RHD_RV570 ), /* ATI FireGL V7400  */
  234.     RHD_DEVICE_MATCH(  0x7290, RHD_RV560 ), /* RV560 */
  235.     RHD_DEVICE_MATCH(  0x7291, RHD_RV560 ), /* Radeon X1650 */
  236.     RHD_DEVICE_MATCH(  0x7293, RHD_RV560 ), /* Radeon X1650 */
  237.     RHD_DEVICE_MATCH(  0x7297, RHD_RV560 ), /* RV560 */
  238.     RHD_DEVICE_MATCH(  0x791E, RHD_RS690 ), /* Radeon X1200 */
  239.     RHD_DEVICE_MATCH(  0x791F, RHD_RS690 ), /* Radeon X1200 */
  240.     RHD_DEVICE_MATCH(  0x793F, RHD_RS600 ), /* Radeon Xpress 1200 */
  241.     RHD_DEVICE_MATCH(  0x7941, RHD_RS600 ), /* Radeon Xpress 1200 */
  242.     RHD_DEVICE_MATCH(  0x7942, RHD_RS600 ), /* Radeon Xpress 1200 (M) */
  243.     RHD_DEVICE_MATCH(  0x796C, RHD_RS740 ), /* RS740 */
  244.     RHD_DEVICE_MATCH(  0x796D, RHD_RS740 ), /* RS740M */
  245.     RHD_DEVICE_MATCH(  0x796E, RHD_RS740 ), /* ATI Radeon 2100 RS740 */
  246.     RHD_DEVICE_MATCH(  0x796F, RHD_RS740 ), /* RS740M */
  247.     RHD_DEVICE_MATCH(  0x9400, RHD_R600  ), /* Radeon HD 2900 XT */
  248.     RHD_DEVICE_MATCH(  0x9401, RHD_R600  ), /* Radeon HD 2900 XT */
  249.     RHD_DEVICE_MATCH(  0x9402, RHD_R600  ), /* Radeon HD 2900 XT */
  250.     RHD_DEVICE_MATCH(  0x9403, RHD_R600  ), /* Radeon HD 2900 Pro */
  251.     RHD_DEVICE_MATCH(  0x9405, RHD_R600  ), /* Radeon HD 2900 GT */
  252.     RHD_DEVICE_MATCH(  0x940A, RHD_R600  ), /* FireGL V8650 */
  253.     RHD_DEVICE_MATCH(  0x940B, RHD_R600  ), /* FireGL V8600 */
  254.     RHD_DEVICE_MATCH(  0x940F, RHD_R600  ), /* FireGL V7600 */
  255.     RHD_DEVICE_MATCH(  0x94C0, RHD_RV610 ), /* RV610 */
  256.     RHD_DEVICE_MATCH(  0x94C1, RHD_RV610 ), /* Radeon HD 2400 XT */
  257.     RHD_DEVICE_MATCH(  0x94C3, RHD_RV610 ), /* Radeon HD 2400 Pro */
  258.     RHD_DEVICE_MATCH(  0x94C4, RHD_RV610 ), /* ATI Radeon HD 2400 PRO AGP */
  259.     RHD_DEVICE_MATCH(  0x94C5, RHD_RV610 ), /* FireGL V4000 */
  260.     RHD_DEVICE_MATCH(  0x94C6, RHD_RV610 ), /* RV610 */
  261.     RHD_DEVICE_MATCH(  0x94C7, RHD_RV610 ), /* ATI Radeon HD 2350 */
  262.     RHD_DEVICE_MATCH(  0x94C8, RHD_M74   ), /* Mobility Radeon HD 2400 XT */
  263.     RHD_DEVICE_MATCH(  0x94C9, RHD_M72   ), /* Mobility Radeon HD 2400 */
  264.     RHD_DEVICE_MATCH(  0x94CB, RHD_M72   ), /* ATI RADEON E2400 */
  265.     RHD_DEVICE_MATCH(  0x94CC, RHD_RV610 ), /* ATI Radeon HD 2400 */
  266.     RHD_DEVICE_MATCH(  0x9500, RHD_RV670 ), /* RV670 */
  267.     RHD_DEVICE_MATCH(  0x9501, RHD_RV670 ), /* ATI Radeon HD3870 */
  268.     RHD_DEVICE_MATCH(  0x9505, RHD_RV670 ), /* ATI Radeon HD3850 */
  269.     RHD_DEVICE_MATCH(  0x9507, RHD_RV670 ), /* RV670 */
  270.     RHD_DEVICE_MATCH(  0x950F, RHD_R680  ), /* ATI Radeon HD3870 X2 */
  271.     RHD_DEVICE_MATCH(  0x9511, RHD_RV670 ), /* ATI FireGL V7700 */
  272.     RHD_DEVICE_MATCH(  0x9515, RHD_RV670 ), /* ATI Radeon HD 3850 AGP */
  273.     RHD_DEVICE_MATCH(  0x9580, RHD_RV630 ), /* RV630 */
  274.     RHD_DEVICE_MATCH(  0x9581, RHD_M76   ), /* Mobility Radeon HD 2600 */
  275.     RHD_DEVICE_MATCH(  0x9583, RHD_M76   ), /* Mobility Radeon HD 2600 XT */
  276.     RHD_DEVICE_MATCH(  0x9586, RHD_RV630 ), /* ATI Radeon HD 2600 XT AGP */
  277.     RHD_DEVICE_MATCH(  0x9587, RHD_RV630 ), /* ATI Radeon HD 2600 Pro AGP */
  278.     RHD_DEVICE_MATCH(  0x9588, RHD_RV630 ), /* Radeon HD 2600 XT */
  279.     RHD_DEVICE_MATCH(  0x9589, RHD_RV630 ), /* Radeon HD 2600 Pro */
  280.     RHD_DEVICE_MATCH(  0x958A, RHD_RV630 ), /* Gemini RV630 */
  281.     RHD_DEVICE_MATCH(  0x958B, RHD_M76   ), /* Gemini ATI Mobility Radeon HD 2600 XT */
  282.     RHD_DEVICE_MATCH(  0x958C, RHD_RV630 ), /* FireGL V5600 */
  283.     RHD_DEVICE_MATCH(  0x958D, RHD_RV630 ), /* FireGL V3600 */
  284.     RHD_DEVICE_MATCH(  0x958E, RHD_RV630 ), /* ATI Radeon HD 2600 LE */
  285.     RHD_DEVICE_MATCH(  0x9590, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
  286.     RHD_DEVICE_MATCH(  0x9591, RHD_RV635 ), /* ATI Mobility Radeon HD 3650 */
  287.     RHD_DEVICE_MATCH(  0x9596, RHD_RV635 ), /* ATI Radeon HD 3650 AGP */
  288.     RHD_DEVICE_MATCH(  0x9597, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
  289.     RHD_DEVICE_MATCH(  0x9598, RHD_RV635 ), /* ATI Radeon HD 3670 */
  290.     RHD_DEVICE_MATCH(  0x9599, RHD_RV635 ), /* ATI Radeon HD 3600 Series */
  291.     RHD_DEVICE_MATCH(  0x95C0, RHD_RV620 ), /* ATI Radeon HD 3470 */
  292.     RHD_DEVICE_MATCH(  0x95C2, RHD_M82   ), /* ATI Mobility Radeon HD 3430 (M82) */
  293.     RHD_DEVICE_MATCH(  0x95C4, RHD_M82 ), /* ATI Mobility Radeon HD 3400 Series (M82)  */
  294.     RHD_DEVICE_MATCH(  0x95C5, RHD_RV620 ), /* ATI Radeon HD 3450 */
  295.     RHD_DEVICE_MATCH(  0x95C7, RHD_RV620 ), /* ATI Radeon HD 3430 */
  296.     RHD_DEVICE_MATCH(  0x95CD, RHD_RV620 ), /* ATI FireMV 2450  */
  297.     RHD_DEVICE_MATCH(  0x95CE, RHD_RV620 ), /* ATI FireMV 2260  */
  298.     RHD_DEVICE_MATCH(  0x95CF, RHD_RV620 ), /* ATI FireMV 2260  */
  299.     LIST_END
  300. };
  301.  
  302. const char *
  303. xf86TokenToString(SymTabPtr table, int token)
  304. {
  305.     int i;
  306.  
  307.     for (i = 0; table[i].token >= 0 && table[i].token != token; i++){};
  308.  
  309.     if (table[i].token < 0)
  310.       return NULL;
  311.     else
  312.       return(table[i].name);
  313. }
  314.  
  315. RHDPtr FindPciDevice()
  316. {
  317.   const PciChipset_t *dev;
  318.   u32 bus, last_bus;
  319.  
  320.   if( (last_bus = PciApi(1))==-1)
  321.     return 0;
  322.  
  323.   for(bus=0;bus<=last_bus;bus++)
  324.   {
  325.     u32 devfn;
  326.  
  327.     for(devfn=0;devfn<256;devfn++)
  328.     {
  329.       u32 id;
  330.       id = PciRead32(bus,devfn, 0);
  331.  
  332.       if( (CARD16)id != VENDOR_ATI)
  333.         continue;
  334.  
  335.       if( (dev=PciDevMatch(id>>16,RHDPCIchipsets))!=NULL)
  336.       {
  337.         CARD32 reg2C;
  338.         int i;
  339.  
  340.         rhd.PciDeviceID = (id>>16);
  341.  
  342.         rhd.bus = bus;
  343.         rhd.devfn = devfn;
  344.         rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7);
  345.  
  346.         rhd.ChipSet = dev->ChipSet;
  347.  
  348.         reg2C = PciRead32(bus,devfn, 0x2C);
  349.  
  350.         rhd.subvendor_id = reg2C & 0xFFFF;;
  351.         rhd.subdevice_id = reg2C >> 16;
  352.  
  353.         for (i = 0; i < 6; i++)
  354.         {
  355.           CARD32 base;
  356.           Bool validSize;
  357.  
  358.           base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2));
  359.           if(base)
  360.           {
  361.             if (base & PCI_MAP_IO)
  362.             {
  363.               rhd.ioBase[i] = (CARD32)PCIGETIO(base);
  364.               rhd.memtype[i]   = base & PCI_MAP_IO_ATTR_MASK;
  365.             }
  366.             else
  367.             {
  368.               rhd.memBase[i] = (CARD32)PCIGETMEMORY(base);
  369.               rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK;
  370.             }
  371.           }
  372.           rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize);
  373.         }
  374.         rhd.ChipName = (char*)xf86TokenToString(RHDChipsets, rhd.PciDeviceID);
  375.  
  376.         return &rhd;
  377.       }
  378.     };
  379.   };
  380.   return NULL;
  381. }
  382.  
  383. const PciChipset_t *PciDevMatch(CARD16 dev,const PciChipset_t *list)
  384. {
  385.   while(list->device)
  386.   {
  387.     if(dev==list->device)
  388.       return list;
  389.     list++;
  390.   }
  391.   return 0;
  392. }
  393.  
  394.  
  395. CARD32 pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min)
  396. {
  397.   int offset;
  398.   CARD32 addr1;
  399.   CARD32 addr2;
  400.   CARD32 mask1;
  401.   CARD32 mask2;
  402.   int bits = 0;
  403.  
  404.   /*
  405.    * silently ignore bogus index values.  Valid values are 0-6.  0-5 are
  406.    * the 6 base address registers, and 6 is the ROM base address register.
  407.    */
  408.   if (index < 0 || index > 6)
  409.     return 0;
  410.  
  411.   if (min)
  412.     *min = destructive;
  413.  
  414.   /* Get the PCI offset */
  415.   if (index == 6)
  416.     offset = PCI_MAP_ROM_REG;
  417.   else
  418.     offset = PCI_MAP_REG_START + (index << 2);
  419.  
  420.   addr1 = PciRead32(bus, devfn, offset);
  421.   /*
  422.    * Check if this is the second part of a 64 bit address.
  423.    * XXX need to check how endianness affects 64 bit addresses.
  424.    */
  425.   if (index > 0 && index < 6) {
  426.     addr2 = PciRead32(bus, devfn, offset - 4);
  427.     if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2))
  428.       return 0;
  429.   }
  430.  
  431.   if (destructive) {
  432.      PciWrite32(bus, devfn, offset, 0xffffffff);
  433.      mask1 = PciRead32(bus, devfn, offset);
  434.      PciWrite32(bus, devfn, offset, addr1);
  435.   } else {
  436.     mask1 = addr1;
  437.   }
  438.  
  439.   /* Check if this is the first part of a 64 bit address. */
  440.   if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1))
  441.   {
  442.     if (PCIGETMEMORY(mask1) == 0)
  443.     {
  444.       addr2 = PciRead32(bus, devfn, offset + 4);
  445.       if (destructive)
  446.       {
  447.         PciWrite32(bus, devfn, offset + 4, 0xffffffff);
  448.         mask2 = PciRead32(bus, devfn, offset + 4);
  449.         PciWrite32(bus, devfn, offset + 4, addr2);
  450.       }
  451.       else
  452.      {
  453.        mask2 = addr2;
  454.      }
  455.      if (mask2 == 0)
  456.        return 0;
  457.      bits = 32;
  458.      while ((mask2 & 1) == 0)
  459.      {
  460.        bits++;
  461.        mask2 >>= 1;
  462.      }
  463.      if (bits > 32)
  464.           return bits;
  465.     }
  466.   }
  467.   if (index < 6)
  468.     if (PCI_MAP_IS_MEM(mask1))
  469.       mask1 = PCIGETMEMORY(mask1);
  470.     else
  471.       mask1 = PCIGETIO(mask1);
  472.   else
  473.     mask1 = PCIGETROM(mask1);
  474.   if (mask1 == 0)
  475.     return 0;
  476.   bits = 0;
  477.   while ((mask1 & 1) == 0) {
  478.     bits++;
  479.     mask1 >>= 1;
  480.   }
  481.   /* I/O maps can be no larger than 8 bits */
  482.  
  483.   if ((index < 6) && PCI_MAP_IS_IO(addr1) && bits > 8)
  484.     bits = 8;
  485.   /* ROM maps can be no larger than 24 bits */
  486.   if (index == 6 && bits > 24)
  487.     bits = 24;
  488.   return bits;
  489. }
  490.  
  491.  
  492.