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  1.  
  2.  
  3. static Bool rhdMapMMIO(RHDPtr rhdPtr)
  4. {
  5.      rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR];
  6.      rhdPtr->MMIOBase = MapIoMem((void*)rhdPtr->memBase[RHD_MMIO_BAR],
  7.                                  rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE);
  8.      if( rhdPtr->MMIOBase==0)
  9.         return 0;
  10.  
  11.      DBG(dbgprintf("Mapped IO at %x (size %x)\n", rhdPtr->MMIOBase, rhdPtr->MMIOMapSize));
  12.      return 1;
  13. }
  14.  
  15. /* Read MC register */
  16. unsigned INMC(RHDPtr info, int addr)
  17. {
  18.     u32_t       data;
  19.  
  20.     if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  21.        (info->ChipFamily == CHIP_FAMILY_RS740)) {
  22.        OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  23.        data = INREG(RS690_MC_DATA);
  24.     } else if (info->ChipFamily == CHIP_FAMILY_RS600) {
  25.        OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK));
  26.        data = INREG(RS600_MC_DATA);
  27.     } else if (IS_AVIVO_VARIANT) {
  28.        OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
  29.        (void)INREG(AVIVO_MC_INDEX);
  30.        data = INREG(AVIVO_MC_DATA);
  31.  
  32.        OUTREG(AVIVO_MC_INDEX, 0);
  33.        (void)INREG(AVIVO_MC_INDEX);
  34.     } else {
  35.        OUTREG(R300_MC_IND_INDEX, addr & 0x3f);
  36.        (void)INREG(R300_MC_IND_INDEX);
  37.        data = INREG(R300_MC_IND_DATA);
  38.  
  39.        OUTREG(R300_MC_IND_INDEX, 0);
  40.        (void)INREG(R300_MC_IND_INDEX);
  41.     }
  42.  
  43.     return data;
  44. }
  45.  
  46.      /* Write MC information */
  47. void OUTMC(RHDPtr info, int addr, u32_t data)
  48. {
  49.      if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  50.          (info->ChipFamily == CHIP_FAMILY_RS740)) {
  51.         OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | RS690_MC_INDEX_WR_EN));
  52.         OUTREG(RS690_MC_DATA, data);
  53.         OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
  54.      }
  55.      else if (info->ChipFamily == CHIP_FAMILY_RS600) {
  56.         OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) | RS600_MC_INDEX_WR_EN));
  57.         OUTREG(RS600_MC_DATA, data);
  58.         OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK);
  59.      }
  60.      else if (IS_AVIVO_VARIANT) {
  61.         OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000);
  62.         (void)INREG(AVIVO_MC_INDEX);
  63.         OUTREG(AVIVO_MC_DATA, data);
  64.         OUTREG(AVIVO_MC_INDEX, 0);
  65.         (void)INREG(AVIVO_MC_INDEX);
  66.      }
  67.      else {
  68.         OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | R300_MC_IND_WR_EN));
  69.         (void)INREG(R300_MC_IND_INDEX);
  70.         OUTREG(R300_MC_IND_DATA, data);
  71.         OUTREG(R300_MC_IND_INDEX, 0);
  72.         (void)INREG(R300_MC_IND_INDEX);
  73.      }
  74. }
  75.  
  76. static Bool avivo_get_mc_idle(RHDPtr info)
  77. {
  78.  
  79.      if (info->ChipFamily >= CHIP_FAMILY_R600) {
  80.         /* no idea where this is on r600 yet */
  81.         return TRUE;
  82.      }
  83.      else if (info->ChipFamily == CHIP_FAMILY_RV515) {
  84.         if (INMC(info, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE)
  85.            return TRUE;
  86.         else
  87.            return FALSE;
  88.      }
  89.      else if (info->ChipFamily == CHIP_FAMILY_RS600)
  90.      {
  91.         if (INMC(info, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE)
  92.            return TRUE;
  93.         else
  94.            return FALSE;
  95.      }
  96.      else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  97.                (info->ChipFamily == CHIP_FAMILY_RS740)) {
  98.         if (INMC(info, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE)
  99.            return TRUE;
  100.         else
  101.            return FALSE;
  102.     }
  103.     else {
  104.        if (INMC(info, R520_MC_STATUS) & R520_MC_STATUS_IDLE)
  105.            return TRUE;
  106.        else
  107.            return FALSE;
  108.     }
  109. }
  110.  
  111. #define LOC_FB 0x1
  112. #define LOC_AGP 0x2
  113.  
  114. static void radeon_read_mc_fb_agp_location(RHDPtr info, int mask,
  115.                                 u32_t *fb_loc, u32_t *agp_loc, u32_t *agp_loc_hi)
  116. {
  117.  
  118.     if (info->ChipFamily >= CHIP_FAMILY_RV770) {
  119.        if (mask & LOC_FB)
  120.             *fb_loc = INREG(R700_MC_VM_FB_LOCATION);
  121.         if (mask & LOC_AGP) {
  122.             *agp_loc = INREG(R600_MC_VM_AGP_BOT);
  123.             *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
  124.         }
  125.     } else if (info->ChipFamily >= CHIP_FAMILY_R600) {
  126.         if (mask & LOC_FB)
  127.             *fb_loc = INREG(R600_MC_VM_FB_LOCATION);
  128.         if (mask & LOC_AGP) {
  129.             *agp_loc = INREG(R600_MC_VM_AGP_BOT);
  130.             *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
  131.         }
  132.     } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
  133.         if (mask & LOC_FB)
  134.         *fb_loc = INMC(info, RV515_MC_FB_LOCATION);
  135.         if (mask & LOC_AGP) {
  136.         *agp_loc = INMC(info, RV515_MC_AGP_LOCATION);
  137.             *agp_loc_hi = 0;
  138.         }
  139.     } else if (info->ChipFamily == CHIP_FAMILY_RS600) {
  140.         if (mask & LOC_FB)
  141.         *fb_loc = INMC(info, RS600_MC_FB_LOCATION);
  142.         if (mask & LOC_AGP) {
  143.             *agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION);
  144.             *agp_loc_hi = 0;
  145.         }
  146.     } else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  147.                (info->ChipFamily == CHIP_FAMILY_RS740)) {
  148.         if (mask & LOC_FB)
  149.         *fb_loc = INMC(info, RS690_MC_FB_LOCATION);
  150.         if (mask & LOC_AGP) {
  151.         *agp_loc = INMC(info, RS690_MC_AGP_LOCATION);
  152.             *agp_loc_hi = 0;
  153.         }
  154.     } else if (info->ChipFamily >= CHIP_FAMILY_R520) {
  155.         if (mask & LOC_FB)
  156.         *fb_loc = INMC(info, R520_MC_FB_LOCATION);
  157.         if (mask & LOC_AGP) {
  158.         *agp_loc = INMC(info, R520_MC_AGP_LOCATION);
  159.             *agp_loc_hi = 0;
  160.         }
  161.     } else {
  162.         if (mask & LOC_FB)
  163.             *fb_loc = INREG(RADEON_MC_FB_LOCATION);
  164.         if (mask & LOC_AGP)
  165.             *agp_loc = INREG(RADEON_MC_AGP_LOCATION);
  166.     }
  167. }
  168.  
  169. static void radeon_write_mc_fb_agp_location(RHDPtr info, int mask, u32_t fb_loc,
  170.                       u32_t agp_loc, u32_t agp_loc_hi)
  171. {
  172.  
  173.      if (info->ChipFamily >= CHIP_FAMILY_RV770) {
  174.         if (mask & LOC_FB)
  175.            OUTREG(R700_MC_VM_FB_LOCATION, fb_loc);
  176.         if (mask & LOC_AGP) {
  177.            OUTREG(R600_MC_VM_AGP_BOT, agp_loc);
  178.            OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi);
  179.         }
  180.      }
  181.      else if (info->ChipFamily >= CHIP_FAMILY_R600)
  182.      {
  183.         if (mask & LOC_FB)
  184.            OUTREG(R600_MC_VM_FB_LOCATION, fb_loc);
  185.         if (mask & LOC_AGP) {
  186.            OUTREG(R600_MC_VM_AGP_BOT, agp_loc);
  187.            OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi);
  188.         }
  189.      }
  190.      else if (info->ChipFamily == CHIP_FAMILY_RV515)
  191.      {
  192.         if (mask & LOC_FB)
  193.            OUTMC(info, RV515_MC_FB_LOCATION, fb_loc);
  194.         if (mask & LOC_AGP)
  195.            OUTMC(info, RV515_MC_AGP_LOCATION, agp_loc);
  196.            (void)INMC(info, RV515_MC_AGP_LOCATION);
  197.      }
  198.      else if (info->ChipFamily == CHIP_FAMILY_RS600)
  199.      {
  200.      if (mask & LOC_FB)
  201.         OUTMC(info, RS600_MC_FB_LOCATION, fb_loc);
  202.         /*      if (mask & LOC_AGP)
  203.                 OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc);*/
  204.      }
  205.      else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  206.               (info->ChipFamily == CHIP_FAMILY_RS740))
  207.      {
  208.         if (mask & LOC_FB)
  209.            OUTMC(info, RS690_MC_FB_LOCATION, fb_loc);
  210.         if (mask & LOC_AGP)
  211.            OUTMC(info, RS690_MC_AGP_LOCATION, agp_loc);
  212.      }
  213.      else if (info->ChipFamily >= CHIP_FAMILY_R520)
  214.      {
  215.         if (mask & LOC_FB)
  216.            OUTMC(info, R520_MC_FB_LOCATION, fb_loc);
  217.         if (mask & LOC_AGP)
  218.            OUTMC(info, R520_MC_AGP_LOCATION, agp_loc);
  219.            (void)INMC(info, R520_MC_FB_LOCATION);
  220.      }
  221.      else {
  222.         if (mask & LOC_FB)
  223.            OUTREG(RADEON_MC_FB_LOCATION, fb_loc);
  224.         if (mask & LOC_AGP)
  225.            OUTREG(RADEON_MC_AGP_LOCATION, agp_loc);
  226.     }
  227. }
  228.  
  229. #if !R300_PIO
  230.  
  231. static void RADEONUpdateMemMapRegisters(RHDPtr info)
  232. {
  233.      u32_t timeout;
  234.  
  235.      u32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi;
  236.  
  237.      radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &mc_fb_loc,
  238.                                    &mc_agp_loc, &mc_agp_loc_hi);
  239.  
  240.      if (IS_AVIVO_VARIANT)
  241.      {
  242.  
  243.         if (mc_fb_loc  != info->mc_fb_location  ||
  244.             mc_agp_loc != info->mc_agp_location)
  245.         {
  246.            u32_t d1crtc, d2crtc;
  247.            u32_t tmp;
  248. //           RADEONWaitForIdleMMIO(pScrn);
  249.  
  250.            OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
  251.            OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
  252.  
  253.            /* Stop display & memory access */
  254.            d1crtc = INREG(AVIVO_D1CRTC_CONTROL);
  255.            OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc & ~AVIVO_CRTC_EN);
  256.  
  257.            d2crtc = INREG(AVIVO_D2CRTC_CONTROL);
  258.            OUTREG(AVIVO_D2CRTC_CONTROL, d2crtc & ~AVIVO_CRTC_EN);
  259.  
  260.            tmp = INREG(AVIVO_D2CRTC_CONTROL);
  261.  
  262.            usleep(10000);
  263.            timeout = 0;
  264.            while (!(avivo_get_mc_idle(info)))
  265.            {
  266.               if (++timeout > 1000000)
  267.               {
  268.                  dbgprintf("Timeout trying to update memory controller settings !\n");
  269.                  dbgprintf("You will probably crash now ... \n");
  270.                /* Nothing we can do except maybe try to kill the server,
  271.                 * let's wait 2 seconds to leave the above message a chance
  272.                 * to maybe hit the disk and continue trying to setup despite
  273.                 * the MC being non-idle
  274.                 */
  275.                  usleep(2000000);
  276.               }
  277.               usleep(10);
  278.            }
  279.  
  280.            radeon_write_mc_fb_agp_location(info, LOC_FB | LOC_AGP,
  281.                            info->mc_fb_location,
  282.                            info->mc_agp_location,
  283.                            info->mc_agp_location_hi);
  284.  
  285.            if (info->ChipFamily < CHIP_FAMILY_R600) {
  286.               OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
  287.            }
  288.            else {
  289.               OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
  290.            }
  291.  
  292.            OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc );
  293.  
  294.            OUTREG(AVIVO_D2CRTC_CONTROL, d2crtc );
  295.  
  296.            tmp = INREG(AVIVO_D2CRTC_CONTROL);
  297.  
  298.            /* Reset the engine and HDP */
  299. //           RADEONEngineReset(pScrn);
  300.        }
  301.      }
  302.      else
  303.      {
  304.  
  305.         /* Write memory mapping registers only if their value change
  306.          * since we must ensure no access is done while they are
  307.          * reprogrammed
  308.          */
  309.         if ( mc_fb_loc != info->mc_fb_location   ||
  310.              mc_agp_loc != info->mc_agp_location)
  311.         {
  312.            u32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl;
  313.            u32_t old_mc_status, status_idle;
  314.  
  315.            dbgprintf("  Map Changed ! Applying ...\n");
  316.  
  317.             /* Make sure engine is idle. We assume the CCE is stopped
  318.              * at this point
  319.              */
  320.    //        RADEONWaitForIdleMMIO(info);
  321.  
  322.            if (info->IsIGP)
  323.               goto igp_no_mcfb;
  324.  
  325.             /* Capture MC_STATUS in case things go wrong ... */
  326.            old_mc_status = INREG(RADEON_MC_STATUS);
  327.  
  328.             /* Stop display & memory access */
  329.            ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
  330.            OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
  331.            crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
  332.            OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
  333.            crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
  334. //           RADEONWaitForVerticalSync(pScrn);
  335.            OUTREG(RADEON_CRTC_GEN_CNTL,
  336.                  (crtc_gen_cntl  & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN))
  337.                  | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
  338.  
  339.            if (info->HasCRTC2)
  340.            {
  341.               crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
  342. //              RADEONWaitForVerticalSync2(pScrn);
  343.               OUTREG(RADEON_CRTC2_GEN_CNTL, (crtc2_gen_cntl
  344.                      & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN))
  345.                     | RADEON_CRTC2_DISP_REQ_EN_B);
  346.            }
  347.  
  348.             /* Make sure the chip settles down (paranoid !) */
  349.            usleep(1000);
  350.  
  351.             /* Wait for MC idle */
  352.            if (IS_R300_VARIANT)
  353.               status_idle = R300_MC_IDLE;
  354.            else
  355.               status_idle = RADEON_MC_IDLE;
  356.  
  357.            timeout = 0;
  358.            while (!(INREG(RADEON_MC_STATUS) & status_idle))
  359.            {
  360.               if (++timeout > 1000000)
  361.               {
  362.                  dbgprintf("Timeout trying to update memory controller settings !\n");
  363.                  dbgprintf("MC_STATUS = 0x%08x (on entry = 0x%08x)\n",
  364.                            INREG(RADEON_MC_STATUS), old_mc_status);
  365.                  dbgprintf("You will probably crash now ... \n");
  366.                     /* Nothing we can do except maybe try to kill the server,
  367.                      * let's wait 2 seconds to leave the above message a chance
  368.                      * to maybe hit the disk and continue trying to setup despite
  369.                      * the MC being non-idle
  370.                      */
  371.                  usleep(20000);
  372.               }
  373.               usleep(10);
  374.            }
  375.  
  376.             /* Update maps, first clearing out AGP to make sure we don't get
  377.              * a temporary overlap
  378.              */
  379.            OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc);
  380.            OUTREG(RADEON_MC_FB_LOCATION, info->mc_fb_location);
  381.            radeon_write_mc_fb_agp_location(info, LOC_FB | LOC_AGP, info->mc_fb_location,
  382.                            0xfffffffc, 0);
  383.  
  384.            OUTREG(RADEON_CRTC_GEN_CNTL,crtc_gen_cntl );
  385.            OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  386.            OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl );
  387.  
  388.  
  389.  igp_no_mcfb:
  390.            radeon_write_mc_fb_agp_location(info, LOC_AGP, 0,
  391.                         info->mc_agp_location, 0);
  392.             /* Make sure map fully reached the chip */
  393.            (void)INREG(RADEON_MC_FB_LOCATION);
  394.  
  395.            dbgprintf("  Map applied, resetting engine ...\n");
  396.  
  397.             /* Reset the engine and HDP */
  398. //        RADEONEngineReset(pScrn);
  399.  
  400.             /* Make sure we have sane offsets before re-enabling the CRTCs, disable
  401.              * stereo, clear offsets, and wait for offsets to catch up with hw
  402.              */
  403.  
  404.            OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL);
  405.            OUTREG(RADEON_CRTC_OFFSET, 0);
  406.            OUTREG(RADEON_CUR_OFFSET, 0);
  407.            timeout = 0;
  408.            while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
  409.            {
  410.               if (timeout++ > 1000000) {
  411.                  dbgprintf("Timeout waiting for CRTC offset to update !\n");
  412.                  break;
  413.               }
  414.               usleep(1000);
  415.            }
  416.            if (info->HasCRTC2)
  417.            {
  418.               OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL);
  419.               OUTREG(RADEON_CRTC2_OFFSET, 0);
  420.               OUTREG(RADEON_CUR2_OFFSET, 0);
  421.               timeout = 0;
  422.               while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET)
  423.               {
  424.                  if (timeout++ > 1000000) {
  425.                     dbgprintf("Timeout waiting for CRTC2 offset to update !\n");
  426.                     break;
  427.                  }
  428.                  usleep(1000);
  429.               }
  430.            }
  431.         }
  432.  
  433.         dbgprintf("Updating display base addresses...\n");
  434.  
  435.         OUTREG(RADEON_DISPLAY_BASE_ADDR, info->fbLocation);
  436.         if (info->HasCRTC2)
  437.            OUTREG(RADEON_DISPLAY2_BASE_ADDR, info->fbLocation);
  438.         OUTREG(RADEON_OV0_BASE_ADDR, info->fbLocation);
  439.         (void)INREG(RADEON_OV0_BASE_ADDR);
  440.  
  441.         /* More paranoia delays, wait 100ms */
  442.         usleep(1000);
  443.  
  444.         dbgprintf("Memory map updated.\n");
  445.      };
  446. };
  447.  
  448. #endif
  449.  
  450.  
  451.  
  452. static void RADEONInitMemoryMap(RHDPtr info)
  453. {
  454.      u32_t       mem_size;
  455.      u32_t       aper_size;
  456.  
  457.      radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location,
  458.                     &info->mc_agp_location, &info->mc_agp_location_hi);
  459.  
  460.       dbgprintf("  MC_FB_LOCATION   : 0x%08x\n", (unsigned)info->mc_fb_location);
  461.       dbgprintf("  MC_AGP_LOCATION  : 0x%08x\n", (unsigned)info->mc_agp_location);
  462.  
  463.  
  464.      /* We shouldn't use info->videoRam here which might have been clipped
  465.       * but the real video RAM instead
  466.       */
  467.      if (info->ChipFamily >= CHIP_FAMILY_R600){
  468.         mem_size = INREG(R600_CONFIG_MEMSIZE);
  469.         aper_size = INREG(R600_CONFIG_APER_SIZE);
  470.      }
  471.      else {
  472.         mem_size = INREG(RADEON_CONFIG_MEMSIZE);
  473.         aper_size = INREG(RADEON_CONFIG_APER_SIZE);
  474.      }
  475.  
  476.      if (mem_size == 0)
  477.         mem_size = 0x800000;
  478.  
  479.      /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
  480.         Novell bug 204882 + along with lots of ubuntu ones */
  481.      if (aper_size > mem_size)
  482.         mem_size = aper_size;
  483.  
  484.  
  485.      if ( (info->ChipFamily != CHIP_FAMILY_RS600) &&
  486.           (info->ChipFamily != CHIP_FAMILY_RS690) &&
  487.           (info->ChipFamily != CHIP_FAMILY_RS740)) {
  488.         if (info->IsIGP)
  489.            info->mc_fb_location = INREG(RADEON_NB_TOM);
  490.         else
  491.         {
  492.            u32_t aper0_base;
  493.  
  494.            if (info->ChipFamily >= CHIP_FAMILY_R600) {
  495.               aper0_base = INREG(R600_CONFIG_F0_BASE);
  496.            }
  497.            else {
  498.               aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
  499.            }
  500.            dbgprintf("aper0 base %x\n", aper0_base );
  501.  
  502.          /* Recent chips have an "issue" with the memory controller, the
  503.           * location must be aligned to the size. We just align it down,
  504.           * too bad if we walk over the top of system memory, we don't
  505.           * use DMA without a remapped anyway.
  506.           * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
  507.           */
  508.            if ( info->ChipFamily == CHIP_FAMILY_RV280 ||
  509.                 info->ChipFamily == CHIP_FAMILY_R300 ||
  510.                 info->ChipFamily == CHIP_FAMILY_R350 ||
  511.                 info->ChipFamily == CHIP_FAMILY_RV350 ||
  512.                 info->ChipFamily == CHIP_FAMILY_RV380 ||
  513.                 info->ChipFamily == CHIP_FAMILY_R420 ||
  514.                 info->ChipFamily == CHIP_FAMILY_RV410)
  515.               aper0_base &= ~(mem_size - 1);
  516.  
  517.            if ( info->ChipFamily >= CHIP_FAMILY_R600) {
  518.               info->mc_fb_location = (aper0_base >> 24) |
  519.               (((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
  520.               dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
  521.            }
  522.            else {
  523.               info->mc_fb_location = (aper0_base >> 16) |
  524.               ((aper0_base + mem_size - 1) & 0xffff0000U);
  525.               dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
  526.            }
  527.         }
  528.      }
  529.      if (info->ChipFamily >= CHIP_FAMILY_R600) {
  530.         info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
  531.      }
  532.      else {
  533.         info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
  534.      }
  535.      /* Just disable the damn AGP apertures for now, it may be
  536.       * re-enabled later by the DRM
  537.       */
  538.  
  539. //     if (IS_AVIVO_VARIANT) {
  540. //        if (info->ChipFamily >= CHIP_FAMILY_R600) {
  541. //           OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
  542. //        }
  543. //        else {
  544. //           OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
  545. //        }
  546. //        info->mc_agp_location = 0x003f0000;
  547. //     }
  548. //     else
  549. //         info->mc_agp_location = 0xffffffc0;
  550.  
  551.       dbgprintf("RADEONInitMemoryMap() : \n");
  552.       dbgprintf("  mem_size         : 0x%08x\n", (u32_t)mem_size);
  553.       dbgprintf("  MC_FB_LOCATION   : 0x%08x\n", (unsigned)info->mc_fb_location);
  554.       dbgprintf("  MC_AGP_LOCATION  : 0x%08x\n", (unsigned)info->mc_agp_location);
  555.       dbgprintf("  FB_LOCATION   : 0x%08x\n", (unsigned)info->fbLocation);
  556.  
  557. #if !R300_PIO
  558.  
  559.       RADEONUpdateMemMapRegisters(info);
  560.  
  561. #endif
  562.  
  563. }
  564.  
  565. static void RADEONGetVRamType(RHDPtr info)
  566. {
  567.      u32_t tmp;
  568.  
  569.      if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300))
  570.         info->IsDDR = TRUE;
  571.      else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
  572.         info->IsDDR = TRUE;
  573.      else
  574.         info->IsDDR = FALSE;
  575.  
  576.      if ( (info->ChipFamily >= CHIP_FAMILY_R600) &&
  577.           (info->ChipFamily <= CHIP_FAMILY_RV635))
  578.      {
  579.         int chansize;
  580.         /* r6xx */
  581.         tmp = INREG(R600_RAMCFG);
  582.         if (tmp & R600_CHANSIZE_OVERRIDE)
  583.             chansize = 16;
  584.         else if (tmp & R600_CHANSIZE)
  585.             chansize = 64;
  586.         else
  587.             chansize = 32;
  588.         if (info->ChipFamily == CHIP_FAMILY_R600)
  589.             info->RamWidth = 8 * chansize;
  590.         else if (info->ChipFamily == CHIP_FAMILY_RV670)
  591.             info->RamWidth = 4 * chansize;
  592.         else if ((info->ChipFamily == CHIP_FAMILY_RV610) ||
  593.              (info->ChipFamily == CHIP_FAMILY_RV620))
  594.             info->RamWidth = chansize;
  595.         else if ((info->ChipFamily == CHIP_FAMILY_RV630) ||
  596.              (info->ChipFamily == CHIP_FAMILY_RV635))
  597.             info->RamWidth = 2 * chansize;
  598.      }
  599.      else if (info->ChipFamily == CHIP_FAMILY_RV515) {
  600.      /* rv515/rv550 */
  601.         tmp = INMC(info, RV515_MC_CNTL);
  602.         tmp &= RV515_MEM_NUM_CHANNELS_MASK;
  603.         switch (tmp) {
  604.            case 0: info->RamWidth = 64; break;
  605.            case 1: info->RamWidth = 128; break;
  606.            default: info->RamWidth = 128; break;
  607.         }
  608.      }
  609.      else if ((info->ChipFamily >= CHIP_FAMILY_R520) &&
  610.               (info->ChipFamily <= CHIP_FAMILY_RV570)){
  611.      /* r520/rv530/rv560/rv570/r580 */
  612.         tmp = INMC(info, R520_MC_CNTL0);
  613.         switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
  614.            case 0: info->RamWidth = 32; break;
  615.            case 1: info->RamWidth = 64; break;
  616.            case 2: info->RamWidth = 128; break;
  617.            case 3: info->RamWidth = 256; break;
  618.            default: info->RamWidth = 64; break;
  619.         }
  620.         if (tmp & R520_MC_CHANNEL_SIZE) {
  621.            info->RamWidth *= 2;
  622.         }
  623.      }
  624.      else if ((info->ChipFamily >= CHIP_FAMILY_R300) &&
  625.               (info->ChipFamily <= CHIP_FAMILY_RV410)) {
  626.      /* r3xx, r4xx */
  627.         tmp = INREG(RADEON_MEM_CNTL);
  628.         tmp &= R300_MEM_NUM_CHANNELS_MASK;
  629.         switch (tmp) {
  630.            case 0: info->RamWidth = 64; break;
  631.            case 1: info->RamWidth = 128; break;
  632.            case 2: info->RamWidth = 256; break;
  633.            default: info->RamWidth = 128; break;
  634.         }
  635.      }
  636.      else if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
  637.               (info->ChipFamily == CHIP_FAMILY_RS100) ||
  638.               (info->ChipFamily == CHIP_FAMILY_RS200)){
  639.      tmp = INREG(RADEON_MEM_CNTL);
  640.      if (tmp & RV100_HALF_MODE)
  641.         info->RamWidth = 32;
  642.      else
  643.         info->RamWidth = 64;
  644.  
  645.      if (!info->HasCRTC2) {
  646.           info->RamWidth /= 4;
  647.           info->IsDDR = TRUE;
  648.      }
  649.      }
  650.      else if (info->ChipFamily <= CHIP_FAMILY_RV280) {
  651.         tmp = INREG(RADEON_MEM_CNTL);
  652.      if (tmp & RADEON_MEM_NUM_CHANNELS_MASK)
  653.         info->RamWidth = 128;
  654.      else
  655.         info->RamWidth = 64;
  656.      } else {
  657.      /* newer IGPs */
  658.         info->RamWidth = 128;
  659.      }
  660.  
  661.      /* This may not be correct, as some cards can have half of channel disabled
  662.       * ToDo: identify these cases
  663.       */
  664. }
  665.  
  666. /*
  667.  * Depending on card genertation, chipset bugs, etc... the amount of vram
  668.  * accessible to the CPU can vary. This function is our best shot at figuring
  669.  * it out. Returns a value in KB.
  670.  */
  671. static u32_t RADEONGetAccessibleVRAM(RHDPtr info)
  672. {
  673.     u32_t       aper_size;
  674.     unsigned char  byte;
  675.  
  676.     if (info->ChipFamily >= CHIP_FAMILY_R600)
  677.        aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
  678.     else
  679.        aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
  680.  
  681.  
  682.     /* Set HDP_APER_CNTL only on cards that are known not to be broken,
  683.      * that is has the 2nd generation multifunction PCI interface
  684.      */
  685.     if (info->ChipFamily == CHIP_FAMILY_RV280 ||
  686.         info->ChipFamily == CHIP_FAMILY_RV350 ||
  687.         info->ChipFamily == CHIP_FAMILY_RV380 ||
  688.         info->ChipFamily == CHIP_FAMILY_R420  ||
  689.         info->ChipFamily == CHIP_FAMILY_RV410 ||
  690.         IS_AVIVO_VARIANT) {
  691.         MASKREG (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
  692.                      ~RADEON_HDP_APER_CNTL);
  693.         dbgprintf("Generation 2 PCI interface, using max accessible memory\n");
  694.             return aper_size * 2;
  695.     }
  696.  
  697.     /* Older cards have all sorts of funny issues to deal with. First
  698.      * check if it's a multifunction card by reading the PCI config
  699.      * header type... Limit those to one aperture size
  700.      */
  701.     byte = pciReadByte(info->PciTag, 0xe);
  702.     if (byte & 0x80) {
  703.        dbgprintf("Generation 1 PCI interface in multifunction mode, "
  704.                  "accessible memory limited to one aperture\n");
  705.        return aper_size;
  706.     }
  707.  
  708.     /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
  709.      * have set it up. We don't write this as it's broken on some ASICs but
  710.      * we expect the BIOS to have done the right thing (might be too optimistic...)
  711.      */
  712.     if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
  713.        return aper_size * 2;
  714.  
  715.     return aper_size;
  716. }
  717.  
  718. int RADEONDRIGetPciAperTableSize(RHDPtr info)
  719. {
  720.     int ret_size;
  721.     int num_pages;
  722.  
  723.     num_pages = (info->pciAperSize * 1024 * 1024) / 4096;
  724.  
  725.     ret_size = num_pages * sizeof(unsigned int);
  726.  
  727.     return ret_size;
  728. }
  729.  
  730. static Bool RADEONPreInitVRAM(RHDPtr info)
  731. {
  732.      u32_t accessible, bar_size;
  733.  
  734.      if ((!IS_AVIVO_VARIANT) && info->IsIGP)
  735.      {
  736.         u32_t tom = INREG(RADEON_NB_TOM);
  737.  
  738.         info->videoRam = (((tom >> 16) -
  739.                  (tom & 0xffff) + 1) << 6);
  740.  
  741.         OUTREG(RADEON_CONFIG_MEMSIZE, info->videoRam * 1024);
  742.      }
  743.      else
  744.      {
  745.         if (info->ChipFamily >= CHIP_FAMILY_R600)
  746.            info->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
  747.         else
  748.         {
  749.          /* Read VRAM size from card */
  750.            info->videoRam      = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
  751.  
  752.          /* Some production boards of m6 will return 0 if it's 8 MB */
  753.            if (info->videoRam == 0)
  754.            {
  755.               info->videoRam = 8192;
  756.               OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000);
  757.            }
  758.         }
  759.      }
  760.  
  761.      RADEONGetVRamType(info);
  762.  
  763.      /* Get accessible memory */
  764.      accessible = RADEONGetAccessibleVRAM(info);
  765.  
  766.      /* Crop it to the size of the PCI BAR */
  767. //     bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024;
  768.  
  769.      bar_size = 1 << (info->memsize[RHD_FB_BAR] - 10);
  770.  
  771.      if (bar_size == 0)
  772.         bar_size = 0x20000;
  773.      if (accessible > bar_size)
  774.         accessible = bar_size;
  775.  
  776.      dbgprintf("Detected total video RAM=%dK width=%dbit,"
  777.                 "accessible=%uK (PCI BAR=%uK)\n",
  778.                 info->videoRam, info->RamWidth,
  779.                 (unsigned)accessible, (unsigned)bar_size);
  780.  
  781.      if (info->videoRam > accessible)
  782.         info->videoRam = accessible;
  783.  
  784.      if (!IS_AVIVO_VARIANT)
  785.         info->MemCntl            = INREG(RADEON_SDRAM_MODE_REG);
  786.         info->BusCntl            = INREG(RADEON_BUS_CNTL);
  787.  
  788.      info->videoRam  &= ~1023;
  789.      info->FbMapSize  = info->videoRam * 1024;
  790.  
  791.      info->gartSize      = RADEON_DEFAULT_GART_SIZE;
  792.      info->ringSize      = RADEON_DEFAULT_RING_SIZE;
  793.      info->bufSize       = RADEON_DEFAULT_BUFFER_SIZE;
  794.  
  795.      info->gartTexSize   = info->gartSize - (info->ringSize + info->bufSize);
  796.  
  797.      info->pciAperSize   = RADEON_DEFAULT_PCI_APER_SIZE;
  798.      info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
  799.  
  800.  
  801.  
  802.      /* if the card is PCI Express reserve the last 32k for the gart table */
  803.  
  804.  //    if (info->cardType == CARD_PCIE )
  805.  //     /* work out the size of pcie aperture */
  806.  //       info->FbSecureSize = RADEONDRIGetPciAperTableSize(info);
  807.  //    else
  808.  //       info->FbSecureSize = 0;
  809.  
  810.      return TRUE;
  811. }
  812.  
  813.  
  814. static Bool RADEONPreInitChipType(RHDPtr rhdPtr)
  815. {
  816.      u32_t cmd_stat;
  817.  
  818.      rhdPtr->ChipErrata = 0;
  819.  
  820.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) &&
  821.           ((_RHDRegRead(rhdPtr,RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
  822.            == RADEON_CFG_ATI_REV_A11))
  823.         rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG;
  824.  
  825.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) ||
  826.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
  827.         rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS;
  828.  
  829.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) ||
  830.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
  831.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
  832.         rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY;
  833.  
  834.      rhdPtr->cardType = CARD_PCI;
  835.  
  836.  
  837.      cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG);
  838.  
  839.      if (cmd_stat & RADEON_CAP_LIST)
  840.      {
  841.         u32_t cap_ptr, cap_id;
  842.  
  843.         cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG);
  844.         cap_ptr &= RADEON_CAP_PTR_MASK;
  845.  
  846.         while(cap_ptr != RADEON_CAP_ID_NULL)
  847.         {
  848.            cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr);
  849.            if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
  850.               rhdPtr->cardType = CARD_AGP;
  851.               break;
  852.            }
  853.            if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) {
  854.               rhdPtr->cardType = CARD_PCIE;
  855.               break;
  856.            }
  857.            cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
  858.         }
  859.      }
  860.  
  861.      dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" :
  862.                (rhdPtr->cardType==CARD_PCIE) ? "PCIE" : "AGP");
  863.  
  864.     /* treat PCIE IGP cards as PCI  */
  865.      if (rhdPtr->cardType == CARD_PCIE && rhdPtr->IsIGP)
  866.          rhdPtr->cardType = CARD_PCI;
  867.  
  868.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
  869.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ||
  870.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS300) ||
  871.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS400) ||
  872.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS480) ||
  873.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS600) ||
  874.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS690) ||
  875.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS740))
  876.         rhdPtr->has_tcl = FALSE;
  877.      else {
  878.         rhdPtr->has_tcl = TRUE;
  879.      }
  880.  
  881.      rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR];
  882.  
  883.      return TRUE;
  884. }
  885.  
  886. #if 0
  887. static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
  888. {
  889.     unsigned char *RADEONMMIO = info->MMIO;
  890. //    unsigned long mode   = drmAgpGetMode(info->dri->drmFD); /* Default mode */
  891. //    unsigned int  vendor = drmAgpVendorId(info->dri->drmFD);
  892. //    unsigned int  device = drmAgpDeviceId(info->dri->drmFD);
  893.     /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with
  894.        pcie-agp rialto bridge chip - use the one from bridge which must match */
  895.     uint32_t agp_status = (INREG(RADEON_AGP_STATUS) ); // & RADEON_AGP_MODE_MASK;
  896.     Bool is_v3 = (agp_status & RADEON_AGPv3_MODE);
  897.     unsigned int defaultMode;
  898.  
  899.     if (is_v3) {
  900.        defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
  901.     } else {
  902.         if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4;
  903.         else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2;
  904.         else defaultMode = 1;
  905.     }
  906.  
  907.    // agpMode = defaultMode;
  908.  
  909.     dbgprintf(pScreen->myNum, from, "Using AGP %dx\n", dbgprintf);
  910.  
  911.     mode &= ~RADEON_AGP_MODE_MASK;
  912.     if (is_v3) {
  913.         /* only set one mode bit for AGPv3 */
  914.     switch (defaultMode) {
  915.         case 8:          mode |= RADEON_AGPv3_8X_MODE; break;
  916.         case 4: default: mode |= RADEON_AGPv3_4X_MODE;
  917.         }
  918.         /*TODO: need to take care of other bits valid for v3 mode
  919.          *      currently these bits are not used in all tested cards.
  920.          */
  921.     } else {
  922.     switch (defaultMode) {
  923.         case 4:          mode |= RADEON_AGP_4X_MODE;
  924.         case 2:          mode |= RADEON_AGP_2X_MODE;
  925.         case 1: default: mode |= RADEON_AGP_1X_MODE;
  926.         }
  927.     }
  928.  
  929.     /* AGP Fast Writes.
  930.      * TODO: take into account that certain agp modes don't support fast
  931.      * writes at all */
  932.     mode &= ~RADEON_AGP_FW_MODE; /* Disable per default */
  933.  
  934.     dbgprintf("AGP Mode 0x%08lx\n", mode);
  935.  
  936.     if (drmAgpEnable(info->dri->drmFD, mode) < 0) {
  937.         xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP not enabled\n");
  938.         drmAgpRelease(info->dri->drmFD);
  939.         return FALSE;
  940.     }
  941.  
  942.     /* Workaround for some hardware bugs */
  943.     if (info->ChipFamily < CHIP_FAMILY_R200)
  944.         OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000);
  945.  
  946.                                 /* Modify the mode if the default mode
  947.                                  * is not appropriate for this
  948.                                  * particular combination of graphics
  949.                                  * card and AGP chipset.
  950.                                  */
  951.  
  952.     return TRUE;
  953. }
  954. #endif
  955.  
  956. Bool RHDPreInit()
  957. {
  958.     RHDPtr info;
  959.  
  960.     /* We need access to IO space already */
  961.      if ( !rhdMapMMIO(&rhd) ) {
  962.         dbgprintf("Failed to map MMIO.\n");
  963.         return FALSE;
  964.      };
  965.  
  966.  
  967.      if( !RADEONPreInitChipType(&rhd))
  968.         return FALSE;
  969.  
  970.      if (!RADEONPreInitVRAM(&rhd))
  971.         return FALSE;
  972.  
  973.      RADEONInitMemoryMap(&rhd);
  974.  
  975.      if (!rhd.videoRam)
  976.      {
  977.         dbgprintf("No Video RAM detected.\n");
  978.         goto error1;
  979.      }
  980.      dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam);
  981.  
  982.  //    rhd.FbFreeStart = 0;
  983.      rhd.FbFreeSize = rhd.videoRam << 10;
  984.  
  985.  // if( !rhdMapFB(&rhd))
  986. //    return FALSE;
  987.  
  988. //  rhd.FbScanoutStart = 0;
  989. //  rhd.FbScanoutSize  = 8*1024*1024;
  990.  
  991.   rhd.FbFreeStart    = 10*1024*1024;
  992.   rhd.FbFreeSize     = rhd.FbMapSize - rhd.FbFreeStart - rhd.FbSecureSize;
  993.  
  994.   rhdInitHeap(&rhd);
  995.  
  996.      info = &rhd;
  997.  
  998.  
  999.    return TRUE;
  1000.  
  1001. error1:
  1002.   return FALSE;
  1003. };
  1004.  
  1005.  
  1006.  
  1007.