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  1.  
  2.  
  3. static Bool rhdMapMMIO(RHDPtr rhdPtr)
  4. {
  5.      rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR];
  6.      rhdPtr->MMIOBase = MapIoMem((void*)rhdPtr->memBase[RHD_MMIO_BAR],
  7.                                  rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE);
  8.      if( rhdPtr->MMIOBase==0)
  9.         return 0;
  10.  
  11.      DBG(dbgprintf("Mapped IO at %x (size %x)\n", rhdPtr->MMIOBase, rhdPtr->MMIOMapSize));
  12.      return 1;
  13. }
  14.  
  15. /* Read MC register */
  16. unsigned INMC(RHDPtr info, int addr)
  17. {
  18.     u32_t       data;
  19.  
  20.     if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  21.        (info->ChipFamily == CHIP_FAMILY_RS740)) {
  22.        OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  23.        data = INREG(RS690_MC_DATA);
  24.     } else if (info->ChipFamily == CHIP_FAMILY_RS600) {
  25.        OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK));
  26.        data = INREG(RS600_MC_DATA);
  27.     } else if (IS_AVIVO_VARIANT) {
  28.        OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);
  29.        (void)INREG(AVIVO_MC_INDEX);
  30.        data = INREG(AVIVO_MC_DATA);
  31.  
  32.        OUTREG(AVIVO_MC_INDEX, 0);
  33.        (void)INREG(AVIVO_MC_INDEX);
  34.     } else {
  35.        OUTREG(R300_MC_IND_INDEX, addr & 0x3f);
  36.        (void)INREG(R300_MC_IND_INDEX);
  37.        data = INREG(R300_MC_IND_DATA);
  38.  
  39.        OUTREG(R300_MC_IND_INDEX, 0);
  40.        (void)INREG(R300_MC_IND_INDEX);
  41.     }
  42.  
  43.     return data;
  44. }
  45.  
  46.      /* Write MC information */
  47. void OUTMC(RHDPtr info, int addr, u32_t data)
  48. {
  49.      if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  50.          (info->ChipFamily == CHIP_FAMILY_RS740)) {
  51.         OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | RS690_MC_INDEX_WR_EN));
  52.         OUTREG(RS690_MC_DATA, data);
  53.         OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
  54.      }
  55.      else if (info->ChipFamily == CHIP_FAMILY_RS600) {
  56.         OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) | RS600_MC_INDEX_WR_EN));
  57.         OUTREG(RS600_MC_DATA, data);
  58.         OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK);
  59.      }
  60.      else if (IS_AVIVO_VARIANT) {
  61.         OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000);
  62.         (void)INREG(AVIVO_MC_INDEX);
  63.         OUTREG(AVIVO_MC_DATA, data);
  64.         OUTREG(AVIVO_MC_INDEX, 0);
  65.         (void)INREG(AVIVO_MC_INDEX);
  66.      }
  67.      else {
  68.         OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | R300_MC_IND_WR_EN));
  69.         (void)INREG(R300_MC_IND_INDEX);
  70.         OUTREG(R300_MC_IND_DATA, data);
  71.         OUTREG(R300_MC_IND_INDEX, 0);
  72.         (void)INREG(R300_MC_IND_INDEX);
  73.      }
  74. }
  75.  
  76. static Bool avivo_get_mc_idle(RHDPtr info)
  77. {
  78.  
  79.      if (info->ChipFamily >= CHIP_FAMILY_R600) {
  80.         /* no idea where this is on r600 yet */
  81.         return TRUE;
  82.      }
  83.      else if (info->ChipFamily == CHIP_FAMILY_RV515) {
  84.         if (INMC(info, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE)
  85.            return TRUE;
  86.         else
  87.            return FALSE;
  88.      }
  89.      else if (info->ChipFamily == CHIP_FAMILY_RS600)
  90.      {
  91.         if (INMC(info, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE)
  92.            return TRUE;
  93.         else
  94.            return FALSE;
  95.      }
  96.      else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  97.                (info->ChipFamily == CHIP_FAMILY_RS740)) {
  98.         if (INMC(info, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE)
  99.            return TRUE;
  100.         else
  101.            return FALSE;
  102.     }
  103.     else {
  104.        if (INMC(info, R520_MC_STATUS) & R520_MC_STATUS_IDLE)
  105.            return TRUE;
  106.        else
  107.            return FALSE;
  108.     }
  109. }
  110.  
  111. #define LOC_FB 0x1
  112. #define LOC_AGP 0x2
  113.  
  114. static void radeon_read_mc_fb_agp_location(RHDPtr info, int mask,
  115.                                 u32_t *fb_loc, u32_t *agp_loc, u32_t *agp_loc_hi)
  116. {
  117.  
  118.     if (info->ChipFamily >= CHIP_FAMILY_RV770) {
  119.        if (mask & LOC_FB)
  120.             *fb_loc = INREG(R700_MC_VM_FB_LOCATION);
  121.         if (mask & LOC_AGP) {
  122.             *agp_loc = INREG(R600_MC_VM_AGP_BOT);
  123.             *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
  124.         }
  125.     } else if (info->ChipFamily >= CHIP_FAMILY_R600) {
  126.         if (mask & LOC_FB)
  127.             *fb_loc = INREG(R600_MC_VM_FB_LOCATION);
  128.         if (mask & LOC_AGP) {
  129.             *agp_loc = INREG(R600_MC_VM_AGP_BOT);
  130.             *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
  131.         }
  132.     } else if (info->ChipFamily == CHIP_FAMILY_RV515) {
  133.         if (mask & LOC_FB)
  134.         *fb_loc = INMC(info, RV515_MC_FB_LOCATION);
  135.         if (mask & LOC_AGP) {
  136.         *agp_loc = INMC(info, RV515_MC_AGP_LOCATION);
  137.             *agp_loc_hi = 0;
  138.         }
  139.     } else if (info->ChipFamily == CHIP_FAMILY_RS600) {
  140.         if (mask & LOC_FB)
  141.         *fb_loc = INMC(info, RS600_MC_FB_LOCATION);
  142.         if (mask & LOC_AGP) {
  143.             *agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION);
  144.             *agp_loc_hi = 0;
  145.         }
  146.     } else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  147.                (info->ChipFamily == CHIP_FAMILY_RS740)) {
  148.         if (mask & LOC_FB)
  149.         *fb_loc = INMC(info, RS690_MC_FB_LOCATION);
  150.         if (mask & LOC_AGP) {
  151.         *agp_loc = INMC(info, RS690_MC_AGP_LOCATION);
  152.             *agp_loc_hi = 0;
  153.         }
  154.     } else if (info->ChipFamily >= CHIP_FAMILY_R520) {
  155.         if (mask & LOC_FB)
  156.         *fb_loc = INMC(info, R520_MC_FB_LOCATION);
  157.         if (mask & LOC_AGP) {
  158.         *agp_loc = INMC(info, R520_MC_AGP_LOCATION);
  159.             *agp_loc_hi = 0;
  160.         }
  161.     } else {
  162.         if (mask & LOC_FB)
  163.             *fb_loc = INREG(RADEON_MC_FB_LOCATION);
  164.         if (mask & LOC_AGP)
  165.             *agp_loc = INREG(RADEON_MC_AGP_LOCATION);
  166.     }
  167. }
  168.  
  169. static void radeon_write_mc_fb_agp_location(RHDPtr info, int mask, u32_t fb_loc,
  170.                       u32_t agp_loc, u32_t agp_loc_hi)
  171. {
  172.  
  173.      if (info->ChipFamily >= CHIP_FAMILY_RV770) {
  174.         if (mask & LOC_FB)
  175.            OUTREG(R700_MC_VM_FB_LOCATION, fb_loc);
  176.         if (mask & LOC_AGP) {
  177.            OUTREG(R600_MC_VM_AGP_BOT, agp_loc);
  178.            OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi);
  179.         }
  180.      }
  181.      else if (info->ChipFamily >= CHIP_FAMILY_R600)
  182.      {
  183.         if (mask & LOC_FB)
  184.            OUTREG(R600_MC_VM_FB_LOCATION, fb_loc);
  185.         if (mask & LOC_AGP) {
  186.            OUTREG(R600_MC_VM_AGP_BOT, agp_loc);
  187.            OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi);
  188.         }
  189.      }
  190.      else if (info->ChipFamily == CHIP_FAMILY_RV515)
  191.      {
  192.         if (mask & LOC_FB)
  193.            OUTMC(info, RV515_MC_FB_LOCATION, fb_loc);
  194.         if (mask & LOC_AGP)
  195.            OUTMC(info, RV515_MC_AGP_LOCATION, agp_loc);
  196.            (void)INMC(info, RV515_MC_AGP_LOCATION);
  197.      }
  198.      else if (info->ChipFamily == CHIP_FAMILY_RS600)
  199.      {
  200.      if (mask & LOC_FB)
  201.         OUTMC(info, RS600_MC_FB_LOCATION, fb_loc);
  202.         /*      if (mask & LOC_AGP)
  203.                 OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc);*/
  204.      }
  205.      else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
  206.               (info->ChipFamily == CHIP_FAMILY_RS740))
  207.      {
  208.         if (mask & LOC_FB)
  209.            OUTMC(info, RS690_MC_FB_LOCATION, fb_loc);
  210.         if (mask & LOC_AGP)
  211.            OUTMC(info, RS690_MC_AGP_LOCATION, agp_loc);
  212.      }
  213.      else if (info->ChipFamily >= CHIP_FAMILY_R520)
  214.      {
  215.         if (mask & LOC_FB)
  216.            OUTMC(info, R520_MC_FB_LOCATION, fb_loc);
  217.         if (mask & LOC_AGP)
  218.            OUTMC(info, R520_MC_AGP_LOCATION, agp_loc);
  219.            (void)INMC(info, R520_MC_FB_LOCATION);
  220.      }
  221.      else {
  222.         if (mask & LOC_FB)
  223.            OUTREG(RADEON_MC_FB_LOCATION, fb_loc);
  224.         if (mask & LOC_AGP)
  225.            OUTREG(RADEON_MC_AGP_LOCATION, agp_loc);
  226.     }
  227. }
  228.  
  229.  
  230. static void RADEONUpdateMemMapRegisters(RHDPtr info)
  231. {
  232.      u32_t timeout;
  233.  
  234.      u32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi;
  235.  
  236.      radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &mc_fb_loc,
  237.                                    &mc_agp_loc, &mc_agp_loc_hi);
  238.  
  239.      if (IS_AVIVO_VARIANT)
  240.      {
  241.  
  242.         if (mc_fb_loc  != info->mc_fb_location  ||
  243.             mc_agp_loc != info->mc_agp_location)
  244.         {
  245.            u32_t d1crtc, d2crtc;
  246.            u32_t tmp;
  247. //           RADEONWaitForIdleMMIO(pScrn);
  248.  
  249.            OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
  250.            OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE);
  251.  
  252.            /* Stop display & memory access */
  253.            d1crtc = INREG(AVIVO_D1CRTC_CONTROL);
  254.            OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc & ~AVIVO_CRTC_EN);
  255.  
  256.            d2crtc = INREG(AVIVO_D2CRTC_CONTROL);
  257.            OUTREG(AVIVO_D2CRTC_CONTROL, d2crtc & ~AVIVO_CRTC_EN);
  258.  
  259.            tmp = INREG(AVIVO_D2CRTC_CONTROL);
  260.  
  261.            usleep(10000);
  262.            timeout = 0;
  263.            while (!(avivo_get_mc_idle(info)))
  264.            {
  265.               if (++timeout > 1000000)
  266.               {
  267.                  dbgprintf("Timeout trying to update memory controller settings !\n");
  268.                  dbgprintf("You will probably crash now ... \n");
  269.                /* Nothing we can do except maybe try to kill the server,
  270.                 * let's wait 2 seconds to leave the above message a chance
  271.                 * to maybe hit the disk and continue trying to setup despite
  272.                 * the MC being non-idle
  273.                 */
  274.                  usleep(2000000);
  275.               }
  276.               usleep(10);
  277.            }
  278.  
  279.            radeon_write_mc_fb_agp_location(info, LOC_FB | LOC_AGP,
  280.                            info->mc_fb_location,
  281.                            info->mc_agp_location,
  282.                            info->mc_agp_location_hi);
  283.  
  284.            if (info->ChipFamily < CHIP_FAMILY_R600) {
  285.               OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
  286.            }
  287.            else {
  288.               OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
  289.            }
  290.  
  291.            OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc );
  292.  
  293.            OUTREG(AVIVO_D2CRTC_CONTROL, d2crtc );
  294.  
  295.            tmp = INREG(AVIVO_D2CRTC_CONTROL);
  296.  
  297.            /* Reset the engine and HDP */
  298. //           RADEONEngineReset(pScrn);
  299.        }
  300.      }
  301.      else
  302.      {
  303.  
  304.         /* Write memory mapping registers only if their value change
  305.          * since we must ensure no access is done while they are
  306.          * reprogrammed
  307.          */
  308.         if ( mc_fb_loc != info->mc_fb_location   ||
  309.              mc_agp_loc != info->mc_agp_location)
  310.         {
  311.            u32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl;
  312.            u32_t old_mc_status, status_idle;
  313.  
  314.            dbgprintf("  Map Changed ! Applying ...\n");
  315.  
  316.             /* Make sure engine is idle. We assume the CCE is stopped
  317.              * at this point
  318.              */
  319.    //        RADEONWaitForIdleMMIO(info);
  320.  
  321.            if (info->IsIGP)
  322.               goto igp_no_mcfb;
  323.  
  324.             /* Capture MC_STATUS in case things go wrong ... */
  325.            old_mc_status = INREG(RADEON_MC_STATUS);
  326.  
  327.             /* Stop display & memory access */
  328.            ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
  329.            OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
  330.            crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
  331.            OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
  332.            crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
  333. //           RADEONWaitForVerticalSync(pScrn);
  334.            OUTREG(RADEON_CRTC_GEN_CNTL,
  335.                  (crtc_gen_cntl  & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN))
  336.                  | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
  337.  
  338.            if (info->HasCRTC2)
  339.            {
  340.               crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
  341. //              RADEONWaitForVerticalSync2(pScrn);
  342.               OUTREG(RADEON_CRTC2_GEN_CNTL, (crtc2_gen_cntl
  343.                      & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN))
  344.                     | RADEON_CRTC2_DISP_REQ_EN_B);
  345.            }
  346.  
  347.             /* Make sure the chip settles down (paranoid !) */
  348.            usleep(1000);
  349.  
  350.             /* Wait for MC idle */
  351.            if (IS_R300_VARIANT)
  352.               status_idle = R300_MC_IDLE;
  353.            else
  354.               status_idle = RADEON_MC_IDLE;
  355.  
  356.            timeout = 0;
  357.            while (!(INREG(RADEON_MC_STATUS) & status_idle))
  358.            {
  359.               if (++timeout > 1000000)
  360.               {
  361.                  dbgprintf("Timeout trying to update memory controller settings !\n");
  362.                  dbgprintf("MC_STATUS = 0x%08x (on entry = 0x%08x)\n",
  363.                            INREG(RADEON_MC_STATUS), old_mc_status);
  364.                  dbgprintf("You will probably crash now ... \n");
  365.                     /* Nothing we can do except maybe try to kill the server,
  366.                      * let's wait 2 seconds to leave the above message a chance
  367.                      * to maybe hit the disk and continue trying to setup despite
  368.                      * the MC being non-idle
  369.                      */
  370.                  usleep(20000);
  371.               }
  372.               usleep(10);
  373.            }
  374.  
  375.             /* Update maps, first clearing out AGP to make sure we don't get
  376.              * a temporary overlap
  377.              */
  378.            OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc);
  379.            OUTREG(RADEON_MC_FB_LOCATION, info->mc_fb_location);
  380.            radeon_write_mc_fb_agp_location(info, LOC_FB | LOC_AGP, info->mc_fb_location,
  381.                            0xfffffffc, 0);
  382.  
  383.            OUTREG(RADEON_CRTC_GEN_CNTL,crtc_gen_cntl );
  384.            OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  385.            OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl );
  386.  
  387.  
  388.  igp_no_mcfb:
  389.            radeon_write_mc_fb_agp_location(info, LOC_AGP, 0,
  390.                         info->mc_agp_location, 0);
  391.             /* Make sure map fully reached the chip */
  392.            (void)INREG(RADEON_MC_FB_LOCATION);
  393.  
  394.            dbgprintf("  Map applied, resetting engine ...\n");
  395.  
  396.             /* Reset the engine and HDP */
  397. //        RADEONEngineReset(pScrn);
  398.  
  399.             /* Make sure we have sane offsets before re-enabling the CRTCs, disable
  400.              * stereo, clear offsets, and wait for offsets to catch up with hw
  401.              */
  402.  
  403.            OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL);
  404.            OUTREG(RADEON_CRTC_OFFSET, 0);
  405.            OUTREG(RADEON_CUR_OFFSET, 0);
  406.            timeout = 0;
  407.            while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
  408.            {
  409.               if (timeout++ > 1000000) {
  410.                  dbgprintf("Timeout waiting for CRTC offset to update !\n");
  411.                  break;
  412.               }
  413.               usleep(1000);
  414.            }
  415.            if (info->HasCRTC2)
  416.            {
  417.               OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL);
  418.               OUTREG(RADEON_CRTC2_OFFSET, 0);
  419.               OUTREG(RADEON_CUR2_OFFSET, 0);
  420.               timeout = 0;
  421.               while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET)
  422.               {
  423.                  if (timeout++ > 1000000) {
  424.                     dbgprintf("Timeout waiting for CRTC2 offset to update !\n");
  425.                     break;
  426.                  }
  427.                  usleep(1000);
  428.               }
  429.            }
  430.         }
  431.  
  432.         dbgprintf("Updating display base addresses...\n");
  433.  
  434.         OUTREG(RADEON_DISPLAY_BASE_ADDR, info->fbLocation);
  435.         if (info->HasCRTC2)
  436.            OUTREG(RADEON_DISPLAY2_BASE_ADDR, info->fbLocation);
  437.         OUTREG(RADEON_OV0_BASE_ADDR, info->fbLocation);
  438.         (void)INREG(RADEON_OV0_BASE_ADDR);
  439.  
  440.         /* More paranoia delays, wait 100ms */
  441.         usleep(1000);
  442.  
  443.         dbgprintf("Memory map updated.\n");
  444.      };
  445. };
  446.  
  447.  
  448. static void RADEONInitMemoryMap(RHDPtr info)
  449. {
  450.      u32_t       mem_size;
  451.      u32_t       aper_size;
  452.  
  453.      radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location,
  454.                     &info->mc_agp_location, &info->mc_agp_location_hi);
  455.  
  456.       dbgprintf("  MC_FB_LOCATION   : 0x%08x\n", (unsigned)info->mc_fb_location);
  457.       dbgprintf("  MC_AGP_LOCATION  : 0x%08x\n", (unsigned)info->mc_agp_location);
  458.  
  459.  
  460.      /* We shouldn't use info->videoRam here which might have been clipped
  461.       * but the real video RAM instead
  462.       */
  463.      if (info->ChipFamily >= CHIP_FAMILY_R600){
  464.         mem_size = INREG(R600_CONFIG_MEMSIZE);
  465.         aper_size = INREG(R600_CONFIG_APER_SIZE);
  466.      }
  467.      else {
  468.         mem_size = INREG(RADEON_CONFIG_MEMSIZE);
  469.         aper_size = INREG(RADEON_CONFIG_APER_SIZE);
  470.      }
  471.  
  472.      if (mem_size == 0)
  473.         mem_size = 0x800000;
  474.  
  475.      /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
  476.         Novell bug 204882 + along with lots of ubuntu ones */
  477.      if (aper_size > mem_size)
  478.         mem_size = aper_size;
  479.  
  480.  
  481.      if ( (info->ChipFamily != CHIP_FAMILY_RS600) &&
  482.           (info->ChipFamily != CHIP_FAMILY_RS690) &&
  483.           (info->ChipFamily != CHIP_FAMILY_RS740)) {
  484.         if (info->IsIGP)
  485.            info->mc_fb_location = INREG(RADEON_NB_TOM);
  486.         else
  487.         {
  488.            u32_t aper0_base;
  489.  
  490.            if (info->ChipFamily >= CHIP_FAMILY_R600) {
  491.               aper0_base = INREG(R600_CONFIG_F0_BASE);
  492.            }
  493.            else {
  494.               aper0_base = INREG(RADEON_CONFIG_APER_0_BASE);
  495.            }
  496.            dbgprintf("aper0 base %x\n", aper0_base );
  497.  
  498.          /* Recent chips have an "issue" with the memory controller, the
  499.           * location must be aligned to the size. We just align it down,
  500.           * too bad if we walk over the top of system memory, we don't
  501.           * use DMA without a remapped anyway.
  502.           * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
  503.           */
  504.            if ( info->ChipFamily == CHIP_FAMILY_RV280 ||
  505.                 info->ChipFamily == CHIP_FAMILY_R300 ||
  506.                 info->ChipFamily == CHIP_FAMILY_R350 ||
  507.                 info->ChipFamily == CHIP_FAMILY_RV350 ||
  508.                 info->ChipFamily == CHIP_FAMILY_RV380 ||
  509.                 info->ChipFamily == CHIP_FAMILY_R420 ||
  510.                 info->ChipFamily == CHIP_FAMILY_RV410)
  511.               aper0_base &= ~(mem_size - 1);
  512.  
  513.            if ( info->ChipFamily >= CHIP_FAMILY_R600) {
  514.               info->mc_fb_location = (aper0_base >> 24) |
  515.               (((aper0_base + mem_size - 1) & 0xff000000U) >> 8);
  516.               dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
  517.            }
  518.            else {
  519.               info->mc_fb_location = (aper0_base >> 16) |
  520.               ((aper0_base + mem_size - 1) & 0xffff0000U);
  521.               dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location);
  522.            }
  523.         }
  524.      }
  525.      if (info->ChipFamily >= CHIP_FAMILY_R600) {
  526.         info->fbLocation = (info->mc_fb_location & 0xffff) << 24;
  527.      }
  528.      else {
  529.         info->fbLocation = (info->mc_fb_location & 0xffff) << 16;
  530.      }
  531.      /* Just disable the damn AGP apertures for now, it may be
  532.       * re-enabled later by the DRM
  533.       */
  534.  
  535. //     if (IS_AVIVO_VARIANT) {
  536. //        if (info->ChipFamily >= CHIP_FAMILY_R600) {
  537. //           OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
  538. //        }
  539. //        else {
  540. //           OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
  541. //        }
  542. //        info->mc_agp_location = 0x003f0000;
  543. //     }
  544. //     else
  545. //         info->mc_agp_location = 0xffffffc0;
  546.  
  547.       dbgprintf("RADEONInitMemoryMap() : \n");
  548.       dbgprintf("  mem_size         : 0x%08x\n", (u32_t)mem_size);
  549.       dbgprintf("  MC_FB_LOCATION   : 0x%08x\n", (unsigned)info->mc_fb_location);
  550.       dbgprintf("  MC_AGP_LOCATION  : 0x%08x\n", (unsigned)info->mc_agp_location);
  551.       dbgprintf("  FB_LOCATION   : 0x%08x\n", (unsigned)info->fbLocation);
  552.  
  553.       RADEONUpdateMemMapRegisters(info);
  554. }
  555.  
  556. static void RADEONGetVRamType(RHDPtr info)
  557. {
  558.      u32_t tmp;
  559.  
  560.      if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300))
  561.         info->IsDDR = TRUE;
  562.      else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
  563.         info->IsDDR = TRUE;
  564.      else
  565.         info->IsDDR = FALSE;
  566.  
  567.      if ( (info->ChipFamily >= CHIP_FAMILY_R600) &&
  568.           (info->ChipFamily <= CHIP_FAMILY_RV635))
  569.      {
  570.         int chansize;
  571.         /* r6xx */
  572.         tmp = INREG(R600_RAMCFG);
  573.         if (tmp & R600_CHANSIZE_OVERRIDE)
  574.             chansize = 16;
  575.         else if (tmp & R600_CHANSIZE)
  576.             chansize = 64;
  577.         else
  578.             chansize = 32;
  579.         if (info->ChipFamily == CHIP_FAMILY_R600)
  580.             info->RamWidth = 8 * chansize;
  581.         else if (info->ChipFamily == CHIP_FAMILY_RV670)
  582.             info->RamWidth = 4 * chansize;
  583.         else if ((info->ChipFamily == CHIP_FAMILY_RV610) ||
  584.              (info->ChipFamily == CHIP_FAMILY_RV620))
  585.             info->RamWidth = chansize;
  586.         else if ((info->ChipFamily == CHIP_FAMILY_RV630) ||
  587.              (info->ChipFamily == CHIP_FAMILY_RV635))
  588.             info->RamWidth = 2 * chansize;
  589.      }
  590.      else if (info->ChipFamily == CHIP_FAMILY_RV515) {
  591.      /* rv515/rv550 */
  592.         tmp = INMC(info, RV515_MC_CNTL);
  593.         tmp &= RV515_MEM_NUM_CHANNELS_MASK;
  594.         switch (tmp) {
  595.            case 0: info->RamWidth = 64; break;
  596.            case 1: info->RamWidth = 128; break;
  597.            default: info->RamWidth = 128; break;
  598.         }
  599.      }
  600.      else if ((info->ChipFamily >= CHIP_FAMILY_R520) &&
  601.               (info->ChipFamily <= CHIP_FAMILY_RV570)){
  602.      /* r520/rv530/rv560/rv570/r580 */
  603.         tmp = INMC(info, R520_MC_CNTL0);
  604.         switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
  605.            case 0: info->RamWidth = 32; break;
  606.            case 1: info->RamWidth = 64; break;
  607.            case 2: info->RamWidth = 128; break;
  608.            case 3: info->RamWidth = 256; break;
  609.            default: info->RamWidth = 64; break;
  610.         }
  611.         if (tmp & R520_MC_CHANNEL_SIZE) {
  612.            info->RamWidth *= 2;
  613.         }
  614.      }
  615.      else if ((info->ChipFamily >= CHIP_FAMILY_R300) &&
  616.               (info->ChipFamily <= CHIP_FAMILY_RV410)) {
  617.      /* r3xx, r4xx */
  618.         tmp = INREG(RADEON_MEM_CNTL);
  619.         tmp &= R300_MEM_NUM_CHANNELS_MASK;
  620.         switch (tmp) {
  621.            case 0: info->RamWidth = 64; break;
  622.            case 1: info->RamWidth = 128; break;
  623.            case 2: info->RamWidth = 256; break;
  624.            default: info->RamWidth = 128; break;
  625.         }
  626.      }
  627.      else if ((info->ChipFamily == CHIP_FAMILY_RV100) ||
  628.               (info->ChipFamily == CHIP_FAMILY_RS100) ||
  629.               (info->ChipFamily == CHIP_FAMILY_RS200)){
  630.      tmp = INREG(RADEON_MEM_CNTL);
  631.      if (tmp & RV100_HALF_MODE)
  632.         info->RamWidth = 32;
  633.      else
  634.         info->RamWidth = 64;
  635.  
  636.      if (!info->HasCRTC2) {
  637.           info->RamWidth /= 4;
  638.           info->IsDDR = TRUE;
  639.      }
  640.      }
  641.      else if (info->ChipFamily <= CHIP_FAMILY_RV280) {
  642.         tmp = INREG(RADEON_MEM_CNTL);
  643.      if (tmp & RADEON_MEM_NUM_CHANNELS_MASK)
  644.         info->RamWidth = 128;
  645.      else
  646.         info->RamWidth = 64;
  647.      } else {
  648.      /* newer IGPs */
  649.         info->RamWidth = 128;
  650.      }
  651.  
  652.      /* This may not be correct, as some cards can have half of channel disabled
  653.       * ToDo: identify these cases
  654.       */
  655. }
  656.  
  657. /*
  658.  * Depending on card genertation, chipset bugs, etc... the amount of vram
  659.  * accessible to the CPU can vary. This function is our best shot at figuring
  660.  * it out. Returns a value in KB.
  661.  */
  662. static u32_t RADEONGetAccessibleVRAM(RHDPtr info)
  663. {
  664.     u32_t       aper_size;
  665.     unsigned char  byte;
  666.  
  667.     if (info->ChipFamily >= CHIP_FAMILY_R600)
  668.        aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024;
  669.     else
  670.        aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024;
  671.  
  672.  
  673.     /* Set HDP_APER_CNTL only on cards that are known not to be broken,
  674.      * that is has the 2nd generation multifunction PCI interface
  675.      */
  676.     if (info->ChipFamily == CHIP_FAMILY_RV280 ||
  677.         info->ChipFamily == CHIP_FAMILY_RV350 ||
  678.         info->ChipFamily == CHIP_FAMILY_RV380 ||
  679.         info->ChipFamily == CHIP_FAMILY_R420  ||
  680.         info->ChipFamily == CHIP_FAMILY_RV410 ||
  681.         IS_AVIVO_VARIANT) {
  682.         MASKREG (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
  683.                      ~RADEON_HDP_APER_CNTL);
  684.         dbgprintf("Generation 2 PCI interface, using max accessible memory\n");
  685.             return aper_size * 2;
  686.     }
  687.  
  688.     /* Older cards have all sorts of funny issues to deal with. First
  689.      * check if it's a multifunction card by reading the PCI config
  690.      * header type... Limit those to one aperture size
  691.      */
  692.     byte = pciReadByte(info->PciTag, 0xe);
  693.     if (byte & 0x80) {
  694.        dbgprintf("Generation 1 PCI interface in multifunction mode, "
  695.                  "accessible memory limited to one aperture\n");
  696.        return aper_size;
  697.     }
  698.  
  699.     /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
  700.      * have set it up. We don't write this as it's broken on some ASICs but
  701.      * we expect the BIOS to have done the right thing (might be too optimistic...)
  702.      */
  703.     if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
  704.        return aper_size * 2;
  705.  
  706.     return aper_size;
  707. }
  708.  
  709. int RADEONDRIGetPciAperTableSize(RHDPtr info)
  710. {
  711.     int ret_size;
  712.     int num_pages;
  713.  
  714.     num_pages = (info->pciAperSize * 1024 * 1024) / 4096;
  715.  
  716.     ret_size = num_pages * sizeof(unsigned int);
  717.  
  718.     return ret_size;
  719. }
  720.  
  721. static Bool RADEONPreInitVRAM(RHDPtr info)
  722. {
  723.      u32_t accessible, bar_size;
  724.  
  725.      if ((!IS_AVIVO_VARIANT) && info->IsIGP)
  726.      {
  727.         u32_t tom = INREG(RADEON_NB_TOM);
  728.  
  729.         info->videoRam = (((tom >> 16) -
  730.                  (tom & 0xffff) + 1) << 6);
  731.  
  732.         OUTREG(RADEON_CONFIG_MEMSIZE, info->videoRam * 1024);
  733.      }
  734.      else
  735.      {
  736.         if (info->ChipFamily >= CHIP_FAMILY_R600)
  737.            info->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024;
  738.         else
  739.         {
  740.          /* Read VRAM size from card */
  741.            info->videoRam      = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
  742.  
  743.          /* Some production boards of m6 will return 0 if it's 8 MB */
  744.            if (info->videoRam == 0)
  745.            {
  746.               info->videoRam = 8192;
  747.               OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000);
  748.            }
  749.         }
  750.      }
  751.  
  752.      RADEONGetVRamType(info);
  753.  
  754.      /* Get accessible memory */
  755.      accessible = RADEONGetAccessibleVRAM(info);
  756.  
  757.      /* Crop it to the size of the PCI BAR */
  758. //     bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024;
  759.  
  760.      bar_size = 1 << (info->memsize[RHD_FB_BAR] - 10);
  761.  
  762.      if (bar_size == 0)
  763.         bar_size = 0x20000;
  764.      if (accessible > bar_size)
  765.         accessible = bar_size;
  766.  
  767.      dbgprintf("Detected total video RAM=%dK width=%dbit,"
  768.                 "accessible=%uK (PCI BAR=%uK)\n",
  769.                 info->videoRam, info->RamWidth,
  770.                 (unsigned)accessible, (unsigned)bar_size);
  771.  
  772.      if (info->videoRam > accessible)
  773.         info->videoRam = accessible;
  774.  
  775.      if (!IS_AVIVO_VARIANT)
  776.         info->MemCntl            = INREG(RADEON_SDRAM_MODE_REG);
  777.         info->BusCntl            = INREG(RADEON_BUS_CNTL);
  778.  
  779.      info->videoRam  &= ~1023;
  780.      info->FbMapSize  = info->videoRam * 1024;
  781.  
  782.      info->gartSize      = RADEON_DEFAULT_GART_SIZE;
  783.      info->ringSize      = RADEON_DEFAULT_RING_SIZE;
  784.      info->bufSize       = RADEON_DEFAULT_BUFFER_SIZE;
  785.  
  786.      info->gartTexSize   = info->gartSize - (info->ringSize + info->bufSize);
  787.  
  788.      info->pciAperSize   = RADEON_DEFAULT_PCI_APER_SIZE;
  789.      info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
  790.  
  791.  
  792.  
  793.      /* if the card is PCI Express reserve the last 32k for the gart table */
  794.  
  795.  //    if (info->cardType == CARD_PCIE )
  796.  //     /* work out the size of pcie aperture */
  797.  //       info->FbSecureSize = RADEONDRIGetPciAperTableSize(info);
  798.  //    else
  799.  //       info->FbSecureSize = 0;
  800.  
  801.      return TRUE;
  802. }
  803.  
  804.  
  805. static Bool RADEONPreInitChipType(RHDPtr rhdPtr)
  806. {
  807.      u32_t cmd_stat;
  808.  
  809.      rhdPtr->ChipErrata = 0;
  810.  
  811.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) &&
  812.           ((_RHDRegRead(rhdPtr,RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
  813.            == RADEON_CFG_ATI_REV_A11))
  814.         rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG;
  815.  
  816.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) ||
  817.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
  818.         rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS;
  819.  
  820.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) ||
  821.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
  822.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) )
  823.         rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY;
  824.  
  825.      rhdPtr->cardType = CARD_PCI;
  826.  
  827.  
  828.      cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG);
  829.  
  830.      if (cmd_stat & RADEON_CAP_LIST)
  831.      {
  832.         u32_t cap_ptr, cap_id;
  833.  
  834.         cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG);
  835.         cap_ptr &= RADEON_CAP_PTR_MASK;
  836.  
  837.         while(cap_ptr != RADEON_CAP_ID_NULL)
  838.         {
  839.            cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr);
  840.            if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) {
  841.               rhdPtr->cardType = CARD_AGP;
  842.               break;
  843.            }
  844.            if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) {
  845.               rhdPtr->cardType = CARD_PCIE;
  846.               break;
  847.            }
  848.            cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK;
  849.         }
  850.      }
  851.  
  852.      dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" :
  853.                (rhdPtr->cardType==CARD_PCIE) ? "PCIE" : "AGP");
  854.  
  855.     /* treat PCIE IGP cards as PCI  */
  856.      if (rhdPtr->cardType == CARD_PCIE && rhdPtr->IsIGP)
  857.          rhdPtr->cardType = CARD_PCI;
  858.  
  859.      if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) ||
  860.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ||
  861.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS300) ||
  862.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS400) ||
  863.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS480) ||
  864.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS600) ||
  865.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS690) ||
  866.           (rhdPtr->ChipFamily == CHIP_FAMILY_RS740))
  867.         rhdPtr->has_tcl = FALSE;
  868.      else {
  869.         rhdPtr->has_tcl = TRUE;
  870.      }
  871.  
  872.      rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR];
  873.  
  874.      return TRUE;
  875. }
  876.  
  877. #if 0
  878. static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen)
  879. {
  880.     unsigned char *RADEONMMIO = info->MMIO;
  881. //    unsigned long mode   = drmAgpGetMode(info->dri->drmFD); /* Default mode */
  882. //    unsigned int  vendor = drmAgpVendorId(info->dri->drmFD);
  883. //    unsigned int  device = drmAgpDeviceId(info->dri->drmFD);
  884.     /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with
  885.        pcie-agp rialto bridge chip - use the one from bridge which must match */
  886.     uint32_t agp_status = (INREG(RADEON_AGP_STATUS) ); // & RADEON_AGP_MODE_MASK;
  887.     Bool is_v3 = (agp_status & RADEON_AGPv3_MODE);
  888.     unsigned int defaultMode;
  889.  
  890.     if (is_v3) {
  891.        defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
  892.     } else {
  893.         if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4;
  894.         else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2;
  895.         else defaultMode = 1;
  896.     }
  897.  
  898.    // agpMode = defaultMode;
  899.  
  900.     dbgprintf(pScreen->myNum, from, "Using AGP %dx\n", dbgprintf);
  901.  
  902.     mode &= ~RADEON_AGP_MODE_MASK;
  903.     if (is_v3) {
  904.         /* only set one mode bit for AGPv3 */
  905.     switch (defaultMode) {
  906.         case 8:          mode |= RADEON_AGPv3_8X_MODE; break;
  907.         case 4: default: mode |= RADEON_AGPv3_4X_MODE;
  908.         }
  909.         /*TODO: need to take care of other bits valid for v3 mode
  910.          *      currently these bits are not used in all tested cards.
  911.          */
  912.     } else {
  913.     switch (defaultMode) {
  914.         case 4:          mode |= RADEON_AGP_4X_MODE;
  915.         case 2:          mode |= RADEON_AGP_2X_MODE;
  916.         case 1: default: mode |= RADEON_AGP_1X_MODE;
  917.         }
  918.     }
  919.  
  920.     /* AGP Fast Writes.
  921.      * TODO: take into account that certain agp modes don't support fast
  922.      * writes at all */
  923.     mode &= ~RADEON_AGP_FW_MODE; /* Disable per default */
  924.  
  925.     dbgprintf("AGP Mode 0x%08lx\n", mode);
  926.  
  927.     if (drmAgpEnable(info->dri->drmFD, mode) < 0) {
  928.         xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP not enabled\n");
  929.         drmAgpRelease(info->dri->drmFD);
  930.         return FALSE;
  931.     }
  932.  
  933.     /* Workaround for some hardware bugs */
  934.     if (info->ChipFamily < CHIP_FAMILY_R200)
  935.         OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000);
  936.  
  937.                                 /* Modify the mode if the default mode
  938.                                  * is not appropriate for this
  939.                                  * particular combination of graphics
  940.                                  * card and AGP chipset.
  941.                                  */
  942.  
  943.     return TRUE;
  944. }
  945. #endif
  946.  
  947. Bool RHDPreInit()
  948. {
  949.     RHDPtr info;
  950.  
  951.     /* We need access to IO space already */
  952.      if ( !rhdMapMMIO(&rhd) ) {
  953.         dbgprintf("Failed to map MMIO.\n");
  954.         return FALSE;
  955.      };
  956.  
  957.  
  958.      if( !RADEONPreInitChipType(&rhd))
  959.         return FALSE;
  960.  
  961.      if (!RADEONPreInitVRAM(&rhd))
  962.         return FALSE;
  963.  
  964.      RADEONInitMemoryMap(&rhd);
  965.  
  966.      if (!rhd.videoRam)
  967.      {
  968.         dbgprintf("No Video RAM detected.\n");
  969.         goto error1;
  970.      }
  971.      dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam);
  972.  
  973.  //    rhd.FbFreeStart = 0;
  974.      rhd.FbFreeSize = rhd.videoRam << 10;
  975.  
  976.  // if( !rhdMapFB(&rhd))
  977. //    return FALSE;
  978.  
  979. //  rhd.FbScanoutStart = 0;
  980. //  rhd.FbScanoutSize  = 8*1024*1024;
  981.  
  982.   rhd.FbFreeStart    = 10*1024*1024;
  983.   rhd.FbFreeSize     = rhd.FbMapSize - rhd.FbFreeStart - rhd.FbSecureSize;
  984.  
  985.   rhdInitHeap(&rhd);
  986.  
  987.      info = &rhd;
  988.  
  989.  
  990.    return TRUE;
  991.  
  992. error1:
  993.   return FALSE;
  994. };
  995.  
  996.  
  997.  
  998.