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  1. /*
  2.  * Copyright © 2010 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *    Xiang Haihao <haihao.xiang@intel.com>
  26.  *
  27.  */
  28.  
  29. #ifndef __I965_POST_PROCESSING_H__
  30. #define __I965_POST_PROCESSING_H__
  31.  
  32. #define MAX_PP_SURFACES  48
  33.  
  34. #define I965_PP_FLAG_TOP_FIELD                 1
  35. #define I965_PP_FLAG_BOTTOM_FIELD              2
  36.  
  37. #define I965_PP_FLAG_AVS                       4
  38. #define I965_PP_FLAG_DEINTERLACING             8
  39.  
  40. enum
  41. {
  42.     PP_NULL = 0,
  43.     PP_NV12_LOAD_SAVE_N12,
  44.     PP_NV12_LOAD_SAVE_PL3,
  45.     PP_PL3_LOAD_SAVE_N12,
  46.     PP_PL3_LOAD_SAVE_PL3,
  47.     PP_NV12_SCALING,
  48.     PP_NV12_AVS,
  49.     PP_NV12_DNDI,
  50.     PP_NV12_DN,
  51.     PP_NV12_LOAD_SAVE_PA,
  52.     PP_PL3_LOAD_SAVE_PA,
  53.     PP_PA_LOAD_SAVE_NV12,
  54.     NUM_PP_MODULES,
  55. };
  56.  
  57. struct pp_load_save_context
  58. {
  59.     int dest_x;
  60.     int dest_y;
  61.     int dest_w;
  62.     int dest_h;
  63. };
  64.  
  65. struct pp_scaling_context
  66. {
  67.     int dest_x; /* in pixel */
  68.     int dest_y; /* in pixel */
  69.     int dest_w;
  70.     int dest_h;
  71.     int src_normalized_x;
  72.     int src_normalized_y;
  73. };
  74.  
  75. struct pp_avs_context
  76. {
  77.     int dest_x; /* in pixel */
  78.     int dest_y; /* in pixel */
  79.     int dest_w;
  80.     int dest_h;
  81.     int src_normalized_x;
  82.     int src_normalized_y;
  83.     int src_w;
  84.     int src_h;
  85. };
  86.  
  87. struct pp_dndi_context
  88. {
  89.     int dest_w;
  90.     int dest_h;
  91. };
  92.  
  93. struct pp_dn_context
  94. {
  95.     int dest_w;
  96.     int dest_h;
  97. };
  98.  
  99. struct i965_post_processing_context;
  100.  
  101. struct pp_module
  102. {
  103.     struct i965_kernel kernel;
  104.    
  105.     /* others */
  106.     VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
  107.                        const struct i965_surface *src_surface,
  108.                        const VARectangle *src_rect,
  109.                        struct i965_surface *dst_surface,
  110.                        const VARectangle *dst_rect,
  111.                        void *filter_param);
  112. };
  113.  
  114. struct pp_static_parameter
  115. {
  116.     struct {
  117.         /* Procamp r1.0 */
  118.         float procamp_constant_c0;
  119.        
  120.         /* Load and Same r1.1 */
  121.         unsigned int source_packed_y_offset:8;
  122.         unsigned int source_packed_u_offset:8;
  123.         unsigned int source_packed_v_offset:8;
  124.         unsigned int pad0:8;
  125.  
  126.         union {
  127.             /* Load and Save r1.2 */
  128.             struct {
  129.                 unsigned int destination_packed_y_offset:8;
  130.                 unsigned int destination_packed_u_offset:8;
  131.                 unsigned int destination_packed_v_offset:8;
  132.                 unsigned int pad0:8;
  133.             } load_and_save;
  134.  
  135.             /* CSC r1.2 */
  136.             struct {
  137.                 unsigned int destination_rgb_format:8;
  138.                 unsigned int pad0:24;
  139.             } csc;
  140.         } r1_2;
  141.        
  142.         /* Procamp r1.3 */
  143.         float procamp_constant_c1;
  144.  
  145.         /* Procamp r1.4 */
  146.         float procamp_constant_c2;
  147.  
  148.         /* DI r1.5 */
  149.         unsigned int statistics_surface_picth:16;  /* Devided by 2 */
  150.         unsigned int pad1:16;
  151.  
  152.         union {
  153.             /* DI r1.6 */
  154.             struct {
  155.                 unsigned int pad0:24;
  156.                 unsigned int top_field_first:8;
  157.             } di;
  158.  
  159.             /* AVS/Scaling r1.6 */
  160.             float normalized_video_y_scaling_step;
  161.         } r1_6;
  162.  
  163.         /* Procamp r1.7 */
  164.         float procamp_constant_c5;
  165.     } grf1;
  166.    
  167.     struct {
  168.         /* Procamp r2.0 */
  169.         float procamp_constant_c3;
  170.  
  171.         /* MBZ r2.1*/
  172.         unsigned int pad0;
  173.  
  174.         /* WG+CSC r2.2 */
  175.         float wg_csc_constant_c4;
  176.  
  177.         /* WG+CSC r2.3 */
  178.         float wg_csc_constant_c8;
  179.  
  180.         /* Procamp r2.4 */
  181.         float procamp_constant_c4;
  182.  
  183.         /* MBZ r2.5 */
  184.         unsigned int pad1;
  185.  
  186.         /* MBZ r2.6 */
  187.         unsigned int pad2;
  188.  
  189.         /* WG+CSC r2.7 */
  190.         float wg_csc_constant_c9;
  191.     } grf2;
  192.  
  193.     struct {
  194.         /* WG+CSC r3.0 */
  195.         float wg_csc_constant_c0;
  196.  
  197.         /* Blending r3.1 */
  198.         float scaling_step_ratio;
  199.  
  200.         /* Blending r3.2 */
  201.         float normalized_alpha_y_scaling;
  202.        
  203.         /* WG+CSC r3.3 */
  204.         float wg_csc_constant_c4;
  205.  
  206.         /* WG+CSC r3.4 */
  207.         float wg_csc_constant_c1;
  208.  
  209.         /* ALL r3.5 */
  210.         int horizontal_origin_offset:16;
  211.         int vertical_origin_offset:16;
  212.  
  213.         /* Shared r3.6*/
  214.         union {
  215.             /* Color filll */
  216.             unsigned int color_pixel;
  217.  
  218.             /* WG+CSC */
  219.             float wg_csc_constant_c2;
  220.         } r3_6;
  221.  
  222.         /* WG+CSC r3.7 */
  223.         float wg_csc_constant_c3;
  224.     } grf3;
  225.  
  226.     struct {
  227.         /* WG+CSC r4.0 */
  228.         float wg_csc_constant_c6;
  229.  
  230.         /* ALL r4.1 MBZ ???*/
  231.         unsigned int pad0;
  232.  
  233.         /* Shared r4.2 */
  234.         union {
  235.             /* AVS */
  236.             struct {
  237.                 unsigned int pad1:15;
  238.                 unsigned int nlas:1;
  239.                 unsigned int pad2:16;
  240.             } avs;
  241.  
  242.             /* DI */
  243.             struct {
  244.                 unsigned int motion_history_coefficient_m2:8;
  245.                 unsigned int motion_history_coefficient_m1:8;
  246.                 unsigned int pad0:16;
  247.             } di;
  248.         } r4_2;
  249.  
  250.         /* WG+CSC r4.3 */
  251.         float wg_csc_constant_c7;
  252.  
  253.         /* WG+CSC r4.4 */
  254.         float wg_csc_constant_c10;
  255.  
  256.         /* AVS r4.5 */
  257.         float source_video_frame_normalized_horizontal_origin;
  258.  
  259.         /* MBZ r4.6 */
  260.         unsigned int pad1;
  261.  
  262.         /* WG+CSC r4.7 */
  263.         float wg_csc_constant_c11;
  264.     } grf4;
  265. };
  266.  
  267. struct pp_inline_parameter
  268. {
  269.     struct {
  270.         /* ALL r5.0 */
  271.         int destination_block_horizontal_origin:16;
  272.         int destination_block_vertical_origin:16;
  273.  
  274.         /* Shared r5.1 */
  275.         union {
  276.             /* AVS/Scaling */
  277.             float source_surface_block_normalized_horizontal_origin;
  278.  
  279.             /* FMD */
  280.             struct {
  281.                 unsigned int variance_surface_vertical_origin:16;
  282.                 unsigned int pad0:16;
  283.             } fmd;
  284.         } r5_1;
  285.  
  286.         /* AVS/Scaling r5.2 */
  287.         float source_surface_block_normalized_vertical_origin;
  288.  
  289.         /* Alpha r5.3 */
  290.         float alpha_surface_block_normalized_horizontal_origin;
  291.  
  292.         /* Alpha r5.4 */
  293.         float alpha_surface_block_normalized_vertical_origin;
  294.  
  295.         /* Alpha r5.5 */
  296.         unsigned int alpha_mask_x:16;
  297.         unsigned int alpha_mask_y:8;
  298.         unsigned int block_count_x:8;
  299.  
  300.         /* r5.6 */
  301.         /* we only support M*1 or 1*N block partitation now.
  302.          *   -- it means asm code only need update this mask from grf6 for the last block
  303.          */
  304.         unsigned int block_horizontal_mask:16;
  305.         unsigned int block_vertical_mask:8;
  306.         unsigned int number_blocks:8;
  307.  
  308.         /* AVS/Scaling r5.7 */
  309.         float normalized_video_x_scaling_step;
  310.     } grf5;
  311.  
  312.     struct {
  313.         /* AVS r6.0 */
  314.         float video_step_delta;
  315.  
  316.         /* r6.1 */    // sizeof(int) == 4?    
  317.         unsigned int block_horizontal_mask_right:16;
  318.         unsigned int block_vertical_mask_bottom:8;
  319.         unsigned int pad1:8;
  320.  
  321.         /* r6.2 */
  322.         unsigned int block_horizontal_mask_middle:16;
  323.         unsigned int pad2:16;
  324.  
  325.         /* r6.3-r6.7 */
  326.         unsigned int padx[5];
  327.     } grf6;
  328. };
  329.  
  330. struct gen7_pp_static_parameter
  331. {
  332.     struct {
  333.         /* r1.0-r1.5 */
  334.         unsigned int padx[6];
  335.         /* r1.6 */
  336.         unsigned int di_statistics_surface_pitch_div2:16;
  337.         unsigned int di_statistics_surface_height_div4:16;
  338.         /* r1.7 */
  339.         unsigned int di_top_field_first:8;
  340.         unsigned int pad0:16;
  341.         unsigned int pointer_to_inline_parameter:8; /* value: 7 */
  342.     } grf1;
  343.  
  344.     struct {
  345.         /* r2.0 */
  346.         unsigned int pad3;
  347.  
  348.         /* r2.1 */
  349.         unsigned int pad2:16;
  350.         unsigned int save_avs_rgb_swap:1; /* 0: RGB, 1: BGR */
  351.         unsigned int avs_wa_enable:1; /* must enabled for GEN7 */
  352.         unsigned int pad1:1;
  353.         unsigned int avs_wa_width:13;
  354.  
  355.         /* 2.2 */
  356.         float avs_wa_one_div_256_width;
  357.  
  358.         /* 2.3 */
  359.         float avs_wa_five_div_256_width;
  360.        
  361.         /* 2.4 - 2.6 */
  362.         unsigned int padx[3];
  363.  
  364.         /* r2.7 */
  365.         unsigned int di_destination_packed_y_component_offset:8;
  366.         unsigned int di_destination_packed_u_component_offset:8;
  367.         unsigned int di_destination_packed_v_component_offset:8;
  368.         unsigned int pad0:8;
  369.     } grf2;
  370.  
  371.     struct {
  372.         float sampler_load_horizontal_scaling_step_ratio;
  373.         unsigned int padx[7];
  374.     } grf3;
  375.  
  376.     struct {
  377.         float sampler_load_vertical_scaling_step;
  378.         unsigned int pad0;
  379.         unsigned int di_hoffset_svf_from_dvf:16;
  380.         unsigned int di_voffset_svf_from_dvf:16;
  381.         unsigned int padx[5];
  382.     } grf4;
  383.  
  384.     struct {
  385.         float sampler_load_vertical_frame_origin;
  386.         unsigned int padx[7];
  387.     } grf5;
  388.  
  389.     struct {
  390.         float sampler_load_horizontal_frame_origin;
  391.         unsigned int padx[7];
  392.     } grf6;
  393. };
  394.  
  395. struct gen7_pp_inline_parameter
  396. {
  397.     struct {
  398.         /* r7.0 */
  399.         unsigned int destination_block_horizontal_origin:16;
  400.         unsigned int destination_block_vertical_origin:16;
  401.         /* r7.1: 0xffffffff */
  402.         unsigned int constant_0;
  403.         /* r7.2 */
  404.         unsigned int pad0;
  405.         /* r7.3 */
  406.         unsigned int pad1;
  407.         /* r7.4 */
  408.         float sampler_load_main_video_x_scaling_step;
  409.         /* r7.5 */
  410.         unsigned int pad2;
  411.         /* r7.6: must be zero */
  412.         unsigned int avs_vertical_block_number;
  413.         /* r7.7: 0 */
  414.         unsigned int group_id_number;
  415.     } grf7;
  416.  
  417.     struct {
  418.         unsigned int padx[8];
  419.     } grf8;
  420. };
  421.  
  422. struct i965_post_processing_context
  423. {
  424.     int current_pp;
  425.     struct pp_module pp_modules[NUM_PP_MODULES];
  426.     void *pp_static_parameter;
  427.     void *pp_inline_parameter;
  428.  
  429.     struct {
  430.         dri_bo *bo;
  431.     } surface_state_binding_table;
  432.  
  433.     struct {
  434.         dri_bo *bo;
  435.     } curbe;
  436.  
  437.     struct {
  438.         dri_bo *bo;
  439.         int num_interface_descriptors;
  440.     } idrt;
  441.  
  442.     struct {
  443.         dri_bo *bo;
  444.     } vfe_state;
  445.  
  446.     struct {
  447.         dri_bo *bo;
  448.         dri_bo *bo_8x8;
  449.         dri_bo *bo_8x8_uv;
  450.     } sampler_state_table;
  451.  
  452.     struct {
  453.         unsigned int size;
  454.  
  455.         unsigned int vfe_start;
  456.         unsigned int cs_start;
  457.  
  458.         unsigned int num_vfe_entries;
  459.         unsigned int num_cs_entries;
  460.  
  461.         unsigned int size_vfe_entry;
  462.         unsigned int size_cs_entry;
  463.     } urb;
  464.  
  465.     struct {
  466.         dri_bo *bo;
  467.     } stmm;
  468.  
  469.     union {
  470.         struct pp_load_save_context pp_load_save_context;
  471.         struct pp_scaling_context pp_scaling_context;
  472.         struct pp_avs_context pp_avs_context;
  473.         struct pp_dndi_context pp_dndi_context;
  474.         struct pp_dn_context pp_dn_context;
  475.     } private_context;
  476.  
  477.     int (*pp_x_steps)(void *private_context);
  478.     int (*pp_y_steps)(void *private_context);
  479.     int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
  480.     struct intel_batchbuffer *batch;
  481.     unsigned int block_horizontal_mask_left:16;
  482.     unsigned int block_horizontal_mask_right:16;
  483.     unsigned int block_vertical_mask_bottom:8;
  484.  
  485.     /* video process based on hsw vebox */
  486.     struct intel_vebox_context *pp_vebox_context;
  487. };
  488.  
  489. VASurfaceID
  490. i965_post_processing(
  491.     VADriverContextP   ctx,
  492.     VASurfaceID        surface,
  493.     const VARectangle *src_rect,
  494.     const VARectangle *dst_rect,
  495.     unsigned int       flags,
  496.     int                *has_done_scaling
  497. );
  498.  
  499. VAStatus
  500. i965_image_processing(VADriverContextP ctx,
  501.                       const struct i965_surface *src_surface,
  502.                       const VARectangle *src_rect,
  503.                       struct i965_surface *dst_surface,
  504.                       const VARectangle *dst_rect);
  505.  
  506. Bool
  507. i965_post_processing_terminate(VADriverContextP ctx);
  508. Bool
  509. i965_post_processing_init(VADriverContextP ctx);
  510.  
  511. #endif /* __I965_POST_PROCESSING_H__ */
  512.