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  1. /*
  2.  * Copyright © 2010 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the
  6.  * "Software"), to deal in the Software without restriction, including
  7.  * without limitation the rights to use, copy, modify, merge, publish,
  8.  * distribute, sub license, and/or sell copies of the Software, and to
  9.  * permit persons to whom the Software is furnished to do so, subject to
  10.  * the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice (including the
  13.  * next paragraph) shall be included in all copies or substantial portions
  14.  * of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17.  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18.  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19.  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20.  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21.  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22.  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors:
  25.  *    Xiang Haihao <haihao.xiang@intel.com>
  26.  *
  27.  */
  28.  
  29. #include <stdio.h>
  30. #include <string.h>
  31. #include <assert.h>
  32.  
  33.  
  34. #include "intel_batchbuffer.h"
  35. #include "intel_driver.h"
  36.  
  37. #include "i965_defines.h"
  38. #include "i965_drv_video.h"
  39. #include "i965_avc_ildb.h"
  40. #include "i965_media_h264.h"
  41. #include "i965_media.h"
  42.  
  43. /* On Cantiga */
  44. #include "shaders/h264/mc/export.inc"
  45.  
  46. /* On Ironlake */
  47. #include "shaders/h264/mc/export.inc.gen5"
  48.  
  49. #define PICTURE_FRAME   0
  50. #define PICTURE_FIELD   1
  51. #define PICTURE_MBAFF   2
  52.  
  53. enum {
  54.     AVC_ILDB_ROOT_Y_ILDB_FRAME,
  55.     AVC_ILDB_CHILD_Y_ILDB_FRAME,
  56.     AVC_ILDB_ROOT_UV_ILDB_FRAME,
  57.     AVC_ILDB_CHILD_UV_ILDB_FRAME,
  58.     AVC_ILDB_ROOT_Y_ILDB_FIELD,
  59.     AVC_ILDB_CHILD_Y_ILDB_FIELD,
  60.     AVC_ILDB_ROOT_UV_ILDB_FIELD,
  61.     AVC_ILDB_CHILD_UV_ILDB_FIELD,
  62.     AVC_ILDB_ROOT_Y_ILDB_MBAFF,
  63.     AVC_ILDB_CHILD_Y_ILDB_MBAFF,
  64.     AVC_ILDB_ROOT_UV_ILDB_MBAFF,
  65.     AVC_ILDB_CHILD_UV_ILDB_MBAFF
  66. };
  67.  
  68. static unsigned long avc_ildb_kernel_offset_gen4[] = {
  69.     AVC_ILDB_ROOT_Y_ILDB_FRAME_IP * INST_UNIT_GEN4,
  70.     AVC_ILDB_CHILD_Y_ILDB_FRAME_IP * INST_UNIT_GEN4,
  71.     AVC_ILDB_ROOT_UV_ILDB_FRAME_IP * INST_UNIT_GEN4,
  72.     AVC_ILDB_CHILD_UV_ILDB_FRAME_IP * INST_UNIT_GEN4,
  73.     AVC_ILDB_ROOT_Y_ILDB_FIELD_IP * INST_UNIT_GEN4,
  74.     AVC_ILDB_CHILD_Y_ILDB_FIELD_IP * INST_UNIT_GEN4,
  75.     AVC_ILDB_ROOT_UV_ILDB_FIELD_IP * INST_UNIT_GEN4,
  76.     AVC_ILDB_CHILD_UV_ILDB_FIELD_IP * INST_UNIT_GEN4,
  77.     AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4,
  78.     AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP * INST_UNIT_GEN4,
  79.     AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4,
  80.     AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP * INST_UNIT_GEN4
  81. };
  82.  
  83. static unsigned long avc_ildb_kernel_offset_gen5[] = {
  84.     AVC_ILDB_ROOT_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  85.     AVC_ILDB_CHILD_Y_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  86.     AVC_ILDB_ROOT_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  87.     AVC_ILDB_CHILD_UV_ILDB_FRAME_IP_GEN5 * INST_UNIT_GEN5,
  88.     AVC_ILDB_ROOT_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  89.     AVC_ILDB_CHILD_Y_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  90.     AVC_ILDB_ROOT_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  91.     AVC_ILDB_CHILD_UV_ILDB_FIELD_IP_GEN5 * INST_UNIT_GEN5,
  92.     AVC_ILDB_ROOT_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
  93.     AVC_ILDB_CHILD_Y_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
  94.     AVC_ILDB_ROOT_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5,
  95.     AVC_ILDB_CHILD_UV_ILDB_MBAFF_IP_GEN5 * INST_UNIT_GEN5
  96. };
  97.  
  98. struct avc_ildb_root_input
  99. {
  100.     unsigned int blocks_per_row : 16;
  101.     unsigned int blocks_per_column : 16;
  102.  
  103.     unsigned int picture_type : 16;
  104.     unsigned int max_concurrent_threads : 16;
  105.  
  106.     unsigned int debug_field : 16;
  107.     unsigned int mbaff_frame_flag : 1;
  108.     unsigned int bottom_field_flag : 1;
  109.     unsigned int control_data_expansion_flag : 1;
  110.     unsigned int chroma_format : 1;
  111.     unsigned int pad0 : 12;
  112.  
  113.     unsigned int ramp_constant_0;
  114.    
  115.     unsigned int ramp_constant_1;
  116.  
  117.     int constant_0 : 8;
  118.     int constant_1 : 8;
  119.     int pad1 : 16;
  120.  
  121.     unsigned int pad2;
  122.     unsigned int pad3;
  123. };
  124.  
  125. #define NUM_AVC_ILDB_INTERFACES ARRAY_ELEMS(avc_ildb_kernel_offset_gen4)
  126. static unsigned long *avc_ildb_kernel_offset = NULL;
  127.  
  128. static void
  129. i965_avc_ildb_surface_state(VADriverContextP ctx,
  130.                             struct decode_state *decode_state,
  131.                             struct i965_h264_context *i965_h264_context)
  132. {
  133.     struct i965_driver_data *i965 = i965_driver_data(ctx);
  134.     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
  135.     struct i965_surface_state *ss;
  136.     struct object_surface *obj_surface;
  137.     VAPictureParameterBufferH264 *pic_param;
  138.     VAPictureH264 *va_pic;
  139.     dri_bo *bo;
  140.     int i;
  141.  
  142.     assert(decode_state->pic_param && decode_state->pic_param->buffer);
  143.     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
  144.     va_pic = &pic_param->CurrPic;
  145.     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
  146.     obj_surface = SURFACE(va_pic->picture_id);
  147.     assert(obj_surface);
  148.  
  149.     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo = i965_h264_context->avc_ildb_data.bo;
  150.     dri_bo_reference(avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].s_bo);
  151.     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].offset = 0;
  152.     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].surface_type = I965_SURFACE_BUFFER;
  153.     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].width = ((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) & 0x7f);
  154.     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].height = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 7) & 0x1fff);
  155.     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].depth = (((avc_ildb_context->mbs_per_picture * EDGE_CONTROL_DATA_IN_DWS - 1) >> 20) & 0x7f);
  156.     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].pitch = EDGE_CONTROL_DATA_IN_BTYES - 1;
  157.     avc_ildb_context->surface[SURFACE_EDGE_CONTROL_DATA].is_target = 0;
  158.    
  159.     avc_ildb_context->surface[SURFACE_SRC_Y].s_bo = obj_surface->bo;
  160.     dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_Y].s_bo);
  161.     avc_ildb_context->surface[SURFACE_SRC_Y].offset = 0;
  162.     avc_ildb_context->surface[SURFACE_SRC_Y].surface_type = I965_SURFACE_2D;
  163.     avc_ildb_context->surface[SURFACE_SRC_Y].format = I965_SURFACEFORMAT_R8_SINT;
  164.     avc_ildb_context->surface[SURFACE_SRC_Y].width = obj_surface->width / 4 - 1;
  165.     avc_ildb_context->surface[SURFACE_SRC_Y].height = obj_surface->height - 1;
  166.     avc_ildb_context->surface[SURFACE_SRC_Y].depth = 0;
  167.     avc_ildb_context->surface[SURFACE_SRC_Y].pitch = obj_surface->width - 1;
  168.     avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
  169.     avc_ildb_context->surface[SURFACE_SRC_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
  170.     avc_ildb_context->surface[SURFACE_SRC_Y].is_target = 0;
  171.    
  172.     avc_ildb_context->surface[SURFACE_SRC_UV].s_bo = obj_surface->bo;
  173.     dri_bo_reference(avc_ildb_context->surface[SURFACE_SRC_UV].s_bo);
  174.     avc_ildb_context->surface[SURFACE_SRC_UV].offset = obj_surface->width * obj_surface->height;
  175.     avc_ildb_context->surface[SURFACE_SRC_UV].surface_type = I965_SURFACE_2D;
  176.     avc_ildb_context->surface[SURFACE_SRC_UV].format = I965_SURFACEFORMAT_R8G8_SINT;
  177.     avc_ildb_context->surface[SURFACE_SRC_UV].width = obj_surface->width / 4 - 1;
  178.     avc_ildb_context->surface[SURFACE_SRC_UV].height = obj_surface->height / 2 - 1;
  179.     avc_ildb_context->surface[SURFACE_SRC_UV].depth = 0;
  180.     avc_ildb_context->surface[SURFACE_SRC_UV].pitch = obj_surface->width - 1;
  181.     avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
  182.     avc_ildb_context->surface[SURFACE_SRC_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
  183.     avc_ildb_context->surface[SURFACE_SRC_UV].is_target = 0;
  184.  
  185.     avc_ildb_context->surface[SURFACE_DEST_Y].s_bo = obj_surface->bo;
  186.     dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_Y].s_bo);
  187.     avc_ildb_context->surface[SURFACE_DEST_Y].offset = 0;
  188.     avc_ildb_context->surface[SURFACE_DEST_Y].surface_type = I965_SURFACE_2D;
  189.     avc_ildb_context->surface[SURFACE_DEST_Y].format = I965_SURFACEFORMAT_R8_SINT;
  190.     avc_ildb_context->surface[SURFACE_DEST_Y].width = obj_surface->width / 4 - 1;
  191.     avc_ildb_context->surface[SURFACE_DEST_Y].height = obj_surface->height - 1;
  192.     avc_ildb_context->surface[SURFACE_DEST_Y].depth = 0;
  193.     avc_ildb_context->surface[SURFACE_DEST_Y].pitch = obj_surface->width - 1;
  194.     avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
  195.     avc_ildb_context->surface[SURFACE_DEST_Y].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
  196.     avc_ildb_context->surface[SURFACE_DEST_Y].is_target = 1;
  197.  
  198.     avc_ildb_context->surface[SURFACE_DEST_UV].s_bo = obj_surface->bo;
  199.     dri_bo_reference(avc_ildb_context->surface[SURFACE_DEST_UV].s_bo);
  200.     avc_ildb_context->surface[SURFACE_DEST_UV].offset = obj_surface->width * obj_surface->height;
  201.     avc_ildb_context->surface[SURFACE_DEST_UV].surface_type = I965_SURFACE_2D;
  202.     avc_ildb_context->surface[SURFACE_DEST_UV].format = I965_SURFACEFORMAT_R8G8_SINT;
  203.     avc_ildb_context->surface[SURFACE_DEST_UV].width = obj_surface->width / 4 - 1;
  204.     avc_ildb_context->surface[SURFACE_DEST_UV].height = obj_surface->height / 2 - 1;
  205.     avc_ildb_context->surface[SURFACE_DEST_UV].depth = 0;
  206.     avc_ildb_context->surface[SURFACE_DEST_UV].pitch = obj_surface->width - 1;
  207.     avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride = !!(va_pic->flags & (VA_PICTURE_H264_TOP_FIELD | VA_PICTURE_H264_BOTTOM_FIELD));
  208.     avc_ildb_context->surface[SURFACE_DEST_UV].vert_line_stride_ofs = !!(va_pic->flags & VA_PICTURE_H264_BOTTOM_FIELD);
  209.     avc_ildb_context->surface[SURFACE_DEST_UV].is_target = 1;
  210.  
  211.     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
  212.         bo = avc_ildb_context->surface[i].ss_bo;
  213.         dri_bo_map(bo, 1);
  214.         assert(bo->virtual);
  215.         ss = bo->virtual;
  216.         memset(ss, 0, sizeof(*ss));
  217.         ss->ss0.surface_type = avc_ildb_context->surface[i].surface_type;
  218.         ss->ss0.surface_format = avc_ildb_context->surface[i].format;
  219.         ss->ss0.vert_line_stride = avc_ildb_context->surface[i].vert_line_stride;
  220.         ss->ss0.vert_line_stride_ofs = avc_ildb_context->surface[i].vert_line_stride_ofs;
  221.         ss->ss1.base_addr = avc_ildb_context->surface[i].s_bo->offset + avc_ildb_context->surface[i].offset;
  222.         ss->ss2.width = avc_ildb_context->surface[i].width;
  223.         ss->ss2.height = avc_ildb_context->surface[i].height;
  224.         ss->ss3.depth = avc_ildb_context->surface[i].depth;
  225.         ss->ss3.pitch = avc_ildb_context->surface[i].pitch;
  226.         dri_bo_emit_reloc(bo,
  227.                           I915_GEM_DOMAIN_RENDER,
  228.                           avc_ildb_context->surface[i].is_target ? I915_GEM_DOMAIN_RENDER : 0,
  229.                           avc_ildb_context->surface[i].offset,
  230.                           offsetof(struct i965_surface_state, ss1),
  231.                           avc_ildb_context->surface[i].s_bo);
  232.         dri_bo_unmap(bo);
  233.     }
  234. }
  235.  
  236. static void
  237. i965_avc_ildb_binding_table(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
  238. {
  239.     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
  240.     unsigned int *binding_table;
  241.     dri_bo *bo = avc_ildb_context->binding_table.bo;
  242.     int i;
  243.  
  244.     dri_bo_map(bo, 1);
  245.     assert(bo->virtual);
  246.     binding_table = bo->virtual;
  247.     memset(binding_table, 0, bo->size);
  248.  
  249.     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
  250.         binding_table[i] = avc_ildb_context->surface[i].ss_bo->offset;
  251.         dri_bo_emit_reloc(bo,
  252.                           I915_GEM_DOMAIN_INSTRUCTION, 0,
  253.                           0,
  254.                           i * sizeof(*binding_table),
  255.                           avc_ildb_context->surface[i].ss_bo);
  256.     }
  257.  
  258.     dri_bo_unmap(bo);
  259. }
  260.  
  261. static void
  262. i965_avc_ildb_interface_descriptor_table(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
  263. {
  264.     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
  265.     struct i965_interface_descriptor *desc;
  266.     dri_bo *bo;
  267.     int i;
  268.  
  269.     bo = avc_ildb_context->idrt.bo;
  270.     dri_bo_map(bo, 1);
  271.     assert(bo->virtual);
  272.     desc = bo->virtual;
  273.  
  274.     for (i = 0; i < NUM_AVC_ILDB_INTERFACES; i++) {
  275.         int kernel_offset = avc_ildb_kernel_offset[i];
  276.         memset(desc, 0, sizeof(*desc));
  277.         desc->desc0.grf_reg_blocks = 7;
  278.         desc->desc0.kernel_start_pointer = (i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo->offset + kernel_offset) >> 6; /* reloc */
  279.         desc->desc1.const_urb_entry_read_offset = 0;
  280.         desc->desc1.const_urb_entry_read_len = ((i == AVC_ILDB_ROOT_Y_ILDB_FRAME ||
  281.                                                  i == AVC_ILDB_ROOT_Y_ILDB_FIELD ||
  282.                                                  i == AVC_ILDB_ROOT_Y_ILDB_MBAFF) ? 1 : 0);
  283.         desc->desc3.binding_table_entry_count = 0;
  284.         desc->desc3.binding_table_pointer =
  285.             avc_ildb_context->binding_table.bo->offset >> 5; /*reloc */
  286.  
  287.         dri_bo_emit_reloc(bo,
  288.                           I915_GEM_DOMAIN_INSTRUCTION, 0,
  289.                           desc->desc0.grf_reg_blocks + kernel_offset,
  290.                           i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc0),
  291.                           i965_h264_context->avc_kernels[H264_AVC_COMBINED].bo);
  292.  
  293.         dri_bo_emit_reloc(bo,
  294.                           I915_GEM_DOMAIN_INSTRUCTION, 0,
  295.                           desc->desc3.binding_table_entry_count,
  296.                           i * sizeof(*desc) + offsetof(struct i965_interface_descriptor, desc3),
  297.                           avc_ildb_context->binding_table.bo);
  298.         desc++;
  299.     }
  300.  
  301.     dri_bo_unmap(bo);
  302. }
  303.  
  304. static void
  305. i965_avc_ildb_vfe_state(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
  306. {
  307.     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
  308.     struct i965_vfe_state *vfe_state;
  309.     dri_bo *bo;
  310.  
  311.     bo = avc_ildb_context->vfe_state.bo;
  312.     dri_bo_map(bo, 1);
  313.     assert(bo->virtual);
  314.     vfe_state = bo->virtual;
  315.     memset(vfe_state, 0, sizeof(*vfe_state));
  316.     vfe_state->vfe1.max_threads = 0;
  317.     vfe_state->vfe1.urb_entry_alloc_size = avc_ildb_context->urb.size_vfe_entry - 1;
  318.     vfe_state->vfe1.num_urb_entries = avc_ildb_context->urb.num_vfe_entries;
  319.     vfe_state->vfe1.vfe_mode = VFE_GENERIC_MODE;
  320.     vfe_state->vfe1.children_present = 1;
  321.     vfe_state->vfe2.interface_descriptor_base =
  322.         avc_ildb_context->idrt.bo->offset >> 4; /* reloc */
  323.     dri_bo_emit_reloc(bo,
  324.                       I915_GEM_DOMAIN_INSTRUCTION, 0,
  325.                       0,
  326.                       offsetof(struct i965_vfe_state, vfe2),
  327.                       avc_ildb_context->idrt.bo);
  328.     dri_bo_unmap(bo);
  329. }
  330.  
  331. static void
  332. i965_avc_ildb_upload_constants(VADriverContextP ctx,
  333.                                struct decode_state *decode_state,
  334.                                struct i965_h264_context *i965_h264_context)
  335. {
  336.     struct i965_driver_data *i965 = i965_driver_data(ctx);
  337.     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
  338.     VAPictureParameterBufferH264 *pic_param;
  339.     struct avc_ildb_root_input *root_input;
  340.  
  341.     assert(decode_state->pic_param && decode_state->pic_param->buffer);
  342.     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
  343.  
  344.     dri_bo_map(avc_ildb_context->curbe.bo, 1);
  345.     assert(avc_ildb_context->curbe.bo->virtual);
  346.     root_input = avc_ildb_context->curbe.bo->virtual;
  347.  
  348.     if (IS_IRONLAKE(i965->intel.device_id)) {
  349.         root_input->max_concurrent_threads = 76; /* 72 - 2 + 8 - 2 */
  350.     } else {
  351.         root_input->max_concurrent_threads = 54; /* 50 - 2 + 8 - 2 */
  352.     }
  353.  
  354.     if (pic_param->pic_fields.bits.field_pic_flag)
  355.         root_input->picture_type = PICTURE_FIELD;
  356.     else {
  357.         if (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag)
  358.             root_input->picture_type = PICTURE_MBAFF;
  359.         else
  360.             root_input->picture_type = PICTURE_FRAME;
  361.     }
  362.  
  363.     avc_ildb_context->picture_type = root_input->picture_type;
  364.     root_input->blocks_per_row = pic_param->picture_width_in_mbs_minus1 + 1;
  365.     root_input->blocks_per_column = (pic_param->picture_height_in_mbs_minus1 + 1) /
  366.         (1 + (root_input->picture_type != PICTURE_FRAME));
  367.     avc_ildb_context->mbs_per_picture = (pic_param->picture_width_in_mbs_minus1 + 1) *
  368.         (pic_param->picture_height_in_mbs_minus1 + 1);
  369.    
  370.     root_input->mbaff_frame_flag = (root_input->picture_type == PICTURE_MBAFF);
  371.     root_input->bottom_field_flag = !!(pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD);
  372.     root_input->control_data_expansion_flag = 1; /* Always 1 on G4x+ */
  373.     root_input->chroma_format = (pic_param->seq_fields.bits.chroma_format_idc != 1); /* 0=4:0:0, 1=4:2:0 */
  374.    
  375.     root_input->ramp_constant_0 = 0x03020100;
  376.    
  377.     root_input->ramp_constant_1 = 0x07060504;
  378.  
  379.     root_input->constant_0 = -2;
  380.     root_input->constant_1 = 1;
  381.  
  382.     dri_bo_unmap(avc_ildb_context->curbe.bo);
  383. }
  384.  
  385. static void
  386. i965_avc_ildb_states_setup(VADriverContextP ctx,
  387.                            struct decode_state *decode_state,
  388.                            struct i965_h264_context *i965_h264_context)
  389. {
  390.     i965_avc_ildb_surface_state(ctx, decode_state, i965_h264_context);
  391.     i965_avc_ildb_binding_table(ctx, i965_h264_context);
  392.     i965_avc_ildb_interface_descriptor_table(ctx, i965_h264_context);
  393.     i965_avc_ildb_vfe_state(ctx, i965_h264_context);
  394.     i965_avc_ildb_upload_constants(ctx, decode_state, i965_h264_context);
  395. }
  396.  
  397. static void
  398. i965_avc_ildb_pipeline_select(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
  399. {
  400.     struct intel_batchbuffer *batch = i965_h264_context->batch;
  401.  
  402.     BEGIN_BATCH(batch, 1);
  403.     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
  404.     ADVANCE_BATCH(batch);
  405. }
  406.  
  407. static void
  408. i965_avc_ildb_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
  409. {
  410.     struct i965_driver_data *i965 = i965_driver_data(ctx);
  411.     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
  412.     struct intel_batchbuffer *batch = i965_h264_context->batch;
  413.     unsigned int vfe_fence, cs_fence;
  414.  
  415.     vfe_fence = avc_ildb_context->urb.cs_start;
  416.     cs_fence = URB_SIZE((&i965->intel));
  417.  
  418.     BEGIN_BATCH(batch, 3);
  419.     OUT_BATCH(batch, CMD_URB_FENCE | UF0_VFE_REALLOC | UF0_CS_REALLOC | 1);
  420.     OUT_BATCH(batch, 0);
  421.     OUT_BATCH(batch,
  422.               (vfe_fence << UF2_VFE_FENCE_SHIFT) |      /* VFE_SIZE */
  423.               (cs_fence << UF2_CS_FENCE_SHIFT));        /* CS_SIZE */
  424.     ADVANCE_BATCH(batch);
  425. }
  426.  
  427. static void
  428. i965_avc_ildb_state_base_address(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
  429. {
  430.     struct i965_driver_data *i965 = i965_driver_data(ctx);
  431.     struct intel_batchbuffer *batch = i965_h264_context->batch;
  432.  
  433.     if (IS_IRONLAKE(i965->intel.device_id)) {
  434.         BEGIN_BATCH(batch, 8);
  435.         OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 6);
  436.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  437.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  438.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  439.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  440.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  441.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  442.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  443.         ADVANCE_BATCH(batch);
  444.     } else {
  445.         BEGIN_BATCH(batch, 6);
  446.         OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 4);
  447.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  448.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  449.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  450.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  451.         OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);
  452.         ADVANCE_BATCH(batch);
  453.     }
  454. }
  455.  
  456. static void
  457. i965_avc_ildb_state_pointers(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
  458. {
  459.     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
  460.     struct intel_batchbuffer *batch = i965_h264_context->batch;
  461.  
  462.     BEGIN_BATCH(batch, 3);
  463.     OUT_BATCH(batch, CMD_MEDIA_STATE_POINTERS | 1);
  464.     OUT_BATCH(batch, 0);
  465.     OUT_RELOC(batch, avc_ildb_context->vfe_state.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
  466.     ADVANCE_BATCH(batch);
  467. }
  468.  
  469. static void
  470. i965_avc_ildb_cs_urb_layout(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
  471. {
  472.     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
  473.     struct intel_batchbuffer *batch = i965_h264_context->batch;
  474.  
  475.     BEGIN_BATCH(batch, 2);
  476.     OUT_BATCH(batch, CMD_CS_URB_STATE | 0);
  477.     OUT_BATCH(batch,
  478.               ((avc_ildb_context->urb.size_cs_entry - 1) << 4) |     /* URB Entry Allocation Size */
  479.               (avc_ildb_context->urb.num_cs_entries << 0));          /* Number of URB Entries */
  480.     ADVANCE_BATCH(batch);
  481. }
  482.  
  483. static void
  484. i965_avc_ildb_constant_buffer(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
  485. {
  486.     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
  487.     struct intel_batchbuffer *batch = i965_h264_context->batch;
  488.  
  489.     BEGIN_BATCH(batch, 2);
  490.     OUT_BATCH(batch, CMD_CONSTANT_BUFFER | (1 << 8) | (2 - 2));
  491.     OUT_RELOC(batch, avc_ildb_context->curbe.bo,
  492.               I915_GEM_DOMAIN_INSTRUCTION, 0,
  493.               avc_ildb_context->urb.size_cs_entry - 1);
  494.     ADVANCE_BATCH(batch);    
  495. }
  496.  
  497. static void
  498. i965_avc_ildb_objects(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
  499. {
  500.     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;
  501.     struct intel_batchbuffer *batch = i965_h264_context->batch;
  502.  
  503.     BEGIN_BATCH(batch, 6);
  504.     OUT_BATCH(batch, CMD_MEDIA_OBJECT | 4);
  505.  
  506.     switch (avc_ildb_context->picture_type) {
  507.     case PICTURE_FRAME:
  508.         OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_FRAME);
  509.         break;
  510.  
  511.     case PICTURE_FIELD:
  512.         OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_FIELD);
  513.         break;
  514.  
  515.     case PICTURE_MBAFF:
  516.         OUT_BATCH(batch, AVC_ILDB_ROOT_Y_ILDB_MBAFF);
  517.         break;
  518.  
  519.     default:
  520.         assert(0);
  521.         OUT_BATCH(batch, 0);
  522.         break;
  523.     }
  524.  
  525.     OUT_BATCH(batch, 0); /* no indirect data */
  526.     OUT_BATCH(batch, 0);
  527.     OUT_BATCH(batch, 0);
  528.     OUT_BATCH(batch, 0);
  529.     ADVANCE_BATCH(batch);
  530. }
  531.  
  532. static void
  533. i965_avc_ildb_pipeline_setup(VADriverContextP ctx, struct i965_h264_context *i965_h264_context)
  534. {
  535.     struct intel_batchbuffer *batch = i965_h264_context->batch;
  536.  
  537.     intel_batchbuffer_emit_mi_flush(batch);
  538.     i965_avc_ildb_pipeline_select(ctx, i965_h264_context);
  539.     i965_avc_ildb_state_base_address(ctx, i965_h264_context);
  540.     i965_avc_ildb_state_pointers(ctx, i965_h264_context);
  541.     i965_avc_ildb_urb_layout(ctx, i965_h264_context);
  542.     i965_avc_ildb_cs_urb_layout(ctx, i965_h264_context);
  543.     i965_avc_ildb_constant_buffer(ctx, i965_h264_context);
  544.     i965_avc_ildb_objects(ctx, i965_h264_context);
  545. }
  546.  
  547. void
  548. i965_avc_ildb(VADriverContextP ctx, struct decode_state *decode_state, void *h264_context)
  549. {
  550.     struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
  551.  
  552.     if (i965_h264_context->enable_avc_ildb) {
  553.         i965_avc_ildb_states_setup(ctx, decode_state, i965_h264_context);
  554.         i965_avc_ildb_pipeline_setup(ctx, i965_h264_context);
  555.     }
  556. }
  557.  
  558. void
  559. i965_avc_ildb_decode_init(VADriverContextP ctx, void *h264_context)
  560. {
  561.     struct i965_driver_data *i965 = i965_driver_data(ctx);
  562.     struct i965_h264_context *i965_h264_context = (struct i965_h264_context *)h264_context;
  563.     struct i965_avc_ildb_context *avc_ildb_context = &i965_h264_context->avc_ildb_context;;
  564.     dri_bo *bo;
  565.     int i;
  566.  
  567.     dri_bo_unreference(avc_ildb_context->curbe.bo);
  568.     bo = dri_bo_alloc(i965->intel.bufmgr,
  569.                       "constant buffer",
  570.                       4096, 64);
  571.     assert(bo);
  572.     avc_ildb_context->curbe.bo = bo;
  573.  
  574.     dri_bo_unreference(avc_ildb_context->binding_table.bo);
  575.     bo = dri_bo_alloc(i965->intel.bufmgr,
  576.                       "binding table",
  577.                       NUM_AVC_ILDB_SURFACES * sizeof(unsigned int), 32);
  578.     assert(bo);
  579.     avc_ildb_context->binding_table.bo = bo;
  580.  
  581.     dri_bo_unreference(avc_ildb_context->idrt.bo);
  582.     bo = dri_bo_alloc(i965->intel.bufmgr,
  583.                       "interface discriptor",
  584.                       NUM_AVC_ILDB_INTERFACES * sizeof(struct i965_interface_descriptor), 16);
  585.     assert(bo);
  586.     avc_ildb_context->idrt.bo = bo;
  587.  
  588.     dri_bo_unreference(avc_ildb_context->vfe_state.bo);
  589.     bo = dri_bo_alloc(i965->intel.bufmgr,
  590.                       "vfe state",
  591.                       sizeof(struct i965_vfe_state), 32);
  592.     assert(bo);
  593.     avc_ildb_context->vfe_state.bo = bo;
  594.  
  595.     avc_ildb_context->urb.num_vfe_entries = 1;
  596.     avc_ildb_context->urb.size_vfe_entry = 640;
  597.     avc_ildb_context->urb.num_cs_entries = 1;
  598.     avc_ildb_context->urb.size_cs_entry = 1;
  599.     avc_ildb_context->urb.vfe_start = 0;
  600.     avc_ildb_context->urb.cs_start = avc_ildb_context->urb.vfe_start +
  601.         avc_ildb_context->urb.num_vfe_entries * avc_ildb_context->urb.size_vfe_entry;
  602.     assert(avc_ildb_context->urb.cs_start +
  603.            avc_ildb_context->urb.num_cs_entries * avc_ildb_context->urb.size_cs_entry <= URB_SIZE((&i965->intel)));
  604.  
  605.     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
  606.         dri_bo_unreference(avc_ildb_context->surface[i].s_bo);
  607.         avc_ildb_context->surface[i].s_bo = NULL;
  608.  
  609.         dri_bo_unreference(avc_ildb_context->surface[i].ss_bo);
  610.         bo = dri_bo_alloc(i965->intel.bufmgr,
  611.                           "surface state",
  612.                           sizeof(struct i965_surface_state), 32);
  613.         assert(bo);
  614.         avc_ildb_context->surface[i].ss_bo = bo;
  615.     }
  616.  
  617.     /* kernel offset */
  618.     assert(NUM_AVC_ILDB_INTERFACES == ARRAY_ELEMS(avc_ildb_kernel_offset_gen5));
  619.  
  620.     if (IS_IRONLAKE(i965->intel.device_id)) {
  621.         avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen5;
  622.     } else {
  623.         avc_ildb_kernel_offset = avc_ildb_kernel_offset_gen4;
  624.     }
  625. }
  626.  
  627. Bool
  628. i965_avc_ildb_ternimate(struct i965_avc_ildb_context *avc_ildb_context)
  629. {
  630.     int i;
  631.  
  632.     dri_bo_unreference(avc_ildb_context->curbe.bo);
  633.     avc_ildb_context->curbe.bo = NULL;
  634.  
  635.     dri_bo_unreference(avc_ildb_context->binding_table.bo);
  636.     avc_ildb_context->binding_table.bo = NULL;
  637.  
  638.     dri_bo_unreference(avc_ildb_context->idrt.bo);
  639.     avc_ildb_context->idrt.bo = NULL;
  640.  
  641.     dri_bo_unreference(avc_ildb_context->vfe_state.bo);
  642.     avc_ildb_context->vfe_state.bo = NULL;
  643.  
  644.     for (i = 0; i < NUM_AVC_ILDB_SURFACES; i++) {
  645.         dri_bo_unreference(avc_ildb_context->surface[i].ss_bo);
  646.         avc_ildb_context->surface[i].ss_bo = NULL;
  647.  
  648.         dri_bo_unreference(avc_ildb_context->surface[i].s_bo);
  649.         avc_ildb_context->surface[i].s_bo = NULL;
  650.     }
  651.  
  652.     return True;
  653. }
  654.