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  1. /**************************************************************************
  2.  *
  3.  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4.  * All Rights Reserved.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the
  8.  * "Software"), to deal in the Software without restriction, including
  9.  * without limitation the rights to use, copy, modify, merge, publish,
  10.  * distribute, sub license, and/or sell copies of the Software, and to
  11.  * permit persons to whom the Software is furnished to do so, subject to
  12.  * the following conditions:
  13.  *
  14.  * The above copyright notice and this permission notice (including the
  15.  * next paragraph) shall be included in all copies or substantial portions
  16.  * of the Software.
  17.  *
  18.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20.  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21.  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22.  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23.  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24.  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25.  *
  26.  **************************************************************************/
  27.  
  28. #include <drm/drmP.h>
  29. #include "vmwgfx_drv.h"
  30.  
  31. #define TASK_INTERRUPTIBLE      1
  32. #define TASK_UNINTERRUPTIBLE    2
  33.  
  34. #define VMW_FENCE_WRAP (1 << 24)
  35.  
  36. irqreturn_t vmw_irq_handler(int irq, void *arg)
  37. {
  38.         struct drm_device *dev = (struct drm_device *)arg;
  39.         struct vmw_private *dev_priv = vmw_priv(dev);
  40.         uint32_t status, masked_status;
  41.  
  42.         spin_lock(&dev_priv->irq_lock);
  43.         status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  44.         masked_status = status & dev_priv->irq_mask;
  45.         spin_unlock(&dev_priv->irq_lock);
  46.  
  47.         if (likely(status))
  48.                 outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  49.  
  50.         if (!masked_status)
  51.                 return IRQ_NONE;
  52.  
  53.         if (masked_status & (SVGA_IRQFLAG_ANY_FENCE |
  54.                              SVGA_IRQFLAG_FENCE_GOAL)) {
  55.                 vmw_fences_update(dev_priv->fman);
  56.                 wake_up_all(&dev_priv->fence_queue);
  57.         }
  58.  
  59.         if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS)
  60.                 wake_up_all(&dev_priv->fifo_queue);
  61.  
  62.  
  63.         return IRQ_HANDLED;
  64. }
  65.  
  66. static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno)
  67. {
  68.         uint32_t busy;
  69.  
  70.         mutex_lock(&dev_priv->hw_mutex);
  71.         busy = vmw_read(dev_priv, SVGA_REG_BUSY);
  72.         mutex_unlock(&dev_priv->hw_mutex);
  73.  
  74.         return (busy == 0);
  75. }
  76.  
  77. void vmw_update_seqno(struct vmw_private *dev_priv,
  78.                          struct vmw_fifo_state *fifo_state)
  79. {
  80.         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  81.         uint32_t seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
  82.  
  83.         if (dev_priv->last_read_seqno != seqno) {
  84.                 dev_priv->last_read_seqno = seqno;
  85.                 vmw_marker_pull(&fifo_state->marker_queue, seqno);
  86.                 vmw_fences_update(dev_priv->fman);
  87.         }
  88. }
  89.  
  90. bool vmw_seqno_passed(struct vmw_private *dev_priv,
  91.                          uint32_t seqno)
  92. {
  93.         struct vmw_fifo_state *fifo_state;
  94.         bool ret;
  95.  
  96.         if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
  97.                 return true;
  98.  
  99.         fifo_state = &dev_priv->fifo;
  100.         vmw_update_seqno(dev_priv, fifo_state);
  101.         if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
  102.                 return true;
  103.  
  104.         if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) &&
  105.             vmw_fifo_idle(dev_priv, seqno))
  106.                 return true;
  107.  
  108.         /**
  109.          * Then check if the seqno is higher than what we've actually
  110.          * emitted. Then the fence is stale and signaled.
  111.          */
  112.  
  113.         ret = ((atomic_read(&dev_priv->marker_seq) - seqno)
  114.                > VMW_FENCE_WRAP);
  115.  
  116.         return ret;
  117. }
  118.  
  119. int vmw_fallback_wait(struct vmw_private *dev_priv,
  120.                       bool lazy,
  121.                       bool fifo_idle,
  122.                       uint32_t seqno,
  123.                       bool interruptible,
  124.                       unsigned long timeout)
  125. {
  126.         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
  127.  
  128.         uint32_t count = 0;
  129.         uint32_t signal_seq;
  130.         int ret;
  131.     unsigned long end_jiffies = GetTimerTicks() + timeout;
  132.         bool (*wait_condition)(struct vmw_private *, uint32_t);
  133.         DEFINE_WAIT(__wait);
  134.  
  135.         wait_condition = (fifo_idle) ? &vmw_fifo_idle :
  136.                 &vmw_seqno_passed;
  137.  
  138.         /**
  139.          * Block command submission while waiting for idle.
  140.          */
  141.  
  142. //   if (fifo_idle)
  143. //       down_read(&fifo_state->rwsem);
  144.         signal_seq = atomic_read(&dev_priv->marker_seq);
  145.         ret = 0;
  146.  
  147.         for (;;) {
  148. //       prepare_to_wait(&dev_priv->fence_queue, &__wait,
  149. //               (interruptible) ?
  150. //               TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
  151.                 if (wait_condition(dev_priv, seqno))
  152.                         break;
  153.         if (time_after_eq(GetTimerTicks(), end_jiffies)) {
  154.                         DRM_ERROR("SVGA device lockup.\n");
  155.                         break;
  156.                 }
  157.                 if (lazy)
  158.             delay(1);
  159.                 else if ((++count & 0x0F) == 0) {
  160.                         /**
  161.                          * FIXME: Use schedule_hr_timeout here for
  162.                          * newer kernels and lower CPU utilization.
  163.                          */
  164.  
  165.             delay(1);
  166.                 }
  167.         }
  168. //   finish_wait(&dev_priv->fence_queue, &__wait);
  169.         if (ret == 0 && fifo_idle) {
  170.                 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  171.                 iowrite32(signal_seq, fifo_mem + SVGA_FIFO_FENCE);
  172.         }
  173.         wake_up_all(&dev_priv->fence_queue);
  174. //   if (fifo_idle)
  175. //       up_read(&fifo_state->rwsem);
  176.  
  177.         return ret;
  178. }
  179.  
  180. void vmw_seqno_waiter_add(struct vmw_private *dev_priv)
  181. {
  182.         mutex_lock(&dev_priv->hw_mutex);
  183.         if (dev_priv->fence_queue_waiters++ == 0) {
  184.                 unsigned long irq_flags;
  185.  
  186.                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  187.                 outl(SVGA_IRQFLAG_ANY_FENCE,
  188.                      dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  189.                 dev_priv->irq_mask |= SVGA_IRQFLAG_ANY_FENCE;
  190.                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  191.                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  192.         }
  193.         mutex_unlock(&dev_priv->hw_mutex);
  194. }
  195.  
  196. void vmw_seqno_waiter_remove(struct vmw_private *dev_priv)
  197. {
  198.         mutex_lock(&dev_priv->hw_mutex);
  199.         if (--dev_priv->fence_queue_waiters == 0) {
  200.                 unsigned long irq_flags;
  201.  
  202.                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  203.                 dev_priv->irq_mask &= ~SVGA_IRQFLAG_ANY_FENCE;
  204.                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  205.                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  206.         }
  207.         mutex_unlock(&dev_priv->hw_mutex);
  208. }
  209.  
  210.  
  211. void vmw_goal_waiter_add(struct vmw_private *dev_priv)
  212. {
  213.         mutex_lock(&dev_priv->hw_mutex);
  214.         if (dev_priv->goal_queue_waiters++ == 0) {
  215.                 unsigned long irq_flags;
  216.  
  217.                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  218.                 outl(SVGA_IRQFLAG_FENCE_GOAL,
  219.                      dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  220.                 dev_priv->irq_mask |= SVGA_IRQFLAG_FENCE_GOAL;
  221.                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  222.                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  223.         }
  224.         mutex_unlock(&dev_priv->hw_mutex);
  225. }
  226.  
  227. void vmw_goal_waiter_remove(struct vmw_private *dev_priv)
  228. {
  229.         mutex_lock(&dev_priv->hw_mutex);
  230.         if (--dev_priv->goal_queue_waiters == 0) {
  231.                 unsigned long irq_flags;
  232.  
  233.                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
  234.                 dev_priv->irq_mask &= ~SVGA_IRQFLAG_FENCE_GOAL;
  235.                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
  236.                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
  237.         }
  238.         mutex_unlock(&dev_priv->hw_mutex);
  239. }
  240.  
  241. int vmw_wait_seqno(struct vmw_private *dev_priv,
  242.                       bool lazy, uint32_t seqno,
  243.                       bool interruptible, unsigned long timeout)
  244. {
  245.         long ret;
  246.         struct vmw_fifo_state *fifo = &dev_priv->fifo;
  247.  
  248.         if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
  249.                 return 0;
  250.  
  251.         if (likely(vmw_seqno_passed(dev_priv, seqno)))
  252.                 return 0;
  253.  
  254.         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
  255.  
  256.         if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE))
  257.                 return vmw_fallback_wait(dev_priv, lazy, true, seqno,
  258.                                          interruptible, timeout);
  259.  
  260.         if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
  261.                 return vmw_fallback_wait(dev_priv, lazy, false, seqno,
  262.                                          interruptible, timeout);
  263.  
  264.         vmw_seqno_waiter_add(dev_priv);
  265.  
  266.         if (interruptible)
  267.                 ret = wait_event_interruptible_timeout
  268.                     (dev_priv->fence_queue,
  269.                      vmw_seqno_passed(dev_priv, seqno),
  270.                      timeout);
  271.         else
  272.                 ret = wait_event_timeout
  273.                     (dev_priv->fence_queue,
  274.                      vmw_seqno_passed(dev_priv, seqno),
  275.                      timeout);
  276.  
  277.         vmw_seqno_waiter_remove(dev_priv);
  278.  
  279.         if (unlikely(ret == 0))
  280.                 ret = -EBUSY;
  281.         else if (likely(ret > 0))
  282.                 ret = 0;
  283.  
  284.         return ret;
  285. }
  286.  
  287. void vmw_irq_preinstall(struct drm_device *dev)
  288. {
  289.         struct vmw_private *dev_priv = vmw_priv(dev);
  290.         uint32_t status;
  291.  
  292.         if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
  293.                 return;
  294.  
  295.         spin_lock_init(&dev_priv->irq_lock);
  296.         status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  297.         outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  298. }
  299.  
  300. int vmw_irq_postinstall(struct drm_device *dev)
  301. {
  302.         return 0;
  303. }
  304.  
  305. void vmw_irq_uninstall(struct drm_device *dev)
  306. {
  307.         struct vmw_private *dev_priv = vmw_priv(dev);
  308.         uint32_t status;
  309.  
  310.         if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
  311.                 return;
  312.  
  313.         mutex_lock(&dev_priv->hw_mutex);
  314.         vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
  315.         mutex_unlock(&dev_priv->hw_mutex);
  316.  
  317.         status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  318.         outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
  319. }
  320.  
  321. int autoremove_wake_function(wait_queue_t *wait, unsigned mode, int sync, void *key)
  322. {
  323.     list_del_init(&wait->task_list);
  324.     return 1;
  325. }
  326.  
  327.