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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. //#include <linux/seq_file.h>
  29. #include "drmP.h"
  30. #include "radeon_reg.h"
  31. #include "radeon.h"
  32.  
  33. /* rv515 depends on : */
  34. void r100_hdp_reset(struct radeon_device *rdev);
  35. int r100_cp_reset(struct radeon_device *rdev);
  36. int r100_rb2d_reset(struct radeon_device *rdev);
  37. int r100_gui_wait_for_idle(struct radeon_device *rdev);
  38. int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  39. int rv370_pcie_gart_enable(struct radeon_device *rdev);
  40. void rv370_pcie_gart_disable(struct radeon_device *rdev);
  41. void r420_pipes_init(struct radeon_device *rdev);
  42. void rs600_mc_disable_clients(struct radeon_device *rdev);
  43. void rs600_disable_vga(struct radeon_device *rdev);
  44.  
  45. /* This files gather functions specifics to:
  46.  * rv515
  47.  *
  48.  * Some of these functions might be used by newer ASICs.
  49.  */
  50. int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  51. int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  52. void rv515_gpu_init(struct radeon_device *rdev);
  53. int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  54.  
  55. /*
  56.  * MC
  57.  */
  58. int rv515_mc_init(struct radeon_device *rdev)
  59. {
  60.         uint32_t tmp;
  61.         int r;
  62.  
  63.         if (r100_debugfs_rbbm_init(rdev)) {
  64.                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  65.         }
  66.         if (rv515_debugfs_pipes_info_init(rdev)) {
  67.                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  68.         }
  69.         if (rv515_debugfs_ga_info_init(rdev)) {
  70.                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  71.         }
  72.  
  73.         rv515_gpu_init(rdev);
  74.         rv370_pcie_gart_disable(rdev);
  75.  
  76.         /* Setup GPU memory space */
  77.         rdev->mc.vram_location = 0xFFFFFFFFUL;
  78.         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  79.         if (rdev->flags & RADEON_IS_AGP) {
  80.                 r = radeon_agp_init(rdev);
  81.                 if (r) {
  82.                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  83.                         rdev->flags &= ~RADEON_IS_AGP;
  84.                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  85.                 } else {
  86.                         rdev->mc.gtt_location = rdev->mc.agp_base;
  87.                 }
  88.         }
  89.         r = radeon_mc_setup(rdev);
  90.         if (r) {
  91.                 return r;
  92.         }
  93.  
  94.         /* Program GPU memory space */
  95.         rs600_mc_disable_clients(rdev);
  96.         if (rv515_mc_wait_for_idle(rdev)) {
  97.                 printk(KERN_WARNING "Failed to wait MC idle while "
  98.                        "programming pipes. Bad things might happen.\n");
  99.         }
  100.         /* Write VRAM size in case we are limiting it */
  101.         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
  102.         tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
  103.         WREG32(0x134, tmp);
  104.         tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
  105.         tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16);
  106.         tmp |= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
  107.         WREG32_MC(RV515_MC_FB_LOCATION, tmp);
  108.         WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
  109.         WREG32(0x310, rdev->mc.vram_location);
  110.         if (rdev->flags & RADEON_IS_AGP) {
  111.                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  112.                 tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16);
  113.                 tmp |= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16);
  114.                 WREG32_MC(RV515_MC_AGP_LOCATION, tmp);
  115.                 WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base);
  116.                 WREG32_MC(RV515_MC_AGP_BASE_2, 0);
  117.         } else {
  118.                 WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF);
  119.                 WREG32_MC(RV515_MC_AGP_BASE, 0);
  120.                 WREG32_MC(RV515_MC_AGP_BASE_2, 0);
  121.         }
  122.         return 0;
  123. }
  124.  
  125. void rv515_mc_fini(struct radeon_device *rdev)
  126. {
  127.         rv370_pcie_gart_disable(rdev);
  128.         radeon_gart_table_vram_free(rdev);
  129.         radeon_gart_fini(rdev);
  130. }
  131.  
  132.  
  133. /*
  134.  * Global GPU functions
  135.  */
  136. void rv515_ring_start(struct radeon_device *rdev)
  137. {
  138.         unsigned gb_tile_config;
  139.         int r;
  140.  
  141.     dbgprintf("%s\n",__FUNCTION__);
  142.         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
  143.         gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16;
  144.         switch (rdev->num_gb_pipes) {
  145.         case 2:
  146.                 gb_tile_config |= R300_PIPE_COUNT_R300;
  147.                 break;
  148.         case 3:
  149.                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
  150.                 break;
  151.         case 4:
  152.                 gb_tile_config |= R300_PIPE_COUNT_R420;
  153.                 break;
  154.         case 1:
  155.         default:
  156.                 gb_tile_config |= R300_PIPE_COUNT_RV350;
  157.                 break;
  158.         }
  159.  
  160.         r = radeon_ring_lock(rdev, 64);
  161.         if (r) {
  162.                 return;
  163.         }
  164.         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
  165.         radeon_ring_write(rdev,
  166.                           RADEON_ISYNC_ANY2D_IDLE3D |
  167.                           RADEON_ISYNC_ANY3D_IDLE2D |
  168.                           RADEON_ISYNC_WAIT_IDLEGUI |
  169.                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
  170.         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
  171.         radeon_ring_write(rdev, gb_tile_config);
  172.         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
  173.         radeon_ring_write(rdev,
  174.                           RADEON_WAIT_2D_IDLECLEAN |
  175.                           RADEON_WAIT_3D_IDLECLEAN);
  176.         radeon_ring_write(rdev, PACKET0(0x170C, 0));
  177.         radeon_ring_write(rdev, 1 << 31);
  178.         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
  179.         radeon_ring_write(rdev, 0);
  180.         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
  181.         radeon_ring_write(rdev, 0);
  182.         radeon_ring_write(rdev, PACKET0(0x42C8, 0));
  183.         radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
  184.         radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0));
  185.         radeon_ring_write(rdev, 0);
  186.         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
  187.         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
  188.         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
  189.         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
  190.         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
  191.         radeon_ring_write(rdev,
  192.                           RADEON_WAIT_2D_IDLECLEAN |
  193.                           RADEON_WAIT_3D_IDLECLEAN);
  194.         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
  195.         radeon_ring_write(rdev, 0);
  196.         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
  197.         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
  198.         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
  199.         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
  200.         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
  201.         radeon_ring_write(rdev,
  202.                           ((6 << R300_MS_X0_SHIFT) |
  203.                            (6 << R300_MS_Y0_SHIFT) |
  204.                            (6 << R300_MS_X1_SHIFT) |
  205.                            (6 << R300_MS_Y1_SHIFT) |
  206.                            (6 << R300_MS_X2_SHIFT) |
  207.                            (6 << R300_MS_Y2_SHIFT) |
  208.                            (6 << R300_MSBD0_Y_SHIFT) |
  209.                            (6 << R300_MSBD0_X_SHIFT)));
  210.         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
  211.         radeon_ring_write(rdev,
  212.                           ((6 << R300_MS_X3_SHIFT) |
  213.                            (6 << R300_MS_Y3_SHIFT) |
  214.                            (6 << R300_MS_X4_SHIFT) |
  215.                            (6 << R300_MS_Y4_SHIFT) |
  216.                            (6 << R300_MS_X5_SHIFT) |
  217.                            (6 << R300_MS_Y5_SHIFT) |
  218.                            (6 << R300_MSBD1_SHIFT)));
  219.         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
  220.         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
  221.         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
  222.         radeon_ring_write(rdev,
  223.                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
  224.         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
  225.         radeon_ring_write(rdev,
  226.                           R300_GEOMETRY_ROUND_NEAREST |
  227.                           R300_COLOR_ROUND_NEAREST);
  228.         radeon_ring_write(rdev, PACKET0(0x20C8, 0));
  229.         radeon_ring_write(rdev, 0);
  230.         radeon_ring_unlock_commit(rdev);
  231.  
  232.     dbgprintf("done %s\n",__FUNCTION__);
  233.  
  234. }
  235.  
  236. void rv515_errata(struct radeon_device *rdev)
  237. {
  238.         rdev->pll_errata = 0;
  239. }
  240.  
  241. int rv515_mc_wait_for_idle(struct radeon_device *rdev)
  242. {
  243.         unsigned i;
  244.         uint32_t tmp;
  245.  
  246.         for (i = 0; i < rdev->usec_timeout; i++) {
  247.                 /* read MC_STATUS */
  248.                 tmp = RREG32_MC(RV515_MC_STATUS);
  249.                 if (tmp & RV515_MC_STATUS_IDLE) {
  250.                         return 0;
  251.                 }
  252.                 DRM_UDELAY(1);
  253.         }
  254.         return -1;
  255. }
  256.  
  257. void rv515_gpu_init(struct radeon_device *rdev)
  258. {
  259.         unsigned pipe_select_current, gb_pipe_select, tmp;
  260.  
  261.         r100_hdp_reset(rdev);
  262.         r100_rb2d_reset(rdev);
  263.  
  264.         if (r100_gui_wait_for_idle(rdev)) {
  265.                 printk(KERN_WARNING "Failed to wait GUI idle while "
  266.                        "reseting GPU. Bad things might happen.\n");
  267.         }
  268.  
  269.         rs600_disable_vga(rdev);
  270.  
  271.         r420_pipes_init(rdev);
  272.         gb_pipe_select = RREG32(0x402C);
  273.         tmp = RREG32(0x170C);
  274.         pipe_select_current = (tmp >> 2) & 3;
  275.         tmp = (1 << pipe_select_current) |
  276.               (((gb_pipe_select >> 8) & 0xF) << 4);
  277.         WREG32_PLL(0x000D, tmp);
  278.         if (r100_gui_wait_for_idle(rdev)) {
  279.                 printk(KERN_WARNING "Failed to wait GUI idle while "
  280.                        "reseting GPU. Bad things might happen.\n");
  281.         }
  282.         if (rv515_mc_wait_for_idle(rdev)) {
  283.                 printk(KERN_WARNING "Failed to wait MC idle while "
  284.                        "programming pipes. Bad things might happen.\n");
  285.         }
  286. }
  287.  
  288.  
  289. int rv515_ga_reset(struct radeon_device *rdev)
  290. {
  291.         uint32_t tmp;
  292.         bool reinit_cp;
  293.         int i;
  294.  
  295.     dbgprintf("%s\n",__FUNCTION__);
  296.  
  297.         reinit_cp = rdev->cp.ready;
  298.         rdev->cp.ready = false;
  299.         for (i = 0; i < rdev->usec_timeout; i++) {
  300.                 WREG32(RADEON_CP_CSQ_MODE, 0);
  301.                 WREG32(RADEON_CP_CSQ_CNTL, 0);
  302.                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
  303.                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
  304.                 udelay(200);
  305.                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
  306.                 /* Wait to prevent race in RBBM_STATUS */
  307.                 mdelay(1);
  308.                 tmp = RREG32(RADEON_RBBM_STATUS);
  309.                 if (tmp & ((1 << 20) | (1 << 26))) {
  310.                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
  311.                         /* GA still busy soft reset it */
  312.                         WREG32(0x429C, 0x200);
  313.                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
  314.                         WREG32(0x43E0, 0);
  315.                         WREG32(0x43E4, 0);
  316.                         WREG32(0x24AC, 0);
  317.                 }
  318.                 /* Wait to prevent race in RBBM_STATUS */
  319.                 mdelay(1);
  320.                 tmp = RREG32(RADEON_RBBM_STATUS);
  321.                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
  322.                         break;
  323.                 }
  324.         }
  325.         for (i = 0; i < rdev->usec_timeout; i++) {
  326.                 tmp = RREG32(RADEON_RBBM_STATUS);
  327.                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
  328.                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
  329.                                  tmp);
  330.                         DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
  331.                         DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
  332.                         DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
  333.                         if (reinit_cp) {
  334.                                 return r100_cp_init(rdev, rdev->cp.ring_size);
  335.                         }
  336.                         return 0;
  337.                 }
  338.                 DRM_UDELAY(1);
  339.         }
  340.         tmp = RREG32(RADEON_RBBM_STATUS);
  341.         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
  342.         return -1;
  343. }
  344.  
  345. int rv515_gpu_reset(struct radeon_device *rdev)
  346. {
  347.         uint32_t status;
  348.  
  349.     dbgprintf("%s\n",__FUNCTION__);
  350.  
  351.         /* reset order likely matter */
  352.         status = RREG32(RADEON_RBBM_STATUS);
  353.         /* reset HDP */
  354.         r100_hdp_reset(rdev);
  355.         /* reset rb2d */
  356.         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
  357.                 r100_rb2d_reset(rdev);
  358.         }
  359.         /* reset GA */
  360.         if (status & ((1 << 20) | (1 << 26))) {
  361.                 rv515_ga_reset(rdev);
  362.         }
  363.         /* reset CP */
  364.         status = RREG32(RADEON_RBBM_STATUS);
  365.         if (status & (1 << 16)) {
  366.                 r100_cp_reset(rdev);
  367.         }
  368.         /* Check if GPU is idle */
  369.         status = RREG32(RADEON_RBBM_STATUS);
  370.         if (status & (1 << 31)) {
  371.                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
  372.                 return -1;
  373.         }
  374.         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
  375.         return 0;
  376. }
  377.  
  378.  
  379. /*
  380.  * VRAM info
  381.  */
  382. static void rv515_vram_get_type(struct radeon_device *rdev)
  383. {
  384.         uint32_t tmp;
  385.  
  386.         rdev->mc.vram_width = 128;
  387.         rdev->mc.vram_is_ddr = true;
  388.         tmp = RREG32_MC(RV515_MC_CNTL);
  389.         tmp &= RV515_MEM_NUM_CHANNELS_MASK;
  390.         switch (tmp) {
  391.         case 0:
  392.                 rdev->mc.vram_width = 64;
  393.                 break;
  394.         case 1:
  395.                 rdev->mc.vram_width = 128;
  396.                 break;
  397.         default:
  398.                 rdev->mc.vram_width = 128;
  399.                 break;
  400.         }
  401. }
  402.  
  403. void rv515_vram_info(struct radeon_device *rdev)
  404. {
  405.         rv515_vram_get_type(rdev);
  406.         rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
  407.  
  408.         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
  409.         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
  410. }
  411.  
  412.  
  413. /*
  414.  * Indirect registers accessor
  415.  */
  416. uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  417. {
  418.         uint32_t r;
  419.  
  420.         WREG32(R520_MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
  421.         r = RREG32(R520_MC_IND_DATA);
  422.         WREG32(R520_MC_IND_INDEX, 0);
  423.         return r;
  424. }
  425.  
  426. void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  427. {
  428.         WREG32(R520_MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
  429.         WREG32(R520_MC_IND_DATA, (v));
  430.         WREG32(R520_MC_IND_INDEX, 0);
  431. }
  432.  
  433. uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  434. {
  435.         uint32_t r;
  436.  
  437.         WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
  438.         (void)RREG32(RADEON_PCIE_INDEX);
  439.         r = RREG32(RADEON_PCIE_DATA);
  440.         return r;
  441. }
  442.  
  443. void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  444. {
  445.         WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
  446.         (void)RREG32(RADEON_PCIE_INDEX);
  447.         WREG32(RADEON_PCIE_DATA, (v));
  448.         (void)RREG32(RADEON_PCIE_DATA);
  449. }
  450.  
  451.  
  452. /*
  453.  * Debugfs info
  454.  */
  455. #if defined(CONFIG_DEBUG_FS)
  456. static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
  457. {
  458.         struct drm_info_node *node = (struct drm_info_node *) m->private;
  459.         struct drm_device *dev = node->minor->dev;
  460.         struct radeon_device *rdev = dev->dev_private;
  461.         uint32_t tmp;
  462.  
  463.         tmp = RREG32(R400_GB_PIPE_SELECT);
  464.         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
  465.         tmp = RREG32(R500_SU_REG_DEST);
  466.         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
  467.         tmp = RREG32(R300_GB_TILE_CONFIG);
  468.         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
  469.         tmp = RREG32(R300_DST_PIPE_CONFIG);
  470.         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
  471.         return 0;
  472. }
  473.  
  474. static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
  475. {
  476.         struct drm_info_node *node = (struct drm_info_node *) m->private;
  477.         struct drm_device *dev = node->minor->dev;
  478.         struct radeon_device *rdev = dev->dev_private;
  479.         uint32_t tmp;
  480.  
  481.         tmp = RREG32(0x2140);
  482.         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
  483.         radeon_gpu_reset(rdev);
  484.         tmp = RREG32(0x425C);
  485.         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
  486.         return 0;
  487. }
  488.  
  489. static struct drm_info_list rv515_pipes_info_list[] = {
  490.         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
  491. };
  492.  
  493. static struct drm_info_list rv515_ga_info_list[] = {
  494.         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
  495. };
  496. #endif
  497.  
  498. int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
  499. {
  500. #if defined(CONFIG_DEBUG_FS)
  501.         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
  502. #else
  503.         return 0;
  504. #endif
  505. }
  506.  
  507. int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
  508. {
  509. #if defined(CONFIG_DEBUG_FS)
  510.         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
  511. #else
  512.         return 0;
  513. #endif
  514. }
  515.  
  516.  
  517. /*
  518.  * Asic initialization
  519.  */
  520. static const unsigned r500_reg_safe_bm[159] = {
  521.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  522.         0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF,
  523.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  524.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  525.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  526.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  527.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  528.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  529.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  530.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  531.         0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
  532.         0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
  533.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  534.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  535.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
  536.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  537.         0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
  538.         0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
  539.         0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
  540.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  541.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  542.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  543.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  544.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  545.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  546.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  547.         0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  548.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  549.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  550.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  551.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  552.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  553.         0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF,
  554.         0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF,
  555.         0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
  556.         0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF,
  557.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  558.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
  559.         0x00000000, 0x00000000, 0x00000000, 0x00000000,
  560.         0x0003FC01, 0x3FFFFCF8, 0xFE800B19,
  561. };
  562.  
  563.  
  564.  
  565. int rv515_init(struct radeon_device *rdev)
  566. {
  567.     dbgprintf("%s\n",__FUNCTION__);
  568.  
  569.         rdev->config.r300.reg_safe_bm = r500_reg_safe_bm;
  570.         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm);
  571.         return 0;
  572. }
  573.