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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. //#include <linux/seq_file.h>
  29. //#include "drmP.h"
  30. #include "radeon_reg.h"
  31. #include "radeon.h"
  32.  
  33. /* rv515 depends on : */
  34. void r100_hdp_reset(struct radeon_device *rdev);
  35. int r100_cp_reset(struct radeon_device *rdev);
  36. int r100_rb2d_reset(struct radeon_device *rdev);
  37. int r100_gui_wait_for_idle(struct radeon_device *rdev);
  38. int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  39. int rv370_pcie_gart_enable(struct radeon_device *rdev);
  40. void rv370_pcie_gart_disable(struct radeon_device *rdev);
  41. void r420_pipes_init(struct radeon_device *rdev);
  42. void rs600_mc_disable_clients(struct radeon_device *rdev);
  43. void rs600_disable_vga(struct radeon_device *rdev);
  44.  
  45. /* This files gather functions specifics to:
  46.  * rv515
  47.  *
  48.  * Some of these functions might be used by newer ASICs.
  49.  */
  50. int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
  51. int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
  52. void rv515_gpu_init(struct radeon_device *rdev);
  53. int rv515_mc_wait_for_idle(struct radeon_device *rdev);
  54.  
  55. #if 0
  56. /*
  57.  * MC
  58.  */
  59. int rv515_mc_init(struct radeon_device *rdev)
  60. {
  61.         uint32_t tmp;
  62.         int r;
  63.  
  64.         if (r100_debugfs_rbbm_init(rdev)) {
  65.                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  66.         }
  67.         if (rv515_debugfs_pipes_info_init(rdev)) {
  68.                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  69.         }
  70.         if (rv515_debugfs_ga_info_init(rdev)) {
  71.                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  72.         }
  73.  
  74.         rv515_gpu_init(rdev);
  75.         rv370_pcie_gart_disable(rdev);
  76.  
  77.         /* Setup GPU memory space */
  78.         rdev->mc.vram_location = 0xFFFFFFFFUL;
  79.         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  80.         if (rdev->flags & RADEON_IS_AGP) {
  81.                 r = radeon_agp_init(rdev);
  82.                 if (r) {
  83.                         printk(KERN_WARNING "[drm] Disabling AGP\n");
  84.                         rdev->flags &= ~RADEON_IS_AGP;
  85.                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  86.                 } else {
  87.                         rdev->mc.gtt_location = rdev->mc.agp_base;
  88.                 }
  89.         }
  90.         r = radeon_mc_setup(rdev);
  91.         if (r) {
  92.                 return r;
  93.         }
  94.  
  95.         /* Program GPU memory space */
  96.         rs600_mc_disable_clients(rdev);
  97.         if (rv515_mc_wait_for_idle(rdev)) {
  98.                 printk(KERN_WARNING "Failed to wait MC idle while "
  99.                        "programming pipes. Bad things might happen.\n");
  100.         }
  101.         /* Write VRAM size in case we are limiting it */
  102.         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
  103.         tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
  104.         WREG32(0x134, tmp);
  105.         tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
  106.         tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16);
  107.         tmp |= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16);
  108.         WREG32_MC(RV515_MC_FB_LOCATION, tmp);
  109.         WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
  110.         WREG32(0x310, rdev->mc.vram_location);
  111.         if (rdev->flags & RADEON_IS_AGP) {
  112.                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  113.                 tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16);
  114.                 tmp |= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16);
  115.                 WREG32_MC(RV515_MC_AGP_LOCATION, tmp);
  116.                 WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base);
  117.                 WREG32_MC(RV515_MC_AGP_BASE_2, 0);
  118.         } else {
  119.                 WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF);
  120.                 WREG32_MC(RV515_MC_AGP_BASE, 0);
  121.                 WREG32_MC(RV515_MC_AGP_BASE_2, 0);
  122.         }
  123.         return 0;
  124. }
  125.  
  126. void rv515_mc_fini(struct radeon_device *rdev)
  127. {
  128.         rv370_pcie_gart_disable(rdev);
  129.         radeon_gart_table_vram_free(rdev);
  130.         radeon_gart_fini(rdev);
  131. }
  132.  
  133. #endif
  134.  
  135. /*
  136.  * Global GPU functions
  137.  */
  138. void rv515_ring_start(struct radeon_device *rdev)
  139. {
  140.         unsigned gb_tile_config;
  141.         int r;
  142.  
  143.     dbgprintf("%s\n\r",__FUNCTION__);
  144.         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
  145.         gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16;
  146.         switch (rdev->num_gb_pipes) {
  147.         case 2:
  148.                 gb_tile_config |= R300_PIPE_COUNT_R300;
  149.                 break;
  150.         case 3:
  151.                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
  152.                 break;
  153.         case 4:
  154.                 gb_tile_config |= R300_PIPE_COUNT_R420;
  155.                 break;
  156.         case 1:
  157.         default:
  158.                 gb_tile_config |= R300_PIPE_COUNT_RV350;
  159.                 break;
  160.         }
  161.  
  162.         r = radeon_ring_lock(rdev, 64);
  163.         if (r) {
  164.                 return;
  165.         }
  166.         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
  167.         radeon_ring_write(rdev,
  168.                           RADEON_ISYNC_ANY2D_IDLE3D |
  169.                           RADEON_ISYNC_ANY3D_IDLE2D |
  170.                           RADEON_ISYNC_WAIT_IDLEGUI |
  171.                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
  172.         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
  173.         radeon_ring_write(rdev, gb_tile_config);
  174.         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
  175.         radeon_ring_write(rdev,
  176.                           RADEON_WAIT_2D_IDLECLEAN |
  177.                           RADEON_WAIT_3D_IDLECLEAN);
  178.         radeon_ring_write(rdev, PACKET0(0x170C, 0));
  179.         radeon_ring_write(rdev, 1 << 31);
  180.         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
  181.         radeon_ring_write(rdev, 0);
  182.         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
  183.         radeon_ring_write(rdev, 0);
  184.         radeon_ring_write(rdev, PACKET0(0x42C8, 0));
  185.         radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
  186.         radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0));
  187.         radeon_ring_write(rdev, 0);
  188.         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
  189.         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
  190.         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
  191.         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
  192.         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
  193.         radeon_ring_write(rdev,
  194.                           RADEON_WAIT_2D_IDLECLEAN |
  195.                           RADEON_WAIT_3D_IDLECLEAN);
  196.         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
  197.         radeon_ring_write(rdev, 0);
  198.         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
  199.         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
  200.         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
  201.         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
  202.         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
  203.         radeon_ring_write(rdev,
  204.                           ((6 << R300_MS_X0_SHIFT) |
  205.                            (6 << R300_MS_Y0_SHIFT) |
  206.                            (6 << R300_MS_X1_SHIFT) |
  207.                            (6 << R300_MS_Y1_SHIFT) |
  208.                            (6 << R300_MS_X2_SHIFT) |
  209.                            (6 << R300_MS_Y2_SHIFT) |
  210.                            (6 << R300_MSBD0_Y_SHIFT) |
  211.                            (6 << R300_MSBD0_X_SHIFT)));
  212.         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
  213.         radeon_ring_write(rdev,
  214.                           ((6 << R300_MS_X3_SHIFT) |
  215.                            (6 << R300_MS_Y3_SHIFT) |
  216.                            (6 << R300_MS_X4_SHIFT) |
  217.                            (6 << R300_MS_Y4_SHIFT) |
  218.                            (6 << R300_MS_X5_SHIFT) |
  219.                            (6 << R300_MS_Y5_SHIFT) |
  220.                            (6 << R300_MSBD1_SHIFT)));
  221.         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
  222.         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
  223.         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
  224.         radeon_ring_write(rdev,
  225.                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
  226.         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
  227.         radeon_ring_write(rdev,
  228.                           R300_GEOMETRY_ROUND_NEAREST |
  229.                           R300_COLOR_ROUND_NEAREST);
  230.         radeon_ring_write(rdev, PACKET0(0x20C8, 0));
  231.         radeon_ring_write(rdev, 0);
  232.         radeon_ring_unlock_commit(rdev);
  233.  
  234.     dbgprintf("done %s\n\r",__FUNCTION__);
  235.  
  236. }
  237.  
  238. void rv515_errata(struct radeon_device *rdev)
  239. {
  240.         rdev->pll_errata = 0;
  241. }
  242.  
  243. int rv515_mc_wait_for_idle(struct radeon_device *rdev)
  244. {
  245.         unsigned i;
  246.         uint32_t tmp;
  247.  
  248.         for (i = 0; i < rdev->usec_timeout; i++) {
  249.                 /* read MC_STATUS */
  250.                 tmp = RREG32_MC(RV515_MC_STATUS);
  251.                 if (tmp & RV515_MC_STATUS_IDLE) {
  252.                         return 0;
  253.                 }
  254.                 DRM_UDELAY(1);
  255.         }
  256.         return -1;
  257. }
  258.  
  259. #if 0
  260. void rv515_gpu_init(struct radeon_device *rdev)
  261. {
  262.         unsigned pipe_select_current, gb_pipe_select, tmp;
  263.  
  264.         r100_hdp_reset(rdev);
  265.         r100_rb2d_reset(rdev);
  266.  
  267.         if (r100_gui_wait_for_idle(rdev)) {
  268.                 printk(KERN_WARNING "Failed to wait GUI idle while "
  269.                        "reseting GPU. Bad things might happen.\n");
  270.         }
  271.  
  272.         rs600_disable_vga(rdev);
  273.  
  274.         r420_pipes_init(rdev);
  275.         gb_pipe_select = RREG32(0x402C);
  276.         tmp = RREG32(0x170C);
  277.         pipe_select_current = (tmp >> 2) & 3;
  278.         tmp = (1 << pipe_select_current) |
  279.               (((gb_pipe_select >> 8) & 0xF) << 4);
  280.         WREG32_PLL(0x000D, tmp);
  281.         if (r100_gui_wait_for_idle(rdev)) {
  282.                 printk(KERN_WARNING "Failed to wait GUI idle while "
  283.                        "reseting GPU. Bad things might happen.\n");
  284.         }
  285.         if (rv515_mc_wait_for_idle(rdev)) {
  286.                 printk(KERN_WARNING "Failed to wait MC idle while "
  287.                        "programming pipes. Bad things might happen.\n");
  288.         }
  289. }
  290.  
  291. #endif
  292.  
  293. int rv515_ga_reset(struct radeon_device *rdev)
  294. {
  295.         uint32_t tmp;
  296.         bool reinit_cp;
  297.         int i;
  298.  
  299.     dbgprintf("%s\n\r",__FUNCTION__);
  300.  
  301.         reinit_cp = rdev->cp.ready;
  302.         rdev->cp.ready = false;
  303.         for (i = 0; i < rdev->usec_timeout; i++) {
  304.                 WREG32(RADEON_CP_CSQ_MODE, 0);
  305.                 WREG32(RADEON_CP_CSQ_CNTL, 0);
  306.                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
  307.                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
  308.                 udelay(200);
  309.                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
  310.                 /* Wait to prevent race in RBBM_STATUS */
  311.                 mdelay(1);
  312.                 tmp = RREG32(RADEON_RBBM_STATUS);
  313.                 if (tmp & ((1 << 20) | (1 << 26))) {
  314.                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
  315.                         /* GA still busy soft reset it */
  316.                         WREG32(0x429C, 0x200);
  317.                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
  318.                         WREG32(0x43E0, 0);
  319.                         WREG32(0x43E4, 0);
  320.                         WREG32(0x24AC, 0);
  321.                 }
  322.                 /* Wait to prevent race in RBBM_STATUS */
  323.                 mdelay(1);
  324.                 tmp = RREG32(RADEON_RBBM_STATUS);
  325.                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
  326.                         break;
  327.                 }
  328.         }
  329.         for (i = 0; i < rdev->usec_timeout; i++) {
  330.                 tmp = RREG32(RADEON_RBBM_STATUS);
  331.                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
  332.                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
  333.                                  tmp);
  334.                         DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
  335.                         DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
  336.                         DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
  337.                         if (reinit_cp) {
  338.                                 return r100_cp_init(rdev, rdev->cp.ring_size);
  339.                         }
  340.                         return 0;
  341.                 }
  342.                 DRM_UDELAY(1);
  343.         }
  344.         tmp = RREG32(RADEON_RBBM_STATUS);
  345.         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
  346.         return -1;
  347. }
  348.  
  349. int rv515_gpu_reset(struct radeon_device *rdev)
  350. {
  351.         uint32_t status;
  352.  
  353.     dbgprintf("%s\n\r",__FUNCTION__);
  354.  
  355.         /* reset order likely matter */
  356.         status = RREG32(RADEON_RBBM_STATUS);
  357.         /* reset HDP */
  358.         r100_hdp_reset(rdev);
  359.         /* reset rb2d */
  360.         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
  361.                 r100_rb2d_reset(rdev);
  362.         }
  363.         /* reset GA */
  364.         if (status & ((1 << 20) | (1 << 26))) {
  365.                 rv515_ga_reset(rdev);
  366.         }
  367.         /* reset CP */
  368.         status = RREG32(RADEON_RBBM_STATUS);
  369.         if (status & (1 << 16)) {
  370.                 r100_cp_reset(rdev);
  371.         }
  372.         /* Check if GPU is idle */
  373.         status = RREG32(RADEON_RBBM_STATUS);
  374.         if (status & (1 << 31)) {
  375.                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
  376.                 return -1;
  377.         }
  378.         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
  379.         return 0;
  380. }
  381.  
  382.  
  383. /*
  384.  * VRAM info
  385.  */
  386. static void rv515_vram_get_type(struct radeon_device *rdev)
  387. {
  388.         uint32_t tmp;
  389.  
  390.         rdev->mc.vram_width = 128;
  391.         rdev->mc.vram_is_ddr = true;
  392.         tmp = RREG32_MC(RV515_MC_CNTL);
  393.         tmp &= RV515_MEM_NUM_CHANNELS_MASK;
  394.         switch (tmp) {
  395.         case 0:
  396.                 rdev->mc.vram_width = 64;
  397.                 break;
  398.         case 1:
  399.                 rdev->mc.vram_width = 128;
  400.                 break;
  401.         default:
  402.                 rdev->mc.vram_width = 128;
  403.                 break;
  404.         }
  405. }
  406.  
  407. void rv515_vram_info(struct radeon_device *rdev)
  408. {
  409.         rv515_vram_get_type(rdev);
  410.         rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
  411.  
  412.         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
  413.         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
  414. }
  415.  
  416.  
  417. /*
  418.  * Indirect registers accessor
  419.  */
  420. uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  421. {
  422.         uint32_t r;
  423.  
  424.         WREG32(R520_MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
  425.         r = RREG32(R520_MC_IND_DATA);
  426.         WREG32(R520_MC_IND_INDEX, 0);
  427.         return r;
  428. }
  429.  
  430. void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  431. {
  432.         WREG32(R520_MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
  433.         WREG32(R520_MC_IND_DATA, (v));
  434.         WREG32(R520_MC_IND_INDEX, 0);
  435. }
  436.  
  437. uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  438. {
  439.         uint32_t r;
  440.  
  441.         WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
  442.         (void)RREG32(RADEON_PCIE_INDEX);
  443.         r = RREG32(RADEON_PCIE_DATA);
  444.         return r;
  445. }
  446.  
  447. void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  448. {
  449.         WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff));
  450.         (void)RREG32(RADEON_PCIE_INDEX);
  451.         WREG32(RADEON_PCIE_DATA, (v));
  452.         (void)RREG32(RADEON_PCIE_DATA);
  453. }
  454.  
  455. #if 0
  456. /*
  457.  * Debugfs info
  458.  */
  459. #if defined(CONFIG_DEBUG_FS)
  460. static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
  461. {
  462.         struct drm_info_node *node = (struct drm_info_node *) m->private;
  463.         struct drm_device *dev = node->minor->dev;
  464.         struct radeon_device *rdev = dev->dev_private;
  465.         uint32_t tmp;
  466.  
  467.         tmp = RREG32(R400_GB_PIPE_SELECT);
  468.         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
  469.         tmp = RREG32(R500_SU_REG_DEST);
  470.         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
  471.         tmp = RREG32(R300_GB_TILE_CONFIG);
  472.         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
  473.         tmp = RREG32(R300_DST_PIPE_CONFIG);
  474.         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
  475.         return 0;
  476. }
  477.  
  478. static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
  479. {
  480.         struct drm_info_node *node = (struct drm_info_node *) m->private;
  481.         struct drm_device *dev = node->minor->dev;
  482.         struct radeon_device *rdev = dev->dev_private;
  483.         uint32_t tmp;
  484.  
  485.         tmp = RREG32(0x2140);
  486.         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
  487.         radeon_gpu_reset(rdev);
  488.         tmp = RREG32(0x425C);
  489.         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
  490.         return 0;
  491. }
  492.  
  493. static struct drm_info_list rv515_pipes_info_list[] = {
  494.         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
  495. };
  496.  
  497. static struct drm_info_list rv515_ga_info_list[] = {
  498.         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
  499. };
  500. #endif
  501.  
  502. int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
  503. {
  504. #if defined(CONFIG_DEBUG_FS)
  505.         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
  506. #else
  507.         return 0;
  508. #endif
  509. }
  510.  
  511. int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
  512. {
  513. #if defined(CONFIG_DEBUG_FS)
  514.         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
  515. #else
  516.         return 0;
  517. #endif
  518. }
  519.  
  520. #endif
  521.  
  522. /*
  523.  * Asic initialization
  524.  */
  525. static const unsigned r500_reg_safe_bm[159] = {
  526.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  527.         0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF,
  528.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  529.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  530.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  531.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  532.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  533.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  534.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  535.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  536.         0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
  537.         0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
  538.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  539.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  540.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
  541.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  542.         0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
  543.         0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
  544.         0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF,
  545.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  546.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  547.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  548.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  549.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  550.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  551.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  552.         0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  553.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  554.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  555.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  556.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  557.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  558.         0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF,
  559.         0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF,
  560.         0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
  561.         0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF,
  562.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  563.         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF,
  564.         0x00000000, 0x00000000, 0x00000000, 0x00000000,
  565.         0x0003FC01, 0x3FFFFCF8, 0xFE800B19,
  566. };
  567.  
  568.  
  569.  
  570. int rv515_init(struct radeon_device *rdev)
  571. {
  572.     dbgprintf("%s\n\r",__FUNCTION__);
  573.  
  574.         rdev->config.r300.reg_safe_bm = r500_reg_safe_bm;
  575.         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm);
  576.         return 0;
  577. }
  578.