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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. /* RS600 / Radeon X1250/X1270 integrated GPU
  29.  *
  30.  * This file gather function specific to RS600 which is the IGP of
  31.  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32.  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33.  * the avivo one, bios is an atombios, 3D block are the one of the
  34.  * R4XX family. The GART is different from the RS400 one and is very
  35.  * close to the one of the R600 family (R600 likely being an evolution
  36.  * of the RS600 GART block).
  37.  */
  38. #include "drmP.h"
  39. #include "radeon.h"
  40. #include "atom.h"
  41. #include "rs600d.h"
  42.  
  43. #include "rs600_reg_safe.h"
  44.  
  45. void rs600_gpu_init(struct radeon_device *rdev);
  46. int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  47.  
  48. /* hpd for digital panel detect/disconnect */
  49. bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  50. {
  51.         u32 tmp;
  52.         bool connected = false;
  53.  
  54.         switch (hpd) {
  55.         case RADEON_HPD_1:
  56.                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
  57.                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
  58.                         connected = true;
  59.                 break;
  60.         case RADEON_HPD_2:
  61.                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
  62.                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
  63.                         connected = true;
  64.                 break;
  65.         default:
  66.                 break;
  67.         }
  68.         return connected;
  69. }
  70.  
  71. void rs600_hpd_set_polarity(struct radeon_device *rdev,
  72.                             enum radeon_hpd_id hpd)
  73. {
  74.         u32 tmp;
  75.         bool connected = rs600_hpd_sense(rdev, hpd);
  76.  
  77.         switch (hpd) {
  78.         case RADEON_HPD_1:
  79.                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
  80.                 if (connected)
  81.                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
  82.                 else
  83.                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
  84.                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  85.                 break;
  86.         case RADEON_HPD_2:
  87.                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
  88.                 if (connected)
  89.                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
  90.                 else
  91.                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
  92.                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  93.                 break;
  94.         default:
  95.                 break;
  96.         }
  97. }
  98.  
  99. void rs600_hpd_init(struct radeon_device *rdev)
  100. {
  101.         struct drm_device *dev = rdev->ddev;
  102.         struct drm_connector *connector;
  103.  
  104.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  105.                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  106.                 switch (radeon_connector->hpd.hpd) {
  107.                 case RADEON_HPD_1:
  108.                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
  109.                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
  110. //           rdev->irq.hpd[0] = true;
  111.                         break;
  112.                 case RADEON_HPD_2:
  113.                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
  114.                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
  115. //           rdev->irq.hpd[1] = true;
  116.                         break;
  117.                 default:
  118.                         break;
  119.                 }
  120.         }
  121. //   if (rdev->irq.installed)
  122. //   rs600_irq_set(rdev);
  123. }
  124.  
  125. void rs600_hpd_fini(struct radeon_device *rdev)
  126. {
  127.         struct drm_device *dev = rdev->ddev;
  128.         struct drm_connector *connector;
  129.  
  130.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  131.                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  132.                 switch (radeon_connector->hpd.hpd) {
  133.                 case RADEON_HPD_1:
  134.                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
  135.                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
  136. //           rdev->irq.hpd[0] = false;
  137.                         break;
  138.                 case RADEON_HPD_2:
  139.                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
  140.                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
  141. //           rdev->irq.hpd[1] = false;
  142.                         break;
  143.                 default:
  144.                         break;
  145.                 }
  146.         }
  147. }
  148.  
  149. /*
  150.  * GART.
  151.  */
  152. void rs600_gart_tlb_flush(struct radeon_device *rdev)
  153. {
  154.         uint32_t tmp;
  155.  
  156.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  157.         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  158.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  159.  
  160.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  161.         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
  162.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  163.  
  164.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  165.         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  166.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  167.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  168. }
  169.  
  170. int rs600_gart_init(struct radeon_device *rdev)
  171. {
  172.         int r;
  173.  
  174.         if (rdev->gart.table.vram.robj) {
  175.                 WARN(1, "RS600 GART already initialized.\n");
  176.                 return 0;
  177.         }
  178.         /* Initialize common gart structure */
  179.         r = radeon_gart_init(rdev);
  180.         if (r) {
  181.                 return r;
  182.         }
  183.         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
  184.         return radeon_gart_table_vram_alloc(rdev);
  185. }
  186.  
  187. int rs600_gart_enable(struct radeon_device *rdev)
  188. {
  189.         u32 tmp;
  190.         int r, i;
  191.  
  192.         if (rdev->gart.table.vram.robj == NULL) {
  193.                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  194.                 return -EINVAL;
  195.         }
  196.         r = radeon_gart_table_vram_pin(rdev);
  197.         if (r)
  198.                 return r;
  199.         radeon_gart_restore(rdev);
  200.         /* Enable bus master */
  201.         tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
  202.         WREG32(R_00004C_BUS_CNTL, tmp);
  203.         /* FIXME: setup default page */
  204.         WREG32_MC(R_000100_MC_PT0_CNTL,
  205.                  (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
  206.                   S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
  207.  
  208.         for (i = 0; i < 19; i++) {
  209.                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
  210.                         S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
  211.                         S_00016C_SYSTEM_ACCESS_MODE_MASK(
  212.                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
  213.                         S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
  214.                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
  215.                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
  216.                         S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
  217.                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
  218.         }
  219.         /* enable first context */
  220.         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
  221.                         S_000102_ENABLE_PAGE_TABLE(1) |
  222.                         S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
  223.  
  224.         /* disable all other contexts */
  225.         for (i = 1; i < 8; i++)
  226.                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
  227.  
  228.         /* setup the page table */
  229.         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
  230.                  rdev->gart.table_addr);
  231.         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
  232.         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
  233.         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
  234.  
  235.         /* System context maps to VRAM space */
  236.         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
  237.         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
  238.  
  239.         /* enable page tables */
  240.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  241.         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
  242.         tmp = RREG32_MC(R_000009_MC_CNTL1);
  243.         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
  244.         rs600_gart_tlb_flush(rdev);
  245.         rdev->gart.ready = true;
  246.         return 0;
  247. }
  248.  
  249. void rs600_gart_disable(struct radeon_device *rdev)
  250. {
  251.         u32 tmp;
  252.         int r;
  253.  
  254.         /* FIXME: disable out of gart access */
  255.         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
  256.         tmp = RREG32_MC(R_000009_MC_CNTL1);
  257.         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
  258.         if (rdev->gart.table.vram.robj) {
  259.                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
  260.                 if (r == 0) {
  261.                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
  262.                         radeon_bo_unpin(rdev->gart.table.vram.robj);
  263.                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
  264.                 }
  265.         }
  266. }
  267.  
  268. void rs600_gart_fini(struct radeon_device *rdev)
  269. {
  270.         rs600_gart_disable(rdev);
  271.         radeon_gart_table_vram_free(rdev);
  272.         radeon_gart_fini(rdev);
  273. }
  274.  
  275. #define R600_PTE_VALID     (1 << 0)
  276. #define R600_PTE_SYSTEM    (1 << 1)
  277. #define R600_PTE_SNOOPED   (1 << 2)
  278. #define R600_PTE_READABLE  (1 << 5)
  279. #define R600_PTE_WRITEABLE (1 << 6)
  280.  
  281. int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  282. {
  283.         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  284.  
  285.         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  286.                 return -EINVAL;
  287.         }
  288.         addr = addr & 0xFFFFFFFFFFFFF000ULL;
  289.         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
  290.         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
  291.         writeq(addr, ((void __iomem *)ptr) + (i * 8));
  292.         return 0;
  293. }
  294.  
  295. /*
  296. int rs600_irq_set(struct radeon_device *rdev)
  297. {
  298.         uint32_t tmp = 0;
  299.         uint32_t mode_int = 0;
  300.         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
  301.                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
  302.         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
  303.                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
  304.  
  305.    if (!rdev->irq.installed) {
  306.                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
  307.                 WREG32(R_000040_GEN_INT_CNTL, 0);
  308.                 return -EINVAL;
  309.         }
  310.         if (rdev->irq.sw_int) {
  311.                 tmp |= S_000040_SW_INT_EN(1);
  312.         }
  313.         if (rdev->irq.crtc_vblank_int[0]) {
  314.                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
  315.         }
  316.         if (rdev->irq.crtc_vblank_int[1]) {
  317.                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
  318.         }
  319.         if (rdev->irq.hpd[0]) {
  320.                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
  321.         }
  322.         if (rdev->irq.hpd[1]) {
  323.                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
  324.         }
  325.         WREG32(R_000040_GEN_INT_CNTL, tmp);
  326.         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
  327.         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
  328.         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
  329.         return 0;
  330. }
  331. */
  332.  
  333. static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
  334. {
  335.         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
  336.         uint32_t irq_mask = ~C_000044_SW_INT;
  337.         u32 tmp;
  338.  
  339.         if (G_000044_DISPLAY_INT_STAT(irqs)) {
  340.                 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
  341.                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
  342.                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
  343.                                 S_006534_D1MODE_VBLANK_ACK(1));
  344.                 }
  345.                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
  346.                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
  347.                                 S_006D34_D2MODE_VBLANK_ACK(1));
  348.                 }
  349.                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
  350.                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
  351.                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
  352.                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  353.                 }
  354.                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
  355.                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
  356.                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
  357.                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  358.                 }
  359.         } else {
  360.                 *r500_disp_int = 0;
  361.         }
  362.  
  363.         if (irqs) {
  364.                 WREG32(R_000044_GEN_INT_STATUS, irqs);
  365.         }
  366.         return irqs & irq_mask;
  367. }
  368.  
  369. void rs600_irq_disable(struct radeon_device *rdev)
  370. {
  371.         u32 tmp;
  372.  
  373.         WREG32(R_000040_GEN_INT_CNTL, 0);
  374.         WREG32(R_006540_DxMODE_INT_MASK, 0);
  375.         /* Wait and acknowledge irq */
  376.         mdelay(1);
  377.         rs600_irq_ack(rdev, &tmp);
  378. }
  379.  
  380.  
  381. u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
  382. {
  383.         if (crtc == 0)
  384.                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
  385.         else
  386.                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
  387. }
  388.  
  389. int rs600_mc_wait_for_idle(struct radeon_device *rdev)
  390. {
  391.         unsigned i;
  392.  
  393.         for (i = 0; i < rdev->usec_timeout; i++) {
  394.                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
  395.                         return 0;
  396.                 udelay(1);
  397.         }
  398.         return -1;
  399. }
  400.  
  401. void rs600_gpu_init(struct radeon_device *rdev)
  402. {
  403.         r100_hdp_reset(rdev);
  404.         r420_pipes_init(rdev);
  405.         /* Wait for mc idle */
  406.         if (rs600_mc_wait_for_idle(rdev))
  407.                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  408. }
  409.  
  410. void rs600_mc_init(struct radeon_device *rdev)
  411. {
  412.         u64 base;
  413.  
  414.         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
  415.         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
  416.         rdev->mc.vram_is_ddr = true;
  417.         rdev->mc.vram_width = 128;
  418.         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
  419.         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  420.         rdev->mc.visible_vram_size = rdev->mc.aper_size;
  421.         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
  422.         base = RREG32_MC(R_000004_MC_FB_LOCATION);
  423.         base = G_000004_MC_FB_START(base) << 16;
  424.         radeon_vram_location(rdev, &rdev->mc, base);
  425.         radeon_gtt_location(rdev, &rdev->mc);
  426. }
  427.  
  428. void rs600_bandwidth_update(struct radeon_device *rdev)
  429. {
  430.         /* FIXME: implement, should this be like rs690 ? */
  431. }
  432.  
  433. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  434. {
  435.         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  436.                 S_000070_MC_IND_CITF_ARB0(1));
  437.         return RREG32(R_000074_MC_IND_DATA);
  438. }
  439.  
  440. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  441. {
  442.         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  443.                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
  444.         WREG32(R_000074_MC_IND_DATA, v);
  445. }
  446.  
  447. void rs600_debugfs(struct radeon_device *rdev)
  448. {
  449.         if (r100_debugfs_rbbm_init(rdev))
  450.                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  451. }
  452.  
  453. void rs600_set_safe_registers(struct radeon_device *rdev)
  454. {
  455.         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
  456.         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
  457. }
  458.  
  459. static void rs600_mc_program(struct radeon_device *rdev)
  460. {
  461.         struct rv515_mc_save save;
  462.  
  463.         /* Stops all mc clients */
  464.         rv515_mc_stop(rdev, &save);
  465.  
  466.         /* Wait for mc idle */
  467.         if (rs600_mc_wait_for_idle(rdev))
  468.                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  469.  
  470.         /* FIXME: What does AGP means for such chipset ? */
  471.         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
  472.         WREG32_MC(R_000006_AGP_BASE, 0);
  473.         WREG32_MC(R_000007_AGP_BASE_2, 0);
  474.         /* Program MC */
  475.         WREG32_MC(R_000004_MC_FB_LOCATION,
  476.                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
  477.                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
  478.         WREG32(R_000134_HDP_FB_LOCATION,
  479.                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
  480.  
  481.         rv515_mc_resume(rdev, &save);
  482. }
  483.  
  484. static int rs600_startup(struct radeon_device *rdev)
  485. {
  486.         int r;
  487.  
  488.         rs600_mc_program(rdev);
  489.         /* Resume clock */
  490.         rv515_clock_startup(rdev);
  491.         /* Initialize GPU configuration (# pipes, ...) */
  492.         rs600_gpu_init(rdev);
  493.         /* Initialize GART (initialize after TTM so we can allocate
  494.          * memory through TTM but finalize after TTM) */
  495.         r = rs600_gart_enable(rdev);
  496.         if (r)
  497.         return r;
  498.         /* Enable IRQ */
  499. //      rs600_irq_set(rdev);
  500.         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  501.         /* 1M ring buffer */
  502.         r = r100_cp_init(rdev, 1024 * 1024);
  503.         if (r) {
  504.                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
  505.                 return r;
  506.         }
  507. //      r = r100_wb_init(rdev);
  508. //      if (r)
  509. //              dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
  510. //      r = r100_ib_init(rdev);
  511. //      if (r) {
  512. //              dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
  513. //              return r;
  514. //      }
  515.         return 0;
  516. }
  517.  
  518.  
  519.  
  520. int rs600_init(struct radeon_device *rdev)
  521. {
  522.         int r;
  523.  
  524.         /* Disable VGA */
  525.         rv515_vga_render_disable(rdev);
  526.         /* Initialize scratch registers */
  527.         radeon_scratch_init(rdev);
  528.         /* Initialize surface registers */
  529.         radeon_surface_init(rdev);
  530.         /* BIOS */
  531.         if (!radeon_get_bios(rdev)) {
  532.                 if (ASIC_IS_AVIVO(rdev))
  533.                         return -EINVAL;
  534.         }
  535.         if (rdev->is_atom_bios) {
  536.                 r = radeon_atombios_init(rdev);
  537.                 if (r)
  538.                         return r;
  539.         } else {
  540.                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
  541.                 return -EINVAL;
  542.         }
  543.         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  544.         if (radeon_gpu_reset(rdev)) {
  545.                 dev_warn(rdev->dev,
  546.                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  547.                         RREG32(R_000E40_RBBM_STATUS),
  548.                         RREG32(R_0007C0_CP_STAT));
  549.         }
  550.         /* check if cards are posted or not */
  551.         if (radeon_boot_test_post_card(rdev) == false)
  552.                 return -EINVAL;
  553.  
  554.         /* Initialize clocks */
  555.         radeon_get_clock_info(rdev->ddev);
  556.         /* Initialize power management */
  557.         radeon_pm_init(rdev);
  558.         /* initialize memory controller */
  559.         rs600_mc_init(rdev);
  560.         rs600_debugfs(rdev);
  561.         /* Fence driver */
  562. //      r = radeon_fence_driver_init(rdev);
  563. //      if (r)
  564. //              return r;
  565. //      r = radeon_irq_kms_init(rdev);
  566. //      if (r)
  567. //              return r;
  568.         /* Memory manager */
  569.         r = radeon_bo_init(rdev);
  570.         if (r)
  571.                 return r;
  572.         r = rs600_gart_init(rdev);
  573.         if (r)
  574.                 return r;
  575.         rs600_set_safe_registers(rdev);
  576.         rdev->accel_working = true;
  577.         r = rs600_startup(rdev);
  578.         if (r) {
  579.                 /* Somethings want wront with the accel init stop accel */
  580.                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
  581. //              r100_cp_fini(rdev);
  582. //              r100_wb_fini(rdev);
  583. //              r100_ib_fini(rdev);
  584.                 rs600_gart_fini(rdev);
  585. //              radeon_irq_kms_fini(rdev);
  586.                 rdev->accel_working = false;
  587.         }
  588.         return 0;
  589. }
  590.