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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. /* RS600 / Radeon X1250/X1270 integrated GPU
  29.  *
  30.  * This file gather function specific to RS600 which is the IGP of
  31.  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32.  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33.  * the avivo one, bios is an atombios, 3D block are the one of the
  34.  * R4XX family. The GART is different from the RS400 one and is very
  35.  * close to the one of the R600 family (R600 likely being an evolution
  36.  * of the RS600 GART block).
  37.  */
  38. #include "drmP.h"
  39. #include "radeon.h"
  40. #include "atom.h"
  41. #include "rs600d.h"
  42.  
  43. #include "rs600_reg_safe.h"
  44.  
  45. void rs600_gpu_init(struct radeon_device *rdev);
  46. int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  47.  
  48. /*
  49.  * GART.
  50.  */
  51. void rs600_gart_tlb_flush(struct radeon_device *rdev)
  52. {
  53.         uint32_t tmp;
  54.  
  55.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  56.         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  57.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  58.  
  59.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  60.         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) & S_000100_INVALIDATE_L2_CACHE(1);
  61.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  62.  
  63.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  64.         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  65.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  66.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  67. }
  68.  
  69. int rs600_gart_init(struct radeon_device *rdev)
  70. {
  71.         int r;
  72.  
  73.         if (rdev->gart.table.vram.robj) {
  74.                 WARN(1, "RS600 GART already initialized.\n");
  75.                 return 0;
  76.         }
  77.         /* Initialize common gart structure */
  78.         r = radeon_gart_init(rdev);
  79.         if (r) {
  80.                 return r;
  81.         }
  82.         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
  83.         return radeon_gart_table_vram_alloc(rdev);
  84. }
  85.  
  86. int rs600_gart_enable(struct radeon_device *rdev)
  87. {
  88.         u32 tmp;
  89.         int r, i;
  90.  
  91.         if (rdev->gart.table.vram.robj == NULL) {
  92.                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  93.                 return -EINVAL;
  94.         }
  95.         r = radeon_gart_table_vram_pin(rdev);
  96.         if (r)
  97.                 return r;
  98.         /* Enable bus master */
  99.         tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
  100.         WREG32(R_00004C_BUS_CNTL, tmp);
  101.         /* FIXME: setup default page */
  102.         WREG32_MC(R_000100_MC_PT0_CNTL,
  103.                  (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
  104.                   S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
  105.         for (i = 0; i < 19; i++) {
  106.                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
  107.                         S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
  108.                         S_00016C_SYSTEM_ACCESS_MODE_MASK(
  109.                                 V_00016C_SYSTEM_ACCESS_MODE_IN_SYS) |
  110.                         S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
  111.                                 V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE) |
  112.                         S_00016C_EFFECTIVE_L1_CACHE_SIZE(1) |
  113.                         S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
  114.                         S_00016C_EFFECTIVE_L1_QUEUE_SIZE(1));
  115.         }
  116.  
  117.         /* System context map to GART space */
  118.         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.gtt_start);
  119.         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.gtt_end);
  120.  
  121.         /* enable first context */
  122.         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
  123.         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
  124.         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
  125.                         S_000102_ENABLE_PAGE_TABLE(1) |
  126.                         S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
  127.         /* disable all other contexts */
  128.         for (i = 1; i < 8; i++) {
  129.                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
  130.         }
  131.  
  132.         /* setup the page table */
  133.         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
  134.                  rdev->gart.table_addr);
  135.         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
  136.  
  137.         /* enable page tables */
  138.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  139.         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
  140.         tmp = RREG32_MC(R_000009_MC_CNTL1);
  141.         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
  142.         rs600_gart_tlb_flush(rdev);
  143.         rdev->gart.ready = true;
  144.         return 0;
  145. }
  146.  
  147. void rs600_gart_disable(struct radeon_device *rdev)
  148. {
  149.         uint32_t tmp;
  150.  
  151.         /* FIXME: disable out of gart access */
  152.         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
  153.         tmp = RREG32_MC(R_000009_MC_CNTL1);
  154.         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
  155.         if (rdev->gart.table.vram.robj) {
  156. //   radeon_object_kunmap(rdev->gart.table.vram.robj);
  157. //   radeon_object_unpin(rdev->gart.table.vram.robj);
  158.         }
  159. }
  160.  
  161. void rs600_gart_fini(struct radeon_device *rdev)
  162. {
  163.         rs600_gart_disable(rdev);
  164.         radeon_gart_table_vram_free(rdev);
  165.         radeon_gart_fini(rdev);
  166. }
  167.  
  168. #define R600_PTE_VALID     (1 << 0)
  169. #define R600_PTE_SYSTEM    (1 << 1)
  170. #define R600_PTE_SNOOPED   (1 << 2)
  171. #define R600_PTE_READABLE  (1 << 5)
  172. #define R600_PTE_WRITEABLE (1 << 6)
  173.  
  174. int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  175. {
  176.         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  177.  
  178.         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  179.                 return -EINVAL;
  180.         }
  181.         addr = addr & 0xFFFFFFFFFFFFF000ULL;
  182.         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
  183.         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
  184.         writeq(addr, ((void __iomem *)ptr) + (i * 8));
  185.         return 0;
  186. }
  187.  
  188.  
  189.  
  190. static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
  191. {
  192.         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
  193.         uint32_t irq_mask = ~C_000044_SW_INT;
  194.  
  195.         if (G_000044_DISPLAY_INT_STAT(irqs)) {
  196.                 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
  197.                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
  198.                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
  199.                                 S_006534_D1MODE_VBLANK_ACK(1));
  200.                 }
  201.                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
  202.                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
  203.                                 S_006D34_D2MODE_VBLANK_ACK(1));
  204.                 }
  205.         } else {
  206.                 *r500_disp_int = 0;
  207.         }
  208.  
  209.         if (irqs) {
  210.                 WREG32(R_000044_GEN_INT_STATUS, irqs);
  211.         }
  212.         return irqs & irq_mask;
  213. }
  214.  
  215. void rs600_irq_disable(struct radeon_device *rdev)
  216. {
  217.         u32 tmp;
  218.  
  219.         WREG32(R_000040_GEN_INT_CNTL, 0);
  220.         WREG32(R_006540_DxMODE_INT_MASK, 0);
  221.         /* Wait and acknowledge irq */
  222.         mdelay(1);
  223.         rs600_irq_ack(rdev, &tmp);
  224. }
  225.  
  226.  
  227. u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
  228. {
  229.         if (crtc == 0)
  230.                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
  231.         else
  232.                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
  233. }
  234.  
  235. int rs600_mc_wait_for_idle(struct radeon_device *rdev)
  236. {
  237.         unsigned i;
  238.  
  239.         for (i = 0; i < rdev->usec_timeout; i++) {
  240.                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
  241.                         return 0;
  242.                 udelay(1);
  243.         }
  244.         return -1;
  245. }
  246.  
  247. void rs600_gpu_init(struct radeon_device *rdev)
  248. {
  249.         /* FIXME: HDP same place on rs600 ? */
  250.         r100_hdp_reset(rdev);
  251.         /* FIXME: is this correct ? */
  252.         r420_pipes_init(rdev);
  253.         /* Wait for mc idle */
  254.         if (rs600_mc_wait_for_idle(rdev))
  255.                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  256. }
  257.  
  258. void rs600_vram_info(struct radeon_device *rdev)
  259. {
  260.         /* FIXME: to do or is these values sane ? */
  261.         rdev->mc.vram_is_ddr = true;
  262.         rdev->mc.vram_width = 128;
  263. }
  264.  
  265. void rs600_bandwidth_update(struct radeon_device *rdev)
  266. {
  267.         /* FIXME: implement, should this be like rs690 ? */
  268. }
  269.  
  270. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  271. {
  272.         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  273.                 S_000070_MC_IND_CITF_ARB0(1));
  274.         return RREG32(R_000074_MC_IND_DATA);
  275. }
  276.  
  277. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  278. {
  279.         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  280.                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
  281.         WREG32(R_000074_MC_IND_DATA, v);
  282. }
  283.  
  284. void rs600_debugfs(struct radeon_device *rdev)
  285. {
  286.         if (r100_debugfs_rbbm_init(rdev))
  287.                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  288. }
  289.  
  290. void rs600_set_safe_registers(struct radeon_device *rdev)
  291. {
  292.         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
  293.         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
  294. }
  295.  
  296. static void rs600_mc_program(struct radeon_device *rdev)
  297. {
  298.         struct rv515_mc_save save;
  299.  
  300.         /* Stops all mc clients */
  301.         rv515_mc_stop(rdev, &save);
  302.  
  303.         /* Wait for mc idle */
  304.         if (rs600_mc_wait_for_idle(rdev))
  305.                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  306.  
  307.         /* FIXME: What does AGP means for such chipset ? */
  308.         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
  309.         WREG32_MC(R_000006_AGP_BASE, 0);
  310.         WREG32_MC(R_000007_AGP_BASE_2, 0);
  311.         /* Program MC */
  312.         WREG32_MC(R_000004_MC_FB_LOCATION,
  313.                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
  314.                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
  315.         WREG32(R_000134_HDP_FB_LOCATION,
  316.                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
  317.  
  318.         rv515_mc_resume(rdev, &save);
  319. }
  320.  
  321. static int rs600_startup(struct radeon_device *rdev)
  322. {
  323.         int r;
  324.  
  325.         rs600_mc_program(rdev);
  326.         /* Resume clock */
  327.         rv515_clock_startup(rdev);
  328.         /* Initialize GPU configuration (# pipes, ...) */
  329.         rs600_gpu_init(rdev);
  330.         /* Initialize GART (initialize after TTM so we can allocate
  331.          * memory through TTM but finalize after TTM) */
  332.         r = rs600_gart_enable(rdev);
  333.         if (r)
  334.         return r;
  335.         /* Enable IRQ */
  336. //      rdev->irq.sw_int = true;
  337. //      rs600_irq_set(rdev);
  338.         /* 1M ring buffer */
  339. //      r = r100_cp_init(rdev, 1024 * 1024);
  340. //      if (r) {
  341. //              dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
  342. //              return r;
  343. //      }
  344. //      r = r100_wb_init(rdev);
  345. //      if (r)
  346. //              dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
  347. //      r = r100_ib_init(rdev);
  348. //      if (r) {
  349. //              dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
  350. //              return r;
  351. //      }
  352.         return 0;
  353. }
  354.  
  355.  
  356.  
  357. int rs600_init(struct radeon_device *rdev)
  358. {
  359.         int r;
  360.  
  361.         /* Disable VGA */
  362.         rv515_vga_render_disable(rdev);
  363.         /* Initialize scratch registers */
  364.         radeon_scratch_init(rdev);
  365.         /* Initialize surface registers */
  366.         radeon_surface_init(rdev);
  367.         /* BIOS */
  368.         if (!radeon_get_bios(rdev)) {
  369.                 if (ASIC_IS_AVIVO(rdev))
  370.                         return -EINVAL;
  371.         }
  372.         if (rdev->is_atom_bios) {
  373.                 r = radeon_atombios_init(rdev);
  374.                 if (r)
  375.                         return r;
  376.         } else {
  377.                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
  378.                 return -EINVAL;
  379.         }
  380.         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  381.         if (radeon_gpu_reset(rdev)) {
  382.                 dev_warn(rdev->dev,
  383.                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  384.                         RREG32(R_000E40_RBBM_STATUS),
  385.                         RREG32(R_0007C0_CP_STAT));
  386.         }
  387.         /* check if cards are posted or not */
  388.         if (!radeon_card_posted(rdev) && rdev->bios) {
  389.                 DRM_INFO("GPU not posted. posting now...\n");
  390.                 atom_asic_init(rdev->mode_info.atom_context);
  391.         }
  392.         /* Initialize clocks */
  393.         radeon_get_clock_info(rdev->ddev);
  394.         /* Get vram informations */
  395.         rs600_vram_info(rdev);
  396.         /* Initialize memory controller (also test AGP) */
  397.         r = r420_mc_init(rdev);
  398.         if (r)
  399.                 return r;
  400.         rs600_debugfs(rdev);
  401.         /* Fence driver */
  402. //      r = radeon_fence_driver_init(rdev);
  403. //      if (r)
  404. //              return r;
  405. //      r = radeon_irq_kms_init(rdev);
  406. //      if (r)
  407. //              return r;
  408.         /* Memory manager */
  409.         r = radeon_object_init(rdev);
  410.         if (r)
  411.                 return r;
  412.         r = rs600_gart_init(rdev);
  413.         if (r)
  414.                 return r;
  415.         rs600_set_safe_registers(rdev);
  416.         rdev->accel_working = true;
  417.         r = rs600_startup(rdev);
  418.         if (r) {
  419.                 /* Somethings want wront with the accel init stop accel */
  420.                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
  421. //              rs600_suspend(rdev);
  422. //              r100_cp_fini(rdev);
  423. //              r100_wb_fini(rdev);
  424. //              r100_ib_fini(rdev);
  425.                 rs600_gart_fini(rdev);
  426. //              radeon_irq_kms_fini(rdev);
  427.                 rdev->accel_working = false;
  428.         }
  429.         return 0;
  430. }
  431.