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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. /* RS600 / Radeon X1250/X1270 integrated GPU
  29.  *
  30.  * This file gather function specific to RS600 which is the IGP of
  31.  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
  32.  * is the X1250/X1270 supporting AMD CPU). The display engine are
  33.  * the avivo one, bios is an atombios, 3D block are the one of the
  34.  * R4XX family. The GART is different from the RS400 one and is very
  35.  * close to the one of the R600 family (R600 likely being an evolution
  36.  * of the RS600 GART block).
  37.  */
  38. #include "drmP.h"
  39. #include "radeon.h"
  40. #include "radeon_asic.h"
  41. #include "atom.h"
  42. #include "rs600d.h"
  43.  
  44. #include "rs600_reg_safe.h"
  45.  
  46. void rs600_gpu_init(struct radeon_device *rdev);
  47. int rs600_mc_wait_for_idle(struct radeon_device *rdev);
  48.  
  49. /* hpd for digital panel detect/disconnect */
  50. bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  51. {
  52.         u32 tmp;
  53.         bool connected = false;
  54.  
  55.         switch (hpd) {
  56.         case RADEON_HPD_1:
  57.                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
  58.                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
  59.                         connected = true;
  60.                 break;
  61.         case RADEON_HPD_2:
  62.                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
  63.                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
  64.                         connected = true;
  65.                 break;
  66.         default:
  67.                 break;
  68.         }
  69.         return connected;
  70. }
  71.  
  72. void rs600_hpd_set_polarity(struct radeon_device *rdev,
  73.                             enum radeon_hpd_id hpd)
  74. {
  75.         u32 tmp;
  76.         bool connected = rs600_hpd_sense(rdev, hpd);
  77.  
  78.         switch (hpd) {
  79.         case RADEON_HPD_1:
  80.                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
  81.                 if (connected)
  82.                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
  83.                 else
  84.                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
  85.                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  86.                 break;
  87.         case RADEON_HPD_2:
  88.                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
  89.                 if (connected)
  90.                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
  91.                 else
  92.                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
  93.                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  94.                 break;
  95.         default:
  96.                 break;
  97.         }
  98. }
  99.  
  100. void rs600_hpd_init(struct radeon_device *rdev)
  101. {
  102.         struct drm_device *dev = rdev->ddev;
  103.         struct drm_connector *connector;
  104.  
  105.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  106.                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  107.                 switch (radeon_connector->hpd.hpd) {
  108.                 case RADEON_HPD_1:
  109.                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
  110.                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
  111. //           rdev->irq.hpd[0] = true;
  112.                         break;
  113.                 case RADEON_HPD_2:
  114.                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
  115.                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
  116. //           rdev->irq.hpd[1] = true;
  117.                         break;
  118.                 default:
  119.                         break;
  120.                 }
  121.         }
  122. //   if (rdev->irq.installed)
  123. //   rs600_irq_set(rdev);
  124. }
  125.  
  126. void rs600_hpd_fini(struct radeon_device *rdev)
  127. {
  128.         struct drm_device *dev = rdev->ddev;
  129.         struct drm_connector *connector;
  130.  
  131.         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  132.                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  133.                 switch (radeon_connector->hpd.hpd) {
  134.                 case RADEON_HPD_1:
  135.                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
  136.                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
  137. //           rdev->irq.hpd[0] = false;
  138.                         break;
  139.                 case RADEON_HPD_2:
  140.                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
  141.                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
  142. //           rdev->irq.hpd[1] = false;
  143.                         break;
  144.                 default:
  145.                         break;
  146.                 }
  147.         }
  148. }
  149.  
  150. void rs600_bm_disable(struct radeon_device *rdev)
  151. {
  152.         u32 tmp;
  153.  
  154.         /* disable bus mastering */
  155.     tmp = PciRead16(rdev->pdev->bus, rdev->pdev->devfn, 0x4);
  156.     PciWrite16(rdev->pdev->bus, rdev->pdev->devfn, 0x4, tmp & 0xFFFB);
  157. mdelay(1);
  158. }
  159.  
  160. int rs600_asic_reset(struct radeon_device *rdev)
  161. {
  162.         struct rv515_mc_save save;
  163.         u32 status, tmp;
  164.         int ret = 0;
  165.  
  166.         status = RREG32(R_000E40_RBBM_STATUS);
  167.         if (!G_000E40_GUI_ACTIVE(status)) {
  168.                 return 0;
  169.         }
  170.         /* Stops all mc clients */
  171.         rv515_mc_stop(rdev, &save);
  172.         status = RREG32(R_000E40_RBBM_STATUS);
  173.         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  174.         /* stop CP */
  175.         WREG32(RADEON_CP_CSQ_CNTL, 0);
  176.         tmp = RREG32(RADEON_CP_RB_CNTL);
  177.         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
  178.         WREG32(RADEON_CP_RB_RPTR_WR, 0);
  179.         WREG32(RADEON_CP_RB_WPTR, 0);
  180.         WREG32(RADEON_CP_RB_CNTL, tmp);
  181. //   pci_save_state(rdev->pdev);
  182.         /* disable bus mastering */
  183.         rs600_bm_disable(rdev);
  184.         /* reset GA+VAP */
  185.         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
  186.                                         S_0000F0_SOFT_RESET_GA(1));
  187.         RREG32(R_0000F0_RBBM_SOFT_RESET);
  188.         mdelay(500);
  189.         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  190.         mdelay(1);
  191.         status = RREG32(R_000E40_RBBM_STATUS);
  192.         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  193.         /* reset CP */
  194.         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
  195.         RREG32(R_0000F0_RBBM_SOFT_RESET);
  196.         mdelay(500);
  197.         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  198.         mdelay(1);
  199.         status = RREG32(R_000E40_RBBM_STATUS);
  200.         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  201.         /* reset MC */
  202.         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
  203.         RREG32(R_0000F0_RBBM_SOFT_RESET);
  204.         mdelay(500);
  205.         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  206.         mdelay(1);
  207.         status = RREG32(R_000E40_RBBM_STATUS);
  208.         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  209.         /* restore PCI & busmastering */
  210. //   pci_restore_state(rdev->pdev);
  211.         /* Check if GPU is idle */
  212.         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
  213.                 dev_err(rdev->dev, "failed to reset GPU\n");
  214.                 rdev->gpu_lockup = true;
  215.                 ret = -1;
  216.         } else
  217.                 dev_info(rdev->dev, "GPU reset succeed\n");
  218.         rv515_mc_resume(rdev, &save);
  219.         return ret;
  220. }
  221.  
  222. /*
  223.  * GART.
  224.  */
  225. void rs600_gart_tlb_flush(struct radeon_device *rdev)
  226. {
  227.         uint32_t tmp;
  228.  
  229.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  230.         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  231.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  232.  
  233.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  234.         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
  235.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  236.  
  237.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  238.         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
  239.         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
  240.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  241. }
  242.  
  243. int rs600_gart_init(struct radeon_device *rdev)
  244. {
  245.         int r;
  246.  
  247.         if (rdev->gart.table.vram.robj) {
  248.                 WARN(1, "RS600 GART already initialized\n");
  249.                 return 0;
  250.         }
  251.         /* Initialize common gart structure */
  252.         r = radeon_gart_init(rdev);
  253.         if (r) {
  254.                 return r;
  255.         }
  256.         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
  257.         return radeon_gart_table_vram_alloc(rdev);
  258. }
  259.  
  260. int rs600_gart_enable(struct radeon_device *rdev)
  261. {
  262.         u32 tmp;
  263.         int r, i;
  264.  
  265.         if (rdev->gart.table.vram.robj == NULL) {
  266.                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  267.                 return -EINVAL;
  268.         }
  269.         r = radeon_gart_table_vram_pin(rdev);
  270.         if (r)
  271.                 return r;
  272.         radeon_gart_restore(rdev);
  273.         /* Enable bus master */
  274.         tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
  275.         WREG32(R_00004C_BUS_CNTL, tmp);
  276.         /* FIXME: setup default page */
  277.         WREG32_MC(R_000100_MC_PT0_CNTL,
  278.                  (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
  279.                   S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
  280.  
  281.         for (i = 0; i < 19; i++) {
  282.                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
  283.                         S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
  284.                         S_00016C_SYSTEM_ACCESS_MODE_MASK(
  285.                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
  286.                         S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
  287.                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
  288.                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
  289.                         S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
  290.                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
  291.         }
  292.         /* enable first context */
  293.         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
  294.                         S_000102_ENABLE_PAGE_TABLE(1) |
  295.                         S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
  296.  
  297.         /* disable all other contexts */
  298.         for (i = 1; i < 8; i++)
  299.                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
  300.  
  301.         /* setup the page table */
  302.         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
  303.                  rdev->gart.table_addr);
  304.         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
  305.         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
  306.         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
  307.  
  308.         /* System context maps to VRAM space */
  309.         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
  310.         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
  311.  
  312.         /* enable page tables */
  313.         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
  314.         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
  315.         tmp = RREG32_MC(R_000009_MC_CNTL1);
  316.         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
  317.         rs600_gart_tlb_flush(rdev);
  318.         rdev->gart.ready = true;
  319.         return 0;
  320. }
  321.  
  322. void rs600_gart_disable(struct radeon_device *rdev)
  323. {
  324.         u32 tmp;
  325.         int r;
  326.  
  327.         /* FIXME: disable out of gart access */
  328.         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
  329.         tmp = RREG32_MC(R_000009_MC_CNTL1);
  330.         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
  331.         if (rdev->gart.table.vram.robj) {
  332.                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
  333.                 if (r == 0) {
  334.                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
  335.                         radeon_bo_unpin(rdev->gart.table.vram.robj);
  336.                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
  337.                 }
  338.         }
  339. }
  340.  
  341. void rs600_gart_fini(struct radeon_device *rdev)
  342. {
  343.         radeon_gart_fini(rdev);
  344.         rs600_gart_disable(rdev);
  345.         radeon_gart_table_vram_free(rdev);
  346. }
  347.  
  348. #define R600_PTE_VALID     (1 << 0)
  349. #define R600_PTE_SYSTEM    (1 << 1)
  350. #define R600_PTE_SNOOPED   (1 << 2)
  351. #define R600_PTE_READABLE  (1 << 5)
  352. #define R600_PTE_WRITEABLE (1 << 6)
  353.  
  354. int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  355. {
  356.         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
  357.  
  358.         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  359.                 return -EINVAL;
  360.         }
  361.         addr = addr & 0xFFFFFFFFFFFFF000ULL;
  362.         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
  363.         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
  364.         writeq(addr, ((void __iomem *)ptr) + (i * 8));
  365.         return 0;
  366. }
  367.  
  368. #if 0
  369.  
  370. int rs600_irq_set(struct radeon_device *rdev)
  371. {
  372.         uint32_t tmp = 0;
  373.         uint32_t mode_int = 0;
  374.         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
  375.                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
  376.         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
  377.                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
  378.  
  379.    if (!rdev->irq.installed) {
  380.                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
  381.                 WREG32(R_000040_GEN_INT_CNTL, 0);
  382.                 return -EINVAL;
  383.         }
  384.         if (rdev->irq.sw_int) {
  385.                 tmp |= S_000040_SW_INT_EN(1);
  386.         }
  387.         if (rdev->irq.gui_idle) {
  388.                 tmp |= S_000040_GUI_IDLE(1);
  389.         }
  390.         if (rdev->irq.crtc_vblank_int[0] ||
  391.             rdev->irq.pflip[0]) {
  392.                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
  393.         }
  394.         if (rdev->irq.crtc_vblank_int[1] ||
  395.             rdev->irq.pflip[1]) {
  396.                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
  397.         }
  398.         if (rdev->irq.hpd[0]) {
  399.                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
  400.         }
  401.         if (rdev->irq.hpd[1]) {
  402.                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
  403.         }
  404.         WREG32(R_000040_GEN_INT_CNTL, tmp);
  405.         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
  406.         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
  407.         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
  408.         return 0;
  409. }
  410.  
  411. static inline u32 rs600_irq_ack(struct radeon_device *rdev)
  412. {
  413.         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
  414.         uint32_t irq_mask = S_000044_SW_INT(1);
  415.         u32 tmp;
  416.  
  417.         /* the interrupt works, but the status bit is permanently asserted */
  418.         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
  419.                 if (!rdev->irq.gui_idle_acked)
  420.                         irq_mask |= S_000044_GUI_IDLE_STAT(1);
  421.         }
  422.  
  423.         if (G_000044_DISPLAY_INT_STAT(irqs)) {
  424.                 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
  425.                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  426.                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
  427.                                 S_006534_D1MODE_VBLANK_ACK(1));
  428.                 }
  429.                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  430.                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
  431.                                 S_006D34_D2MODE_VBLANK_ACK(1));
  432.                 }
  433.                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  434.                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
  435.                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
  436.                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
  437.                 }
  438.                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
  439.                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
  440.                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
  441.                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
  442.                 }
  443.         } else {
  444.                 rdev->irq.stat_regs.r500.disp_int = 0;
  445.         }
  446.  
  447.         if (irqs) {
  448.                 WREG32(R_000044_GEN_INT_STATUS, irqs);
  449.         }
  450.         return irqs & irq_mask;
  451. }
  452.  
  453. void rs600_irq_disable(struct radeon_device *rdev)
  454. {
  455.         WREG32(R_000040_GEN_INT_CNTL, 0);
  456.         WREG32(R_006540_DxMODE_INT_MASK, 0);
  457.         /* Wait and acknowledge irq */
  458.         mdelay(1);
  459.         rs600_irq_ack(rdev);
  460. }
  461.  
  462. #endif
  463.  
  464. u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
  465. {
  466.         if (crtc == 0)
  467.                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
  468.         else
  469.                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
  470. }
  471.  
  472. int rs600_mc_wait_for_idle(struct radeon_device *rdev)
  473. {
  474.         unsigned i;
  475.  
  476.         for (i = 0; i < rdev->usec_timeout; i++) {
  477.                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
  478.                         return 0;
  479.                 udelay(1);
  480.         }
  481.         return -1;
  482. }
  483.  
  484. void rs600_gpu_init(struct radeon_device *rdev)
  485. {
  486.         r420_pipes_init(rdev);
  487.         /* Wait for mc idle */
  488.         if (rs600_mc_wait_for_idle(rdev))
  489.                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  490. }
  491.  
  492. void rs600_mc_init(struct radeon_device *rdev)
  493. {
  494.         u64 base;
  495.  
  496.         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
  497.         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
  498.         rdev->mc.vram_is_ddr = true;
  499.         rdev->mc.vram_width = 128;
  500.         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
  501.         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  502.         rdev->mc.visible_vram_size = rdev->mc.aper_size;
  503.         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
  504.         base = RREG32_MC(R_000004_MC_FB_LOCATION);
  505.         base = G_000004_MC_FB_START(base) << 16;
  506.         radeon_vram_location(rdev, &rdev->mc, base);
  507.         rdev->mc.gtt_base_align = 0;
  508.         radeon_gtt_location(rdev, &rdev->mc);
  509.         radeon_update_bandwidth_info(rdev);
  510. }
  511.  
  512. void rs600_bandwidth_update(struct radeon_device *rdev)
  513. {
  514.         struct drm_display_mode *mode0 = NULL;
  515.         struct drm_display_mode *mode1 = NULL;
  516.         u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
  517.         /* FIXME: implement full support */
  518.  
  519.         radeon_update_display_priority(rdev);
  520.  
  521.         if (rdev->mode_info.crtcs[0]->base.enabled)
  522.                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
  523.         if (rdev->mode_info.crtcs[1]->base.enabled)
  524.                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
  525.  
  526.         rs690_line_buffer_adjust(rdev, mode0, mode1);
  527.  
  528.         if (rdev->disp_priority == 2) {
  529.                 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
  530.                 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
  531.                 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
  532.                 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
  533.                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
  534.                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
  535.                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
  536.                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
  537.         }
  538. }
  539.  
  540. uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  541. {
  542.         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  543.                 S_000070_MC_IND_CITF_ARB0(1));
  544.         return RREG32(R_000074_MC_IND_DATA);
  545. }
  546.  
  547. void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  548. {
  549.         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
  550.                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
  551.         WREG32(R_000074_MC_IND_DATA, v);
  552. }
  553.  
  554. void rs600_debugfs(struct radeon_device *rdev)
  555. {
  556.         if (r100_debugfs_rbbm_init(rdev))
  557.                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  558. }
  559.  
  560. void rs600_set_safe_registers(struct radeon_device *rdev)
  561. {
  562.         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
  563.         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
  564. }
  565.  
  566. static void rs600_mc_program(struct radeon_device *rdev)
  567. {
  568.         struct rv515_mc_save save;
  569.  
  570.         /* Stops all mc clients */
  571.         rv515_mc_stop(rdev, &save);
  572.  
  573.         /* Wait for mc idle */
  574.         if (rs600_mc_wait_for_idle(rdev))
  575.                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
  576.  
  577.         /* FIXME: What does AGP means for such chipset ? */
  578.         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
  579.         WREG32_MC(R_000006_AGP_BASE, 0);
  580.         WREG32_MC(R_000007_AGP_BASE_2, 0);
  581.         /* Program MC */
  582.         WREG32_MC(R_000004_MC_FB_LOCATION,
  583.                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
  584.                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
  585.         WREG32(R_000134_HDP_FB_LOCATION,
  586.                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
  587.  
  588.         rv515_mc_resume(rdev, &save);
  589. }
  590.  
  591. static int rs600_startup(struct radeon_device *rdev)
  592. {
  593.         int r;
  594.  
  595.         rs600_mc_program(rdev);
  596.         /* Resume clock */
  597.         rv515_clock_startup(rdev);
  598.         /* Initialize GPU configuration (# pipes, ...) */
  599.         rs600_gpu_init(rdev);
  600.         /* Initialize GART (initialize after TTM so we can allocate
  601.          * memory through TTM but finalize after TTM) */
  602.         r = rs600_gart_enable(rdev);
  603.         if (r)
  604.         return r;
  605.         /* Enable IRQ */
  606. //      rs600_irq_set(rdev);
  607.         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  608.         /* 1M ring buffer */
  609.         r = r100_cp_init(rdev, 1024 * 1024);
  610.         if (r) {
  611.                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
  612.                 return r;
  613.         }
  614. //      r = r100_ib_init(rdev);
  615. //      if (r) {
  616. //              dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
  617. //              return r;
  618. //      }
  619.         return 0;
  620. }
  621.  
  622.  
  623.  
  624. int rs600_init(struct radeon_device *rdev)
  625. {
  626.         int r;
  627.  
  628.         /* Disable VGA */
  629.         rv515_vga_render_disable(rdev);
  630.         /* Initialize scratch registers */
  631.         radeon_scratch_init(rdev);
  632.         /* Initialize surface registers */
  633.         radeon_surface_init(rdev);
  634.         /* restore some register to sane defaults */
  635.         r100_restore_sanity(rdev);
  636.         /* BIOS */
  637.         if (!radeon_get_bios(rdev)) {
  638.                 if (ASIC_IS_AVIVO(rdev))
  639.                         return -EINVAL;
  640.         }
  641.         if (rdev->is_atom_bios) {
  642.                 r = radeon_atombios_init(rdev);
  643.                 if (r)
  644.                         return r;
  645.         } else {
  646.                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
  647.                 return -EINVAL;
  648.         }
  649.         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  650.         if (radeon_asic_reset(rdev)) {
  651.                 dev_warn(rdev->dev,
  652.                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  653.                         RREG32(R_000E40_RBBM_STATUS),
  654.                         RREG32(R_0007C0_CP_STAT));
  655.         }
  656.         /* check if cards are posted or not */
  657.         if (radeon_boot_test_post_card(rdev) == false)
  658.                 return -EINVAL;
  659.  
  660.         /* Initialize clocks */
  661.         radeon_get_clock_info(rdev->ddev);
  662.         /* initialize memory controller */
  663.         rs600_mc_init(rdev);
  664.         rs600_debugfs(rdev);
  665.         /* Fence driver */
  666. //      r = radeon_fence_driver_init(rdev);
  667. //      if (r)
  668. //              return r;
  669. //      r = radeon_irq_kms_init(rdev);
  670. //      if (r)
  671. //              return r;
  672.         /* Memory manager */
  673.         r = radeon_bo_init(rdev);
  674.         if (r)
  675.                 return r;
  676.         r = rs600_gart_init(rdev);
  677.         if (r)
  678.                 return r;
  679.         rs600_set_safe_registers(rdev);
  680.         rdev->accel_working = true;
  681.         r = rs600_startup(rdev);
  682.         if (r) {
  683.                 /* Somethings want wront with the accel init stop accel */
  684.                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
  685. //              r100_cp_fini(rdev);
  686. //              r100_wb_fini(rdev);
  687. //              r100_ib_fini(rdev);
  688.                 rs600_gart_fini(rdev);
  689. //              radeon_irq_kms_fini(rdev);
  690.                 rdev->accel_working = false;
  691.         }
  692.         return 0;
  693. }
  694.