Subversion Repositories Kolibri OS

Rev

Rev 3764 | Rev 5139 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include <linux/seq_file.h>
  29. #include <linux/slab.h>
  30. #include <drm/drmP.h>
  31. #include "radeon.h"
  32. #include "radeon_asic.h"
  33. #include "rs400d.h"
  34.  
  35. /* This files gather functions specifics to : rs400,rs480 */
  36. static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  37.  
  38. void rs400_gart_adjust_size(struct radeon_device *rdev)
  39. {
  40.         /* Check gart size */
  41.         switch (rdev->mc.gtt_size/(1024*1024)) {
  42.         case 32:
  43.         case 64:
  44.         case 128:
  45.         case 256:
  46.         case 512:
  47.         case 1024:
  48.         case 2048:
  49.                 break;
  50.         default:
  51.                 DRM_ERROR("Unable to use IGP GART size %uM\n",
  52.                           (unsigned)(rdev->mc.gtt_size >> 20));
  53.                 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
  54.                 DRM_ERROR("Forcing to 32M GART size\n");
  55.                 rdev->mc.gtt_size = 32 * 1024 * 1024;
  56.                 return;
  57.         }
  58. }
  59.  
  60. void rs400_gart_tlb_flush(struct radeon_device *rdev)
  61. {
  62.         uint32_t tmp;
  63.         unsigned int timeout = rdev->usec_timeout;
  64.  
  65.         WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
  66.         do {
  67.                 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
  68.                 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
  69.                         break;
  70.                 DRM_UDELAY(1);
  71.                 timeout--;
  72.         } while (timeout > 0);
  73.         WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
  74. }
  75.  
  76. int rs400_gart_init(struct radeon_device *rdev)
  77. {
  78.         int r;
  79.  
  80.         if (rdev->gart.ptr) {
  81.                 WARN(1, "RS400 GART already initialized\n");
  82.                 return 0;
  83.         }
  84.         /* Check gart size */
  85.         switch(rdev->mc.gtt_size / (1024 * 1024)) {
  86.         case 32:
  87.         case 64:
  88.         case 128:
  89.         case 256:
  90.         case 512:
  91.         case 1024:
  92.         case 2048:
  93.                 break;
  94.         default:
  95.                 return -EINVAL;
  96.         }
  97.         /* Initialize common gart structure */
  98.         r = radeon_gart_init(rdev);
  99.         if (r)
  100.                 return r;
  101.         if (rs400_debugfs_pcie_gart_info_init(rdev))
  102.                 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
  103.         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
  104.         return radeon_gart_table_ram_alloc(rdev);
  105. }
  106.  
  107. int rs400_gart_enable(struct radeon_device *rdev)
  108. {
  109.         uint32_t size_reg;
  110.         uint32_t tmp;
  111.  
  112.         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
  113.         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
  114.         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
  115.         /* Check gart size */
  116.         switch(rdev->mc.gtt_size / (1024 * 1024)) {
  117.         case 32:
  118.                 size_reg = RS480_VA_SIZE_32MB;
  119.                 break;
  120.         case 64:
  121.                 size_reg = RS480_VA_SIZE_64MB;
  122.                 break;
  123.         case 128:
  124.                 size_reg = RS480_VA_SIZE_128MB;
  125.                 break;
  126.         case 256:
  127.                 size_reg = RS480_VA_SIZE_256MB;
  128.                 break;
  129.         case 512:
  130.                 size_reg = RS480_VA_SIZE_512MB;
  131.                 break;
  132.         case 1024:
  133.                 size_reg = RS480_VA_SIZE_1GB;
  134.                 break;
  135.         case 2048:
  136.                 size_reg = RS480_VA_SIZE_2GB;
  137.                 break;
  138.         default:
  139.                 return -EINVAL;
  140.         }
  141.         /* It should be fine to program it to max value */
  142.         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
  143.                 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
  144.                 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
  145.         } else {
  146.                 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
  147.                 WREG32(RS480_AGP_BASE_2, 0);
  148.         }
  149.         tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);
  150.         tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);
  151.         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
  152.                 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
  153.                 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
  154.                 WREG32(RADEON_BUS_CNTL, tmp);
  155.         } else {
  156.                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
  157.                 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
  158.                 WREG32(RADEON_BUS_CNTL, tmp);
  159.         }
  160.         /* Table should be in 32bits address space so ignore bits above. */
  161.         tmp = (u32)rdev->gart.table_addr & 0xfffff000;
  162.         tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
  163.  
  164.         WREG32_MC(RS480_GART_BASE, tmp);
  165.         /* TODO: more tweaking here */
  166.         WREG32_MC(RS480_GART_FEATURE_ID,
  167.                   (RS480_TLB_ENABLE |
  168.                    RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
  169.         /* Disable snooping */
  170.         WREG32_MC(RS480_AGP_MODE_CNTL,
  171.                   (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
  172.         /* Disable AGP mode */
  173.         /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
  174.          * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
  175.         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
  176.                 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
  177.                 tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN;
  178.                 WREG32_MC(RS480_MC_MISC_CNTL, tmp);
  179.         } else {
  180.                 tmp = RREG32_MC(RS480_MC_MISC_CNTL);
  181.                 tmp |= RS480_GART_INDEX_REG_EN;
  182.                 WREG32_MC(RS480_MC_MISC_CNTL, tmp);
  183.         }
  184.         /* Enable gart */
  185.         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
  186.         rs400_gart_tlb_flush(rdev);
  187.         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
  188.                  (unsigned)(rdev->mc.gtt_size >> 20),
  189.                  (unsigned long long)rdev->gart.table_addr);
  190.         rdev->gart.ready = true;
  191.         return 0;
  192. }
  193.  
  194. void rs400_gart_disable(struct radeon_device *rdev)
  195. {
  196.         uint32_t tmp;
  197.  
  198.         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
  199.         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
  200.         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
  201.         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
  202. }
  203.  
  204. void rs400_gart_fini(struct radeon_device *rdev)
  205. {
  206.         radeon_gart_fini(rdev);
  207.         rs400_gart_disable(rdev);
  208.         radeon_gart_table_ram_free(rdev);
  209. }
  210.  
  211. #define RS400_PTE_UNSNOOPED (1 << 0)
  212. #define RS400_PTE_WRITEABLE (1 << 2)
  213. #define RS400_PTE_READABLE  (1 << 3)
  214.  
  215. void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
  216.                          uint64_t addr, uint32_t flags)
  217. {
  218.         uint32_t entry;
  219.         u32 *gtt = rdev->gart.ptr;
  220.  
  221.         entry = (lower_32_bits(addr) & PAGE_MASK) |
  222.                 ((upper_32_bits(addr) & 0xff) << 4);
  223.         if (flags & RADEON_GART_PAGE_READ)
  224.                 addr |= RS400_PTE_READABLE;
  225.         if (flags & RADEON_GART_PAGE_WRITE)
  226.                 addr |= RS400_PTE_WRITEABLE;
  227.         if (!(flags & RADEON_GART_PAGE_SNOOP))
  228.                 entry |= RS400_PTE_UNSNOOPED;
  229.         entry = cpu_to_le32(entry);
  230.         gtt[i] = entry;
  231. }
  232.  
  233. int rs400_mc_wait_for_idle(struct radeon_device *rdev)
  234. {
  235.         unsigned i;
  236.         uint32_t tmp;
  237.  
  238.         for (i = 0; i < rdev->usec_timeout; i++) {
  239.                 /* read MC_STATUS */
  240.                 tmp = RREG32(RADEON_MC_STATUS);
  241.                 if (tmp & RADEON_MC_IDLE) {
  242.                         return 0;
  243.                 }
  244.                 DRM_UDELAY(1);
  245.         }
  246.         return -1;
  247. }
  248.  
  249. static void rs400_gpu_init(struct radeon_device *rdev)
  250. {
  251.         /* FIXME: is this correct ? */
  252.         r420_pipes_init(rdev);
  253.         if (rs400_mc_wait_for_idle(rdev)) {
  254.                 printk(KERN_WARNING "rs400: Failed to wait MC idle while "
  255.                        "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS));
  256.         }
  257. }
  258.  
  259. static void rs400_mc_init(struct radeon_device *rdev)
  260. {
  261.         u64 base;
  262.  
  263.         rs400_gart_adjust_size(rdev);
  264.         rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
  265.         /* DDR for all card after R300 & IGP */
  266.         rdev->mc.vram_is_ddr = true;
  267.         rdev->mc.vram_width = 128;
  268.         r100_vram_init_sizes(rdev);
  269.         base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
  270.         radeon_vram_location(rdev, &rdev->mc, base);
  271.         rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
  272.         radeon_gtt_location(rdev, &rdev->mc);
  273.         radeon_update_bandwidth_info(rdev);
  274. }
  275.  
  276. uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  277. {
  278.         unsigned long flags;
  279.         uint32_t r;
  280.  
  281.         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
  282.         WREG32(RS480_NB_MC_INDEX, reg & 0xff);
  283.         r = RREG32(RS480_NB_MC_DATA);
  284.         WREG32(RS480_NB_MC_INDEX, 0xff);
  285.         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
  286.         return r;
  287. }
  288.  
  289. void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  290. {
  291.         unsigned long flags;
  292.  
  293.         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
  294.         WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
  295.         WREG32(RS480_NB_MC_DATA, (v));
  296.         WREG32(RS480_NB_MC_INDEX, 0xff);
  297.         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
  298. }
  299.  
  300. #if defined(CONFIG_DEBUG_FS)
  301. static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
  302. {
  303.         struct drm_info_node *node = (struct drm_info_node *) m->private;
  304.         struct drm_device *dev = node->minor->dev;
  305.         struct radeon_device *rdev = dev->dev_private;
  306.         uint32_t tmp;
  307.  
  308.         tmp = RREG32(RADEON_HOST_PATH_CNTL);
  309.         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
  310.         tmp = RREG32(RADEON_BUS_CNTL);
  311.         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
  312.         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
  313.         seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
  314.         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
  315.                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
  316.                 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
  317.                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
  318.                 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
  319.                 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
  320.                 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
  321.                 tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
  322.                 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
  323.                 tmp = RREG32(RS690_HDP_FB_LOCATION);
  324.                 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
  325.         } else {
  326.                 tmp = RREG32(RADEON_AGP_BASE);
  327.                 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
  328.                 tmp = RREG32(RS480_AGP_BASE_2);
  329.                 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
  330.                 tmp = RREG32(RADEON_MC_AGP_LOCATION);
  331.                 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
  332.         }
  333.         tmp = RREG32_MC(RS480_GART_BASE);
  334.         seq_printf(m, "GART_BASE 0x%08x\n", tmp);
  335.         tmp = RREG32_MC(RS480_GART_FEATURE_ID);
  336.         seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
  337.         tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
  338.         seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
  339.         tmp = RREG32_MC(RS480_MC_MISC_CNTL);
  340.         seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
  341.         tmp = RREG32_MC(0x5F);
  342.         seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
  343.         tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
  344.         seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
  345.         tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
  346.         seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
  347.         tmp = RREG32_MC(0x3B);
  348.         seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
  349.         tmp = RREG32_MC(0x3C);
  350.         seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
  351.         tmp = RREG32_MC(0x30);
  352.         seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
  353.         tmp = RREG32_MC(0x31);
  354.         seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
  355.         tmp = RREG32_MC(0x32);
  356.         seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
  357.         tmp = RREG32_MC(0x33);
  358.         seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
  359.         tmp = RREG32_MC(0x34);
  360.         seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
  361.         tmp = RREG32_MC(0x35);
  362.         seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
  363.         tmp = RREG32_MC(0x36);
  364.         seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
  365.         tmp = RREG32_MC(0x37);
  366.         seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
  367.         return 0;
  368. }
  369.  
  370. static struct drm_info_list rs400_gart_info_list[] = {
  371.         {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
  372. };
  373. #endif
  374.  
  375. static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
  376. {
  377. #if defined(CONFIG_DEBUG_FS)
  378.         return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
  379. #else
  380.         return 0;
  381. #endif
  382. }
  383.  
  384. static void rs400_mc_program(struct radeon_device *rdev)
  385. {
  386.         struct r100_mc_save save;
  387.  
  388.         /* Stops all mc clients */
  389.         r100_mc_stop(rdev, &save);
  390.  
  391.         /* Wait for mc idle */
  392.         if (rs400_mc_wait_for_idle(rdev))
  393.                 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
  394.         WREG32(R_000148_MC_FB_LOCATION,
  395.                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
  396.                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
  397.  
  398.         r100_mc_resume(rdev, &save);
  399. }
  400.  
  401. static int rs400_startup(struct radeon_device *rdev)
  402. {
  403.         int r;
  404.  
  405.         r100_set_common_regs(rdev);
  406.  
  407.         rs400_mc_program(rdev);
  408.         /* Resume clock */
  409.         r300_clock_startup(rdev);
  410.         /* Initialize GPU configuration (# pipes, ...) */
  411.         rs400_gpu_init(rdev);
  412.         r100_enable_bm(rdev);
  413.         /* Initialize GART (initialize after TTM so we can allocate
  414.          * memory through TTM but finalize after TTM) */
  415.         r = rs400_gart_enable(rdev);
  416.         if (r)
  417.                 return r;
  418.  
  419.         /* allocate wb buffer */
  420.         r = radeon_wb_init(rdev);
  421.         if (r)
  422.                 return r;
  423.  
  424.         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  425.         if (r) {
  426.                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  427.                 return r;
  428.         }
  429.  
  430.         /* Enable IRQ */
  431.         if (!rdev->irq.installed) {
  432.                 r = radeon_irq_kms_init(rdev);
  433.                 if (r)
  434.                         return r;
  435.         }
  436.  
  437.         r100_irq_set(rdev);
  438.         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  439.         /* 1M ring buffer */
  440.    r = r100_cp_init(rdev, 1024 * 1024);
  441.    if (r) {
  442.                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
  443.        return r;
  444.    }
  445.  
  446.         r = radeon_ib_pool_init(rdev);
  447.         if (r) {
  448.                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  449.                 return r;
  450.         }
  451.  
  452.         return 0;
  453. }
  454.  
  455.  
  456.  
  457.  
  458. int rs400_init(struct radeon_device *rdev)
  459. {
  460.         int r;
  461.  
  462.         /* Disable VGA */
  463.         r100_vga_render_disable(rdev);
  464.         /* Initialize scratch registers */
  465.         radeon_scratch_init(rdev);
  466.         /* Initialize surface registers */
  467.         radeon_surface_init(rdev);
  468.         /* TODO: disable VGA need to use VGA request */
  469.         /* restore some register to sane defaults */
  470.         r100_restore_sanity(rdev);
  471.         /* BIOS*/
  472.         if (!radeon_get_bios(rdev)) {
  473.                 if (ASIC_IS_AVIVO(rdev))
  474.                         return -EINVAL;
  475.         }
  476.         if (rdev->is_atom_bios) {
  477.                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
  478.                 return -EINVAL;
  479.         } else {
  480.                 r = radeon_combios_init(rdev);
  481.                 if (r)
  482.                         return r;
  483.         }
  484.         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  485.         if (radeon_asic_reset(rdev)) {
  486.                 dev_warn(rdev->dev,
  487.                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  488.                         RREG32(R_000E40_RBBM_STATUS),
  489.                         RREG32(R_0007C0_CP_STAT));
  490.         }
  491.         /* check if cards are posted or not */
  492.         if (radeon_boot_test_post_card(rdev) == false)
  493.                 return -EINVAL;
  494.  
  495.         /* Initialize clocks */
  496.         radeon_get_clock_info(rdev->ddev);
  497.         /* initialize memory controller */
  498.         rs400_mc_init(rdev);
  499.         /* Fence driver */
  500.         r = radeon_fence_driver_init(rdev);
  501.         if (r)
  502.                 return r;
  503.         /* Memory manager */
  504.         r = radeon_bo_init(rdev);
  505.         if (r)
  506.                 return r;
  507.         r = rs400_gart_init(rdev);
  508.         if (r)
  509.                 return r;
  510.         r300_set_reg_safe(rdev);
  511.  
  512.         /* Initialize power management */
  513.         radeon_pm_init(rdev);
  514.  
  515.         rdev->accel_working = true;
  516.         r = rs400_startup(rdev);
  517.         if (r) {
  518.                 /* Somethings want wront with the accel init stop accel */
  519.                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
  520. //              r100_cp_fini(rdev);
  521. //              r100_wb_fini(rdev);
  522. //              r100_ib_fini(rdev);
  523.                 rs400_gart_fini(rdev);
  524. //              radeon_irq_kms_fini(rdev);
  525.                 rdev->accel_working = false;
  526.         }
  527.         return 0;
  528. }
  529.