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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include <linux/seq_file.h>
  29. #include <drm/drmP.h>
  30. #include "radeon_reg.h"
  31. #include "radeon.h"
  32.  
  33. /* rs400,rs480 depends on : */
  34. void r100_hdp_reset(struct radeon_device *rdev);
  35. void r100_mc_disable_clients(struct radeon_device *rdev);
  36. int r300_mc_wait_for_idle(struct radeon_device *rdev);
  37. void r420_pipes_init(struct radeon_device *rdev);
  38.  
  39. /* This files gather functions specifics to :
  40.  * rs400,rs480
  41.  *
  42.  * Some of these functions might be used by newer ASICs.
  43.  */
  44. void rs400_gpu_init(struct radeon_device *rdev);
  45. int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  46.  
  47.  
  48. /*
  49.  * GART functions.
  50.  */
  51. void rs400_gart_adjust_size(struct radeon_device *rdev)
  52. {
  53.         /* Check gart size */
  54.         switch (rdev->mc.gtt_size/(1024*1024)) {
  55.         case 32:
  56.         case 64:
  57.         case 128:
  58.         case 256:
  59.         case 512:
  60.         case 1024:
  61.         case 2048:
  62.                 break;
  63.         default:
  64.                 DRM_ERROR("Unable to use IGP GART size %uM\n",
  65.                           (unsigned)(rdev->mc.gtt_size >> 20));
  66.                 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n");
  67.                 DRM_ERROR("Forcing to 32M GART size\n");
  68.                 rdev->mc.gtt_size = 32 * 1024 * 1024;
  69.                 return;
  70.         }
  71.         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  72.                 /* FIXME: RS400 & RS480 seems to have issue with GART size
  73.                  * if 4G of system memory (needs more testing) */
  74.                 rdev->mc.gtt_size = 32 * 1024 * 1024;
  75.                 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
  76.         }
  77. }
  78.  
  79. void rs400_gart_tlb_flush(struct radeon_device *rdev)
  80. {
  81.         uint32_t tmp;
  82.         unsigned int timeout = rdev->usec_timeout;
  83.  
  84.         WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
  85.         do {
  86.                 tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
  87.                 if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0)
  88.                         break;
  89.                 DRM_UDELAY(1);
  90.                 timeout--;
  91.         } while (timeout > 0);
  92.         WREG32_MC(RS480_GART_CACHE_CNTRL, 0);
  93. }
  94.  
  95. int rs400_gart_init(struct radeon_device *rdev)
  96. {
  97.         int r;
  98.  
  99.         if (rdev->gart.table.ram.ptr) {
  100.                 WARN(1, "RS400 GART already initialized.\n");
  101.                 return 0;
  102.         }
  103.         /* Check gart size */
  104.         switch(rdev->mc.gtt_size / (1024 * 1024)) {
  105.         case 32:
  106.         case 64:
  107.         case 128:
  108.         case 256:
  109.         case 512:
  110.         case 1024:
  111.         case 2048:
  112.                 break;
  113.         default:
  114.                 return -EINVAL;
  115.         }
  116.         /* Initialize common gart structure */
  117.         r = radeon_gart_init(rdev);
  118.         if (r)
  119.                 return r;
  120.         if (rs400_debugfs_pcie_gart_info_init(rdev))
  121.                 DRM_ERROR("Failed to register debugfs file for RS400 GART !\n");
  122.         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
  123.         return radeon_gart_table_ram_alloc(rdev);
  124. }
  125.  
  126. int rs400_gart_enable(struct radeon_device *rdev)
  127. {
  128.         uint32_t size_reg;
  129.         uint32_t tmp;
  130.  
  131.         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
  132.         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
  133.         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
  134.         /* Check gart size */
  135.         switch(rdev->mc.gtt_size / (1024 * 1024)) {
  136.         case 32:
  137.                 size_reg = RS480_VA_SIZE_32MB;
  138.                 break;
  139.         case 64:
  140.                 size_reg = RS480_VA_SIZE_64MB;
  141.                 break;
  142.         case 128:
  143.                 size_reg = RS480_VA_SIZE_128MB;
  144.                 break;
  145.         case 256:
  146.                 size_reg = RS480_VA_SIZE_256MB;
  147.                 break;
  148.         case 512:
  149.                 size_reg = RS480_VA_SIZE_512MB;
  150.                 break;
  151.         case 1024:
  152.                 size_reg = RS480_VA_SIZE_1GB;
  153.                 break;
  154.         case 2048:
  155.                 size_reg = RS480_VA_SIZE_2GB;
  156.                 break;
  157.         default:
  158.                 return -EINVAL;
  159.         }
  160.         /* It should be fine to program it to max value */
  161.         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
  162.                 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF);
  163.                 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0);
  164.         } else {
  165.                 WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);
  166.                 WREG32(RS480_AGP_BASE_2, 0);
  167.         }
  168.         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  169.         tmp = REG_SET(RS690_MC_AGP_TOP, tmp >> 16);
  170.         tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_location >> 16);
  171.         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
  172.                 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp);
  173.                 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
  174.                 WREG32(RADEON_BUS_CNTL, tmp);
  175.         } else {
  176.                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
  177.                 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
  178.                 WREG32(RADEON_BUS_CNTL, tmp);
  179.         }
  180.         /* Table should be in 32bits address space so ignore bits above. */
  181.         tmp = (u32)rdev->gart.table_addr & 0xfffff000;
  182.         tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4;
  183.  
  184.         WREG32_MC(RS480_GART_BASE, tmp);
  185.         /* TODO: more tweaking here */
  186.         WREG32_MC(RS480_GART_FEATURE_ID,
  187.                   (RS480_TLB_ENABLE |
  188.                    RS480_GTW_LAC_EN | RS480_1LEVEL_GART));
  189.         /* Disable snooping */
  190.         WREG32_MC(RS480_AGP_MODE_CNTL,
  191.                   (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS);
  192.         /* Disable AGP mode */
  193.         /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0,
  194.          * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */
  195.         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) {
  196.                 WREG32_MC(RS480_MC_MISC_CNTL,
  197.                           (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN));
  198.         } else {
  199.                 WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
  200.         }
  201.         /* Enable gart */
  202.         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg));
  203.         rs400_gart_tlb_flush(rdev);
  204.         rdev->gart.ready = true;
  205.         return 0;
  206. }
  207.  
  208. void rs400_gart_disable(struct radeon_device *rdev)
  209. {
  210.         uint32_t tmp;
  211.  
  212.         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
  213.         tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
  214.         WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
  215.         WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
  216. }
  217.  
  218. void rs400_gart_fini(struct radeon_device *rdev)
  219. {
  220.         rs400_gart_disable(rdev);
  221.         radeon_gart_table_ram_free(rdev);
  222.         radeon_gart_fini(rdev);
  223. }
  224.  
  225. int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  226. {
  227.         uint32_t entry;
  228.  
  229.         if (i < 0 || i > rdev->gart.num_gpu_pages) {
  230.                 return -EINVAL;
  231.         }
  232.  
  233.         entry = (lower_32_bits(addr) & PAGE_MASK) |
  234.                 ((upper_32_bits(addr) & 0xff) << 4) |
  235.                 0xc;
  236.         entry = cpu_to_le32(entry);
  237.         rdev->gart.table.ram.ptr[i] = entry;
  238.         return 0;
  239. }
  240.  
  241.  
  242. /*
  243.  * MC functions.
  244.  */
  245. int rs400_mc_init(struct radeon_device *rdev)
  246. {
  247.         uint32_t tmp;
  248.         int r;
  249.  
  250.         if (r100_debugfs_rbbm_init(rdev)) {
  251.                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  252.         }
  253.  
  254.         rs400_gpu_init(rdev);
  255.         rs400_gart_disable(rdev);
  256.         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
  257.         rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
  258.         rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
  259.         r = radeon_mc_setup(rdev);
  260.         if (r) {
  261.                 return r;
  262.         }
  263.  
  264.         r100_mc_disable_clients(rdev);
  265.         if (r300_mc_wait_for_idle(rdev)) {
  266.                 printk(KERN_WARNING "Failed to wait MC idle while "
  267.                        "programming pipes. Bad things might happen.\n");
  268.         }
  269.  
  270.         tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
  271.         tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
  272.         tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
  273.         WREG32(RADEON_MC_FB_LOCATION, tmp);
  274.         tmp = RREG32(RADEON_HOST_PATH_CNTL) | RADEON_HP_LIN_RD_CACHE_DIS;
  275.         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
  276.         (void)RREG32(RADEON_HOST_PATH_CNTL);
  277.         WREG32(RADEON_HOST_PATH_CNTL, tmp);
  278.         (void)RREG32(RADEON_HOST_PATH_CNTL);
  279.  
  280.         return 0;
  281. }
  282.  
  283. void rs400_mc_fini(struct radeon_device *rdev)
  284. {
  285. }
  286.  
  287.  
  288. /*
  289.  * Global GPU functions
  290.  */
  291. void rs400_errata(struct radeon_device *rdev)
  292. {
  293.         rdev->pll_errata = 0;
  294. }
  295.  
  296. void rs400_gpu_init(struct radeon_device *rdev)
  297. {
  298.         /* FIXME: HDP same place on rs400 ? */
  299.         r100_hdp_reset(rdev);
  300.         /* FIXME: is this correct ? */
  301.         r420_pipes_init(rdev);
  302.         if (r300_mc_wait_for_idle(rdev)) {
  303.                 printk(KERN_WARNING "Failed to wait MC idle while "
  304.                        "programming pipes. Bad things might happen.\n");
  305.         }
  306. }
  307.  
  308.  
  309. /*
  310.  * VRAM info.
  311.  */
  312. void rs400_vram_info(struct radeon_device *rdev)
  313. {
  314.         rs400_gart_adjust_size(rdev);
  315.         /* DDR for all card after R300 & IGP */
  316.         rdev->mc.vram_is_ddr = true;
  317.         rdev->mc.vram_width = 128;
  318.  
  319.         r100_vram_init_sizes(rdev);
  320. }
  321.  
  322.  
  323. /*
  324.  * Indirect registers accessor
  325.  */
  326. uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg)
  327. {
  328.         uint32_t r;
  329.  
  330.         WREG32(RS480_NB_MC_INDEX, reg & 0xff);
  331.         r = RREG32(RS480_NB_MC_DATA);
  332.         WREG32(RS480_NB_MC_INDEX, 0xff);
  333.         return r;
  334. }
  335.  
  336. void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  337. {
  338.         WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);
  339.         WREG32(RS480_NB_MC_DATA, (v));
  340.         WREG32(RS480_NB_MC_INDEX, 0xff);
  341. }
  342.  
  343.  
  344. /*
  345.  * Debugfs info
  346.  */
  347. #if defined(CONFIG_DEBUG_FS)
  348. static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
  349. {
  350.         struct drm_info_node *node = (struct drm_info_node *) m->private;
  351.         struct drm_device *dev = node->minor->dev;
  352.         struct radeon_device *rdev = dev->dev_private;
  353.         uint32_t tmp;
  354.  
  355.         tmp = RREG32(RADEON_HOST_PATH_CNTL);
  356.         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
  357.         tmp = RREG32(RADEON_BUS_CNTL);
  358.         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
  359.         tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
  360.         seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp);
  361.         if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) {
  362.                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE);
  363.                 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp);
  364.                 tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2);
  365.                 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
  366.                 tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
  367.                 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
  368.                 tmp = RREG32_MC(0x100);
  369.                 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
  370.                 tmp = RREG32(0x134);
  371.                 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
  372.         } else {
  373.                 tmp = RREG32(RADEON_AGP_BASE);
  374.                 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
  375.                 tmp = RREG32(RS480_AGP_BASE_2);
  376.                 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp);
  377.                 tmp = RREG32(RADEON_MC_AGP_LOCATION);
  378.                 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
  379.         }
  380.         tmp = RREG32_MC(RS480_GART_BASE);
  381.         seq_printf(m, "GART_BASE 0x%08x\n", tmp);
  382.         tmp = RREG32_MC(RS480_GART_FEATURE_ID);
  383.         seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp);
  384.         tmp = RREG32_MC(RS480_AGP_MODE_CNTL);
  385.         seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp);
  386.         tmp = RREG32_MC(RS480_MC_MISC_CNTL);
  387.         seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp);
  388.         tmp = RREG32_MC(0x5F);
  389.         seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp);
  390.         tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE);
  391.         seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp);
  392.         tmp = RREG32_MC(RS480_GART_CACHE_CNTRL);
  393.         seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp);
  394.         tmp = RREG32_MC(0x3B);
  395.         seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp);
  396.         tmp = RREG32_MC(0x3C);
  397.         seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp);
  398.         tmp = RREG32_MC(0x30);
  399.         seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp);
  400.         tmp = RREG32_MC(0x31);
  401.         seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp);
  402.         tmp = RREG32_MC(0x32);
  403.         seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp);
  404.         tmp = RREG32_MC(0x33);
  405.         seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp);
  406.         tmp = RREG32_MC(0x34);
  407.         seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp);
  408.         tmp = RREG32_MC(0x35);
  409.         seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp);
  410.         tmp = RREG32_MC(0x36);
  411.         seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp);
  412.         tmp = RREG32_MC(0x37);
  413.         seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp);
  414.         return 0;
  415. }
  416.  
  417. static struct drm_info_list rs400_gart_info_list[] = {
  418.         {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL},
  419. };
  420. #endif
  421.  
  422. int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
  423. {
  424. #if defined(CONFIG_DEBUG_FS)
  425.         return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1);
  426. #else
  427.         return 0;
  428. #endif
  429. }
  430.