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  1.  
  2. #include <linux/list.h>
  3. #include <drm/drmP.h>
  4. #include "radeon_drm.h"
  5. #include "radeon.h"
  6.  
  7.  
  8. static struct drm_mm   mm_gtt;
  9. static struct drm_mm   mm_vram;
  10.  
  11.  
  12. /**
  13.  * Initialize an already allocate GEM object of the specified size with
  14.  * shmfs backing store.
  15.  */
  16. int drm_gem_object_init(struct drm_device *dev,
  17.             struct drm_gem_object *obj, size_t size)
  18. {
  19.     BUG_ON((size & (PAGE_SIZE - 1)) != 0);
  20.  
  21.     obj->dev = dev;
  22.     obj->filp = NULL;
  23.  
  24.     atomic_set(&obj->handle_count, 0);
  25.     obj->size = size;
  26.  
  27.     return 0;
  28. }
  29.  
  30.  
  31. int drm_mm_alloc(struct drm_mm *mm, size_t num_pages,
  32.                  struct drm_mm_node **node)
  33. {
  34.     struct drm_mm_node *vm_node;
  35.     int    r;
  36.  
  37. retry_pre_get:
  38.  
  39.     r = drm_mm_pre_get(mm);
  40.  
  41.     if (unlikely(r != 0))
  42.        return r;
  43.  
  44.     vm_node = drm_mm_search_free(mm, num_pages, 0, 0);
  45.  
  46.     if (unlikely(vm_node == NULL)) {
  47.         r = -ENOMEM;
  48.         return r;
  49.     }
  50.  
  51.     *node =  drm_mm_get_block_atomic(vm_node, num_pages, 0);
  52.  
  53.     if (unlikely(*node == NULL)) {
  54.             goto retry_pre_get;
  55.     }
  56.  
  57.     return 0;
  58. };
  59.  
  60.  
  61.  
  62. void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  63. {
  64.     u32 c = 0;
  65.  
  66.     rbo->placement.fpfn = 0;
  67.     rbo->placement.lpfn = 0;
  68.     rbo->placement.placement = rbo->placements;
  69.     rbo->placement.busy_placement = rbo->placements;
  70.     if (domain & RADEON_GEM_DOMAIN_VRAM)
  71.         rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  72.                     TTM_PL_FLAG_VRAM;
  73.     if (domain & RADEON_GEM_DOMAIN_GTT)
  74.         rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  75.     if (domain & RADEON_GEM_DOMAIN_CPU)
  76.         rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  77.     if (!c)
  78.         rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  79.     rbo->placement.num_placement = c;
  80.     rbo->placement.num_busy_placement = c;
  81. }
  82.  
  83.  
  84. int radeon_bo_init(struct radeon_device *rdev)
  85. {
  86.     int r;
  87.  
  88.     DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
  89.         rdev->mc.mc_vram_size >> 20,
  90.         (unsigned long long)rdev->mc.aper_size >> 20);
  91.     DRM_INFO("RAM width %dbits %cDR\n",
  92.             rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
  93.  
  94.     r = drm_mm_init(&mm_vram, 0xC00000 >> PAGE_SHIFT,
  95.                ((rdev->mc.real_vram_size - 0xC00000) >> PAGE_SHIFT));
  96.     if (r) {
  97.         DRM_ERROR("Failed initializing VRAM heap.\n");
  98.         return r;
  99.     };
  100.  
  101.     r = drm_mm_init(&mm_gtt, 0, rdev->mc.gtt_size >> PAGE_SHIFT);
  102.     if (r) {
  103.         DRM_ERROR("Failed initializing GTT heap.\n");
  104.         return r;
  105.     }
  106.  
  107.     return 0;
  108. }
  109.  
  110.  
  111. int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
  112. {
  113.     int r;
  114.  
  115.     bo->tbo.reserved.counter = 1;
  116.  
  117.     return 0;
  118. }
  119.  
  120. void ttm_bo_unreserve(struct ttm_buffer_object *bo)
  121. {
  122.     bo->reserved.counter = 1;
  123. }
  124.  
  125. int radeon_bo_create(struct radeon_device *rdev,
  126.                      unsigned long size, int byte_align, bool kernel, u32 domain,
  127.                 struct radeon_bo **bo_ptr)
  128. {
  129.         struct radeon_bo *bo;
  130.     enum ttm_bo_type type;
  131.  
  132.     size_t num_pages;
  133.     struct drm_mm      *mman;
  134.     u32                 bo_domain;
  135.     int r;
  136.  
  137.     num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
  138.  
  139.     if (num_pages == 0) {
  140.         dbgprintf("Illegal buffer object size.\n");
  141.         return -EINVAL;
  142.     }
  143.  
  144.     if(domain & RADEON_GEM_DOMAIN_VRAM)
  145.     {
  146.         mman = &mm_vram;
  147.         bo_domain = RADEON_GEM_DOMAIN_VRAM;
  148.     }
  149.     else if(domain & RADEON_GEM_DOMAIN_GTT)
  150.     {
  151.         mman = &mm_gtt;
  152.         bo_domain = RADEON_GEM_DOMAIN_GTT;
  153.     }
  154.     else return -EINVAL;
  155.  
  156.     if (kernel) {
  157.         type = ttm_bo_type_kernel;
  158.     } else {
  159.         type = ttm_bo_type_device;
  160.     }
  161.     *bo_ptr = NULL;
  162.     bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
  163.     if (bo == NULL)
  164.         return -ENOMEM;
  165.  
  166.         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
  167.     if (unlikely(r)) {
  168.                 kfree(bo);
  169.                 return r;
  170.         }
  171.     bo->rdev = rdev;
  172.         bo->gem_base.driver_private = NULL;
  173.     bo->surface_reg = -1;
  174.     bo->tbo.num_pages = num_pages;
  175.     bo->domain = domain;
  176.  
  177.     INIT_LIST_HEAD(&bo->list);
  178.  
  179. //    radeon_ttm_placement_from_domain(bo, domain);
  180.     /* Kernel allocation are uninterruptible */
  181.  
  182.     r = drm_mm_alloc(mman, num_pages, &bo->tbo.vm_node);
  183.     if (unlikely(r != 0))
  184.         return r;
  185.  
  186.     *bo_ptr = bo;
  187.  
  188.     return 0;
  189. }
  190.  
  191. #define page_tabs  0xFDC00000      /* just another hack */
  192.  
  193. int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
  194. {
  195.     int r=0, i;
  196.  
  197.     if (bo->pin_count) {
  198.         bo->pin_count++;
  199.         if (gpu_addr)
  200.             *gpu_addr = radeon_bo_gpu_offset(bo);
  201.         return 0;
  202.     }
  203.  
  204.     bo->tbo.offset = bo->tbo.vm_node->start << PAGE_SHIFT;
  205.  
  206.     if(bo->domain & RADEON_GEM_DOMAIN_VRAM)
  207.     {
  208.         bo->tbo.offset += (u64)bo->rdev->mc.vram_start;
  209.     }
  210.     else if (bo->domain & RADEON_GEM_DOMAIN_GTT)
  211.     {
  212.         u32_t *pagelist;
  213.         bo->kptr  = KernelAlloc( bo->tbo.num_pages << PAGE_SHIFT );
  214.         dbgprintf("kernel alloc %x\n", bo->kptr );
  215.  
  216.         pagelist =  &((u32_t*)page_tabs)[(u32_t)bo->kptr >> 12];
  217.         dbgprintf("pagelist %x\n", pagelist);
  218.         radeon_gart_bind(bo->rdev, bo->tbo.offset,
  219.                          bo->tbo.vm_node->size,  pagelist);
  220.         bo->tbo.offset += (u64)bo->rdev->mc.gtt_start;
  221.     }
  222.     else
  223.     {
  224.         DRM_ERROR("Unknown placement %x\n", bo->domain);
  225.         bo->tbo.offset = -1;
  226.         r = -1;
  227.     };
  228.  
  229.     if (unlikely(r != 0)) {
  230.         DRM_ERROR("radeon: failed to pin object.\n");
  231.     }
  232.  
  233.     if (likely(r == 0)) {
  234.         bo->pin_count = 1;
  235.         if (gpu_addr != NULL)
  236.             *gpu_addr = radeon_bo_gpu_offset(bo);
  237.     }
  238.  
  239.     if (unlikely(r != 0))
  240.         dev_err(bo->rdev->dev, "%p pin failed\n", bo);
  241.     return r;
  242. };
  243.  
  244. int radeon_bo_unpin(struct radeon_bo *bo)
  245. {
  246.     int r = 0;
  247.  
  248.     if (!bo->pin_count) {
  249.         dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
  250.         return 0;
  251.     }
  252.     bo->pin_count--;
  253.     if (bo->pin_count)
  254.         return 0;
  255.  
  256.     if( bo->tbo.vm_node )
  257.     {
  258.         drm_mm_put_block(bo->tbo.vm_node);
  259.         bo->tbo.vm_node = NULL;
  260.     };
  261.  
  262.     return r;
  263. }
  264.  
  265. int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
  266. {
  267.     bool is_iomem;
  268.  
  269.     if (bo->kptr) {
  270.         if (ptr) {
  271.             *ptr = bo->kptr;
  272.         }
  273.         return 0;
  274.     }
  275.  
  276.     if(bo->domain & RADEON_GEM_DOMAIN_VRAM)
  277.     {
  278.         bo->cpu_addr = bo->rdev->mc.aper_base +
  279.                        (bo->tbo.vm_node->start << PAGE_SHIFT);
  280.         bo->kptr = (void*)MapIoMem(bo->cpu_addr,
  281.                         bo->tbo.vm_node->size << 12, PG_SW);
  282.     }
  283.     else
  284.     {
  285.         return -1;
  286.     }
  287.  
  288.     if (ptr) {
  289.         *ptr = bo->kptr;
  290.     }
  291.  
  292.     return 0;
  293. }
  294.  
  295. void radeon_bo_kunmap(struct radeon_bo *bo)
  296. {
  297.     if (bo->kptr == NULL)
  298.         return;
  299.  
  300.     if (bo->domain & RADEON_GEM_DOMAIN_VRAM)
  301.     {
  302.         FreeKernelSpace(bo->kptr);
  303.     }
  304.  
  305.     bo->kptr = NULL;
  306.  
  307. }
  308.  
  309. void radeon_bo_unref(struct radeon_bo **bo)
  310. {
  311.     struct ttm_buffer_object *tbo;
  312.  
  313.     if ((*bo) == NULL)
  314.         return;
  315.  
  316.     *bo = NULL;
  317. }
  318.  
  319.  
  320. void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
  321.                 uint32_t *tiling_flags,
  322.                 uint32_t *pitch)
  323. {
  324. //    BUG_ON(!atomic_read(&bo->tbo.reserved));
  325.     if (tiling_flags)
  326.         *tiling_flags = bo->tiling_flags;
  327.     if (pitch)
  328.         *pitch = bo->pitch;
  329. }
  330.  
  331.  
  332. /**
  333.  * Allocate a GEM object of the specified size with shmfs backing store
  334.  */
  335. struct drm_gem_object *
  336. drm_gem_object_alloc(struct drm_device *dev, size_t size)
  337. {
  338.     struct drm_gem_object *obj;
  339.  
  340.     BUG_ON((size & (PAGE_SIZE - 1)) != 0);
  341.  
  342.     obj = kzalloc(sizeof(*obj), GFP_KERNEL);
  343.  
  344.     obj->dev = dev;
  345.     obj->size = size;
  346.     return obj;
  347. }
  348.  
  349.  
  350. int radeon_fb_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
  351.             unsigned long size, bool kernel, u32 domain,
  352.             struct radeon_bo **bo_ptr)
  353. {
  354.     enum ttm_bo_type    type;
  355.  
  356.     struct radeon_bo    *bo;
  357.     struct drm_mm       *mman;
  358.     struct drm_mm_node  *vm_node;
  359.  
  360.     size_t  num_pages;
  361.     u32     bo_domain;
  362.     int     r;
  363.  
  364.     num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
  365.  
  366.     if (num_pages == 0) {
  367.         dbgprintf("Illegal buffer object size.\n");
  368.         return -EINVAL;
  369.     }
  370.  
  371.     if( (domain & RADEON_GEM_DOMAIN_VRAM) !=
  372.         RADEON_GEM_DOMAIN_VRAM )
  373.     {
  374.         return -EINVAL;
  375.     };
  376.  
  377.     if (kernel) {
  378.         type = ttm_bo_type_kernel;
  379.     } else {
  380.         type = ttm_bo_type_device;
  381.     }
  382.     *bo_ptr = NULL;
  383.     bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
  384.     if (bo == NULL)
  385.         return -ENOMEM;
  386.  
  387.     bo->rdev = rdev;
  388. //    bo->gobj = gobj;
  389.     bo->surface_reg = -1;
  390.     bo->tbo.num_pages = num_pages;
  391.     bo->domain = domain;
  392.  
  393.     INIT_LIST_HEAD(&bo->list);
  394.  
  395. //    radeon_ttm_placement_from_domain(bo, domain);
  396.     /* Kernel allocation are uninterruptible */
  397.  
  398.     vm_node = kzalloc(sizeof(*vm_node),0);
  399.  
  400.     vm_node->size = 0xC00000 >> 12;
  401.     vm_node->start = 0;
  402.     vm_node->mm = NULL;
  403.  
  404.     bo->tbo.vm_node = vm_node;
  405.     bo->tbo.offset  = bo->tbo.vm_node->start << PAGE_SHIFT;
  406.     bo->tbo.offset += (u64)bo->rdev->mc.vram_start;
  407.     bo->kptr        = (void*)0xFE000000;
  408.     bo->pin_count   = 1;
  409.  
  410.     *bo_ptr = bo;
  411.  
  412.     return 0;
  413. }
  414.