Subversion Repositories Kolibri OS

Rev

Rev 1430 | Rev 3120 | Go to most recent revision | Blame | Compare with Previous | Last modification | View Log | Download | RSS feed

  1. /*
  2.  * Copyright 2007-8 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the "Software"),
  7.  * to deal in the Software without restriction, including without limitation
  8.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9.  * and/or sell copies of the Software, and to permit persons to whom the
  10.  * Software is furnished to do so, subject to the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice shall be included in
  13.  * all copies or substantial portions of the Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21.  * OTHER DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors: Dave Airlie
  24.  *          Alex Deucher
  25.  */
  26. #include "drmP.h"
  27. #include "drm_crtc_helper.h"
  28. #include "radeon_drm.h"
  29. #include "radeon.h"
  30. #include "atom.h"
  31.  
  32. static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  33. {
  34.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  35.         struct drm_encoder_helper_funcs *encoder_funcs;
  36.  
  37.         encoder_funcs = encoder->helper_private;
  38.         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  39.         radeon_encoder->active_device = 0;
  40. }
  41.  
  42. static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
  43. {
  44.         struct drm_device *dev = encoder->dev;
  45.         struct radeon_device *rdev = dev->dev_private;
  46.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  47.         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  48.         int panel_pwr_delay = 2000;
  49.         bool is_mac = false;
  50.         uint8_t backlight_level;
  51.         DRM_DEBUG_KMS("\n");
  52.  
  53.         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  54.         backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
  55.  
  56.         if (radeon_encoder->enc_priv) {
  57.                 if (rdev->is_atom_bios) {
  58.                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  59.                         panel_pwr_delay = lvds->panel_pwr_delay;
  60.                         if (lvds->bl_dev)
  61.                                 backlight_level = lvds->backlight_level;
  62.                 } else {
  63.                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  64.                         panel_pwr_delay = lvds->panel_pwr_delay;
  65.                         if (lvds->bl_dev)
  66.                                 backlight_level = lvds->backlight_level;
  67.                 }
  68.         }
  69.  
  70.         /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
  71.          * Taken from radeonfb.
  72.          */
  73.         if ((rdev->mode_info.connector_table == CT_IBOOK) ||
  74.             (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
  75.             (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
  76.             (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
  77.                 is_mac = true;
  78.  
  79.         switch (mode) {
  80.         case DRM_MODE_DPMS_ON:
  81.                 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  82.                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  83.                 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  84.                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  85.                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  86.                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  87.                 udelay(1000);
  88.  
  89.                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  90.                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  91.                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  92.  
  93.                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
  94.                                    RADEON_LVDS_BL_MOD_LEVEL_MASK);
  95.                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
  96.                                   RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
  97.                                   (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
  98.                 if (is_mac)
  99.                         lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
  100.                 udelay(panel_pwr_delay * 1000);
  101.                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  102.                 break;
  103.         case DRM_MODE_DPMS_STANDBY:
  104.         case DRM_MODE_DPMS_SUSPEND:
  105.         case DRM_MODE_DPMS_OFF:
  106.                 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  107.                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
  108.                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  109.                 if (is_mac) {
  110.                         lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
  111.                         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  112.                         lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
  113.                 } else {
  114.                         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  115.                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
  116.                 }
  117.                 udelay(panel_pwr_delay * 1000);
  118.                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  119.                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  120.                 udelay(panel_pwr_delay * 1000);
  121.                 break;
  122.         }
  123.  
  124.         if (rdev->is_atom_bios)
  125.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  126.         else
  127.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  128.  
  129. }
  130.  
  131. static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
  132. {
  133.         struct radeon_device *rdev = encoder->dev->dev_private;
  134.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  135.         DRM_DEBUG("\n");
  136.  
  137.         if (radeon_encoder->enc_priv) {
  138.                 if (rdev->is_atom_bios) {
  139.                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  140.                         lvds->dpms_mode = mode;
  141.                 } else {
  142.                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  143.                         lvds->dpms_mode = mode;
  144.                 }
  145.         }
  146.  
  147.         radeon_legacy_lvds_update(encoder, mode);
  148. }
  149.  
  150. static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
  151. {
  152.         struct radeon_device *rdev = encoder->dev->dev_private;
  153.  
  154.         if (rdev->is_atom_bios)
  155.                 radeon_atom_output_lock(encoder, true);
  156.         else
  157.                 radeon_combios_output_lock(encoder, true);
  158.         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
  159. }
  160.  
  161. static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
  162. {
  163.         struct radeon_device *rdev = encoder->dev->dev_private;
  164.  
  165.         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
  166.         if (rdev->is_atom_bios)
  167.                 radeon_atom_output_lock(encoder, false);
  168.         else
  169.                 radeon_combios_output_lock(encoder, false);
  170. }
  171.  
  172. static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
  173.                                         struct drm_display_mode *mode,
  174.                                         struct drm_display_mode *adjusted_mode)
  175. {
  176.         struct drm_device *dev = encoder->dev;
  177.         struct radeon_device *rdev = dev->dev_private;
  178.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  179.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  180.         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
  181.  
  182.         DRM_DEBUG_KMS("\n");
  183.  
  184.         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  185.         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
  186.  
  187.         lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
  188.         if (rdev->is_atom_bios) {
  189.                 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
  190.                  * need to call that on resume to set up the reg properly.
  191.                  */
  192.                 radeon_encoder->pixel_clock = adjusted_mode->clock;
  193.                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
  194.                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  195.         } else {
  196.                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
  197.                 if (lvds) {
  198.                         DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
  199.                         lvds_gen_cntl = lvds->lvds_gen_cntl;
  200.                         lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
  201.                                               (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
  202.                         lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
  203.                                              (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
  204.                 } else
  205.                         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  206.         }
  207.         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  208.         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
  209.                            RADEON_LVDS_BLON |
  210.                            RADEON_LVDS_EN |
  211.                            RADEON_LVDS_RST_FM);
  212.  
  213.         if (ASIC_IS_R300(rdev))
  214.                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
  215.  
  216.         if (radeon_crtc->crtc_id == 0) {
  217.                 if (ASIC_IS_R300(rdev)) {
  218.                         if (radeon_encoder->rmx_type != RMX_OFF)
  219.                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
  220.                 } else
  221.                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
  222.         } else {
  223.                 if (ASIC_IS_R300(rdev))
  224.                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
  225.                 else
  226.                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
  227.         }
  228.  
  229.         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  230.         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  231.         WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
  232.  
  233.         if (rdev->family == CHIP_RV410)
  234.                 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
  235.  
  236.         if (rdev->is_atom_bios)
  237.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  238.         else
  239.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  240. }
  241.  
  242. static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
  243.                                           struct drm_display_mode *mode,
  244.                                           struct drm_display_mode *adjusted_mode)
  245. {
  246.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  247.  
  248.         /* set the active encoder to connector routing */
  249.         radeon_encoder_set_active_device(encoder);
  250.         drm_mode_set_crtcinfo(adjusted_mode, 0);
  251.  
  252.         /* get the native mode for LVDS */
  253.         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
  254.                 radeon_panel_mode_fixup(encoder, adjusted_mode);
  255.  
  256.         return true;
  257. }
  258.  
  259. static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
  260.         .dpms = radeon_legacy_lvds_dpms,
  261.         .mode_fixup = radeon_legacy_mode_fixup,
  262.         .prepare = radeon_legacy_lvds_prepare,
  263.         .mode_set = radeon_legacy_lvds_mode_set,
  264.         .commit = radeon_legacy_lvds_commit,
  265.         .disable = radeon_legacy_encoder_disable,
  266. };
  267.  
  268. #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
  269.  
  270. #define MAX_RADEON_LEVEL 0xFF
  271.  
  272. struct radeon_backlight_privdata {
  273.         struct radeon_encoder *encoder;
  274.         uint8_t negative;
  275. };
  276.  
  277. static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
  278. {
  279.         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
  280.         uint8_t level;
  281.  
  282.         /* Convert brightness to hardware level */
  283.         if (bd->props.brightness < 0)
  284.                 level = 0;
  285.         else if (bd->props.brightness > MAX_RADEON_LEVEL)
  286.                 level = MAX_RADEON_LEVEL;
  287.         else
  288.                 level = bd->props.brightness;
  289.  
  290.         if (pdata->negative)
  291.                 level = MAX_RADEON_LEVEL - level;
  292.  
  293.         return level;
  294. }
  295.  
  296. static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
  297. {
  298.         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
  299.         struct radeon_encoder *radeon_encoder = pdata->encoder;
  300.         struct drm_device *dev = radeon_encoder->base.dev;
  301.         struct radeon_device *rdev = dev->dev_private;
  302.         int dpms_mode = DRM_MODE_DPMS_ON;
  303.  
  304.         if (radeon_encoder->enc_priv) {
  305.                 if (rdev->is_atom_bios) {
  306.                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  307.                         dpms_mode = lvds->dpms_mode;
  308.                         lvds->backlight_level = radeon_legacy_lvds_level(bd);
  309.                 } else {
  310.                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  311.                         dpms_mode = lvds->dpms_mode;
  312.                         lvds->backlight_level = radeon_legacy_lvds_level(bd);
  313.                 }
  314.         }
  315.  
  316.         if (bd->props.brightness > 0)
  317.                 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
  318.         else
  319.                 radeon_legacy_lvds_update(&radeon_encoder->base, DRM_MODE_DPMS_OFF);
  320.  
  321.         return 0;
  322. }
  323.  
  324. static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
  325. {
  326.         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
  327.         struct radeon_encoder *radeon_encoder = pdata->encoder;
  328.         struct drm_device *dev = radeon_encoder->base.dev;
  329.         struct radeon_device *rdev = dev->dev_private;
  330.         uint8_t backlight_level;
  331.  
  332.         backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
  333.                            RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
  334.  
  335.         return pdata->negative ? MAX_RADEON_LEVEL - backlight_level : backlight_level;
  336. }
  337.  
  338. static const struct backlight_ops radeon_backlight_ops = {
  339.         .get_brightness = radeon_legacy_backlight_get_brightness,
  340.         .update_status  = radeon_legacy_backlight_update_status,
  341. };
  342.  
  343. void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
  344.                                   struct drm_connector *drm_connector)
  345. {
  346.         struct drm_device *dev = radeon_encoder->base.dev;
  347.         struct radeon_device *rdev = dev->dev_private;
  348.         struct backlight_device *bd;
  349.         struct backlight_properties props;
  350.         struct radeon_backlight_privdata *pdata;
  351.         uint8_t backlight_level;
  352.  
  353.         if (!radeon_encoder->enc_priv)
  354.                 return;
  355.  
  356. #ifdef CONFIG_PMAC_BACKLIGHT
  357.         if (!pmac_has_backlight_type("ati") &&
  358.             !pmac_has_backlight_type("mnca"))
  359.                 return;
  360. #endif
  361.  
  362.         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
  363.         if (!pdata) {
  364.                 DRM_ERROR("Memory allocation failed\n");
  365.                 goto error;
  366.         }
  367.  
  368.         props.max_brightness = MAX_RADEON_LEVEL;
  369.         props.type = BACKLIGHT_RAW;
  370.         bd = backlight_device_register("radeon_bl", &drm_connector->kdev,
  371.                                        pdata, &radeon_backlight_ops, &props);
  372.         if (IS_ERR(bd)) {
  373.                 DRM_ERROR("Backlight registration failed\n");
  374.                 goto error;
  375.         }
  376.  
  377.         pdata->encoder = radeon_encoder;
  378.  
  379.         backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
  380.                            RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
  381.  
  382.         /* First, try to detect backlight level sense based on the assumption
  383.          * that firmware set it up at full brightness
  384.          */
  385.         if (backlight_level == 0)
  386.                 pdata->negative = true;
  387.         else if (backlight_level == 0xff)
  388.                 pdata->negative = false;
  389.         else {
  390.                 /* XXX hack... maybe some day we can figure out in what direction
  391.                  * backlight should work on a given panel?
  392.                  */
  393.                 pdata->negative = (rdev->family != CHIP_RV200 &&
  394.                                    rdev->family != CHIP_RV250 &&
  395.                                    rdev->family != CHIP_RV280 &&
  396.                                    rdev->family != CHIP_RV350);
  397.  
  398. #ifdef CONFIG_PMAC_BACKLIGHT
  399.                 pdata->negative = (pdata->negative ||
  400.                                    of_machine_is_compatible("PowerBook4,3") ||
  401.                                    of_machine_is_compatible("PowerBook6,3") ||
  402.                                    of_machine_is_compatible("PowerBook6,5"));
  403. #endif
  404.         }
  405.  
  406.         if (rdev->is_atom_bios) {
  407.                 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  408.                 lvds->bl_dev = bd;
  409.         } else {
  410.                 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  411.                 lvds->bl_dev = bd;
  412.         }
  413.  
  414.         bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
  415.         bd->props.power = FB_BLANK_UNBLANK;
  416.         backlight_update_status(bd);
  417.  
  418.         DRM_INFO("radeon legacy LVDS backlight initialized\n");
  419.  
  420.         return;
  421.  
  422. error:
  423.         kfree(pdata);
  424.         return;
  425. }
  426.  
  427. static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
  428. {
  429.         struct drm_device *dev = radeon_encoder->base.dev;
  430.         struct radeon_device *rdev = dev->dev_private;
  431.         struct backlight_device *bd = NULL;
  432.  
  433.         if (!radeon_encoder->enc_priv)
  434.                 return;
  435.  
  436.         if (rdev->is_atom_bios) {
  437.                 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  438.                 bd = lvds->bl_dev;
  439.                 lvds->bl_dev = NULL;
  440.         } else {
  441.                 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  442.                 bd = lvds->bl_dev;
  443.                 lvds->bl_dev = NULL;
  444.         }
  445.  
  446.         if (bd) {
  447.                 struct radeon_legacy_backlight_privdata *pdata;
  448.  
  449.                 pdata = bl_get_data(bd);
  450.                 backlight_device_unregister(bd);
  451.                 kfree(pdata);
  452.  
  453.                 DRM_INFO("radeon legacy LVDS backlight unloaded\n");
  454.         }
  455. }
  456.  
  457. #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
  458.  
  459. void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
  460. {
  461. }
  462.  
  463. static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
  464. {
  465. }
  466.  
  467. #endif
  468.  
  469.  
  470. static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
  471. {
  472.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  473.  
  474.         if (radeon_encoder->enc_priv) {
  475.                 radeon_legacy_backlight_exit(radeon_encoder);
  476.                 kfree(radeon_encoder->enc_priv);
  477.         }
  478.         drm_encoder_cleanup(encoder);
  479.         kfree(radeon_encoder);
  480. }
  481.  
  482. static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
  483.         .destroy = radeon_lvds_enc_destroy,
  484. };
  485.  
  486. static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
  487. {
  488.         struct drm_device *dev = encoder->dev;
  489.         struct radeon_device *rdev = dev->dev_private;
  490.         uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  491.         uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
  492.         uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  493.  
  494.         DRM_DEBUG_KMS("\n");
  495.  
  496.         switch (mode) {
  497.         case DRM_MODE_DPMS_ON:
  498.                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
  499.                 dac_cntl &= ~RADEON_DAC_PDWN;
  500.                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
  501.                                     RADEON_DAC_PDWN_G |
  502.                                     RADEON_DAC_PDWN_B);
  503.                 break;
  504.         case DRM_MODE_DPMS_STANDBY:
  505.         case DRM_MODE_DPMS_SUSPEND:
  506.         case DRM_MODE_DPMS_OFF:
  507.                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
  508.                 dac_cntl |= RADEON_DAC_PDWN;
  509.                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
  510.                                    RADEON_DAC_PDWN_G |
  511.                                    RADEON_DAC_PDWN_B);
  512.                 break;
  513.         }
  514.  
  515.         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  516.         WREG32(RADEON_DAC_CNTL, dac_cntl);
  517.         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  518.  
  519.         if (rdev->is_atom_bios)
  520.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  521.         else
  522.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  523.  
  524. }
  525.  
  526. static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
  527. {
  528.         struct radeon_device *rdev = encoder->dev->dev_private;
  529.  
  530.         if (rdev->is_atom_bios)
  531.                 radeon_atom_output_lock(encoder, true);
  532.         else
  533.                 radeon_combios_output_lock(encoder, true);
  534.         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
  535. }
  536.  
  537. static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
  538. {
  539.         struct radeon_device *rdev = encoder->dev->dev_private;
  540.  
  541.         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
  542.  
  543.         if (rdev->is_atom_bios)
  544.                 radeon_atom_output_lock(encoder, false);
  545.         else
  546.                 radeon_combios_output_lock(encoder, false);
  547. }
  548.  
  549. static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
  550.                                                struct drm_display_mode *mode,
  551.                                                struct drm_display_mode *adjusted_mode)
  552. {
  553.         struct drm_device *dev = encoder->dev;
  554.         struct radeon_device *rdev = dev->dev_private;
  555.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  556.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  557.         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
  558.  
  559.         DRM_DEBUG_KMS("\n");
  560.  
  561.         if (radeon_crtc->crtc_id == 0) {
  562.                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
  563.                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
  564.                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
  565.                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  566.                 } else {
  567.                         dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
  568.                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  569.                 }
  570.         } else {
  571.                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
  572.                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
  573.                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
  574.                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
  575.                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  576.                 } else {
  577.                         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
  578.                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  579.                 }
  580.         }
  581.  
  582.         dac_cntl = (RADEON_DAC_MASK_ALL |
  583.                     RADEON_DAC_VGA_ADR_EN |
  584.                     /* TODO 6-bits */
  585.                     RADEON_DAC_8BIT_EN);
  586.  
  587.         WREG32_P(RADEON_DAC_CNTL,
  588.                        dac_cntl,
  589.                        RADEON_DAC_RANGE_CNTL |
  590.                        RADEON_DAC_BLANKING);
  591.  
  592.         if (radeon_encoder->enc_priv) {
  593.                 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
  594.                 dac_macro_cntl = p_dac->ps2_pdac_adj;
  595.         } else
  596.                 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  597.         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
  598.         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  599.  
  600.         if (rdev->is_atom_bios)
  601.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  602.         else
  603.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  604. }
  605.  
  606. static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
  607.                                                                   struct drm_connector *connector)
  608. {
  609.         struct drm_device *dev = encoder->dev;
  610.         struct radeon_device *rdev = dev->dev_private;
  611.         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
  612.         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
  613.         enum drm_connector_status found = connector_status_disconnected;
  614.         bool color = true;
  615.  
  616.         /* save the regs we need */
  617.         vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
  618.         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  619.         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  620.         dac_cntl = RREG32(RADEON_DAC_CNTL);
  621.         dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  622.  
  623.         tmp = vclk_ecp_cntl &
  624.                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
  625.         WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
  626.  
  627.         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
  628.         WREG32(RADEON_CRTC_EXT_CNTL, tmp);
  629.  
  630.         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
  631.                 RADEON_DAC_FORCE_DATA_EN;
  632.  
  633.         if (color)
  634.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
  635.         else
  636.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
  637.  
  638.         if (ASIC_IS_R300(rdev))
  639.                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
  640.         else
  641.                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
  642.  
  643.         WREG32(RADEON_DAC_EXT_CNTL, tmp);
  644.  
  645.         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
  646.         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
  647.         WREG32(RADEON_DAC_CNTL, tmp);
  648.  
  649.         tmp &= ~(RADEON_DAC_PDWN_R |
  650.                  RADEON_DAC_PDWN_G |
  651.                  RADEON_DAC_PDWN_B);
  652.  
  653.         WREG32(RADEON_DAC_MACRO_CNTL, tmp);
  654.  
  655.         udelay(2000);
  656.  
  657.         if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
  658.                 found = connector_status_connected;
  659.  
  660.         /* restore the regs we used */
  661.         WREG32(RADEON_DAC_CNTL, dac_cntl);
  662.         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  663.         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  664.         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  665.         WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
  666.  
  667.         return found;
  668. }
  669.  
  670. static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
  671.         .dpms = radeon_legacy_primary_dac_dpms,
  672.         .mode_fixup = radeon_legacy_mode_fixup,
  673.         .prepare = radeon_legacy_primary_dac_prepare,
  674.         .mode_set = radeon_legacy_primary_dac_mode_set,
  675.         .commit = radeon_legacy_primary_dac_commit,
  676.         .detect = radeon_legacy_primary_dac_detect,
  677.         .disable = radeon_legacy_encoder_disable,
  678. };
  679.  
  680.  
  681. static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
  682.         .destroy = radeon_enc_destroy,
  683. };
  684.  
  685. static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
  686. {
  687.         struct drm_device *dev = encoder->dev;
  688.         struct radeon_device *rdev = dev->dev_private;
  689.         uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
  690.         DRM_DEBUG_KMS("\n");
  691.  
  692.         switch (mode) {
  693.         case DRM_MODE_DPMS_ON:
  694.                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  695.                 break;
  696.         case DRM_MODE_DPMS_STANDBY:
  697.         case DRM_MODE_DPMS_SUSPEND:
  698.         case DRM_MODE_DPMS_OFF:
  699.                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  700.                 break;
  701.         }
  702.  
  703.         WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
  704.  
  705.         if (rdev->is_atom_bios)
  706.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  707.         else
  708.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  709.  
  710. }
  711.  
  712. static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
  713. {
  714.         struct radeon_device *rdev = encoder->dev->dev_private;
  715.  
  716.         if (rdev->is_atom_bios)
  717.                 radeon_atom_output_lock(encoder, true);
  718.         else
  719.                 radeon_combios_output_lock(encoder, true);
  720.         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
  721. }
  722.  
  723. static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
  724. {
  725.         struct radeon_device *rdev = encoder->dev->dev_private;
  726.  
  727.         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
  728.  
  729.         if (rdev->is_atom_bios)
  730.                 radeon_atom_output_lock(encoder, true);
  731.         else
  732.                 radeon_combios_output_lock(encoder, true);
  733. }
  734.  
  735. static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
  736.                                             struct drm_display_mode *mode,
  737.                                             struct drm_display_mode *adjusted_mode)
  738. {
  739.         struct drm_device *dev = encoder->dev;
  740.         struct radeon_device *rdev = dev->dev_private;
  741.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  742.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  743.         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
  744.         int i;
  745.  
  746.         DRM_DEBUG_KMS("\n");
  747.  
  748.         tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
  749.         tmp &= 0xfffff;
  750.         if (rdev->family == CHIP_RV280) {
  751.                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
  752.                 tmp ^= (1 << 22);
  753.                 tmds_pll_cntl ^= (1 << 22);
  754.         }
  755.  
  756.         if (radeon_encoder->enc_priv) {
  757.                 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
  758.  
  759.                 for (i = 0; i < 4; i++) {
  760.                         if (tmds->tmds_pll[i].freq == 0)
  761.                                 break;
  762.                         if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
  763.                                 tmp = tmds->tmds_pll[i].value ;
  764.                                 break;
  765.                         }
  766.                 }
  767.         }
  768.  
  769.         if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
  770.                 if (tmp & 0xfff00000)
  771.                         tmds_pll_cntl = tmp;
  772.                 else {
  773.                         tmds_pll_cntl &= 0xfff00000;
  774.                         tmds_pll_cntl |= tmp;
  775.                 }
  776.         } else
  777.                 tmds_pll_cntl = tmp;
  778.  
  779.         tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
  780.                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
  781.  
  782.     if (rdev->family == CHIP_R200 ||
  783.         rdev->family == CHIP_R100 ||
  784.         ASIC_IS_R300(rdev))
  785.             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
  786.     else /* RV chips got this bit reversed */
  787.             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
  788.  
  789.     fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
  790.                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
  791.                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
  792.  
  793.     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  794.  
  795.     fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
  796.                      RADEON_FP_DFP_SYNC_SEL |
  797.                      RADEON_FP_CRT_SYNC_SEL |
  798.                      RADEON_FP_CRTC_LOCK_8DOT |
  799.                      RADEON_FP_USE_SHADOW_EN |
  800.                      RADEON_FP_CRTC_USE_SHADOW_VEND |
  801.                      RADEON_FP_CRT_SYNC_ALT);
  802.  
  803.     if (1) /*  FIXME rgbBits == 8 */
  804.             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
  805.     else
  806.             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
  807.  
  808.     if (radeon_crtc->crtc_id == 0) {
  809.             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
  810.                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
  811.                     if (radeon_encoder->rmx_type != RMX_OFF)
  812.                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
  813.                     else
  814.                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
  815.             } else
  816.                     fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
  817.     } else {
  818.             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
  819.                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
  820.                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
  821.             } else
  822.                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
  823.     }
  824.  
  825.     WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
  826.     WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
  827.     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
  828.  
  829.         if (rdev->is_atom_bios)
  830.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  831.         else
  832.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  833. }
  834.  
  835. static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
  836.         .dpms = radeon_legacy_tmds_int_dpms,
  837.         .mode_fixup = radeon_legacy_mode_fixup,
  838.         .prepare = radeon_legacy_tmds_int_prepare,
  839.         .mode_set = radeon_legacy_tmds_int_mode_set,
  840.         .commit = radeon_legacy_tmds_int_commit,
  841.         .disable = radeon_legacy_encoder_disable,
  842. };
  843.  
  844.  
  845. static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
  846.         .destroy = radeon_enc_destroy,
  847. };
  848.  
  849. static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
  850. {
  851.         struct drm_device *dev = encoder->dev;
  852.         struct radeon_device *rdev = dev->dev_private;
  853.         uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  854.         DRM_DEBUG_KMS("\n");
  855.  
  856.         switch (mode) {
  857.         case DRM_MODE_DPMS_ON:
  858.                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
  859.                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  860.                 break;
  861.         case DRM_MODE_DPMS_STANDBY:
  862.         case DRM_MODE_DPMS_SUSPEND:
  863.         case DRM_MODE_DPMS_OFF:
  864.                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
  865.                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  866.                 break;
  867.         }
  868.  
  869.         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  870.  
  871.         if (rdev->is_atom_bios)
  872.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  873.         else
  874.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  875.  
  876. }
  877.  
  878. static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
  879. {
  880.         struct radeon_device *rdev = encoder->dev->dev_private;
  881.  
  882.         if (rdev->is_atom_bios)
  883.                 radeon_atom_output_lock(encoder, true);
  884.         else
  885.                 radeon_combios_output_lock(encoder, true);
  886.         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
  887. }
  888.  
  889. static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
  890. {
  891.         struct radeon_device *rdev = encoder->dev->dev_private;
  892.         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
  893.  
  894.         if (rdev->is_atom_bios)
  895.                 radeon_atom_output_lock(encoder, false);
  896.         else
  897.                 radeon_combios_output_lock(encoder, false);
  898. }
  899.  
  900. static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
  901.                                             struct drm_display_mode *mode,
  902.                                             struct drm_display_mode *adjusted_mode)
  903. {
  904.         struct drm_device *dev = encoder->dev;
  905.         struct radeon_device *rdev = dev->dev_private;
  906.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  907.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  908.         uint32_t fp2_gen_cntl;
  909.  
  910.         DRM_DEBUG_KMS("\n");
  911.  
  912.         if (rdev->is_atom_bios) {
  913.                 radeon_encoder->pixel_clock = adjusted_mode->clock;
  914.                 atombios_dvo_setup(encoder, ATOM_ENABLE);
  915.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  916.         } else {
  917.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  918.  
  919.                 if (1) /*  FIXME rgbBits == 8 */
  920.                         fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
  921.                 else
  922.                         fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
  923.  
  924.                 fp2_gen_cntl &= ~(RADEON_FP2_ON |
  925.                                   RADEON_FP2_DVO_EN |
  926.                                   RADEON_FP2_DVO_RATE_SEL_SDR);
  927.  
  928.                 /* XXX: these are oem specific */
  929.                 if (ASIC_IS_R300(rdev)) {
  930.                         if ((dev->pdev->device == 0x4850) &&
  931.                             (dev->pdev->subsystem_vendor == 0x1028) &&
  932.                             (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
  933.                                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
  934.                         else
  935.                                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
  936.  
  937.                         /*if (mode->clock > 165000)
  938.                           fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
  939.                 }
  940.                 if (!radeon_combios_external_tmds_setup(encoder))
  941.                         radeon_external_tmds_setup(encoder);
  942.         }
  943.  
  944.         if (radeon_crtc->crtc_id == 0) {
  945.                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
  946.                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
  947.                         if (radeon_encoder->rmx_type != RMX_OFF)
  948.                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
  949.                         else
  950.                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
  951.                 } else
  952.                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
  953.         } else {
  954.                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
  955.                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
  956.                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
  957.                 } else
  958.                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
  959.         }
  960.  
  961.         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  962.  
  963.         if (rdev->is_atom_bios)
  964.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  965.         else
  966.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  967. }
  968.  
  969. static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
  970. {
  971.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  972.         struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
  973.         if (tmds) {
  974.                 if (tmds->i2c_bus)
  975.                         radeon_i2c_destroy(tmds->i2c_bus);
  976.         }
  977.         kfree(radeon_encoder->enc_priv);
  978.         drm_encoder_cleanup(encoder);
  979.         kfree(radeon_encoder);
  980. }
  981.  
  982. static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
  983.         .dpms = radeon_legacy_tmds_ext_dpms,
  984.         .mode_fixup = radeon_legacy_mode_fixup,
  985.         .prepare = radeon_legacy_tmds_ext_prepare,
  986.         .mode_set = radeon_legacy_tmds_ext_mode_set,
  987.         .commit = radeon_legacy_tmds_ext_commit,
  988.         .disable = radeon_legacy_encoder_disable,
  989. };
  990.  
  991.  
  992. static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
  993.         .destroy = radeon_ext_tmds_enc_destroy,
  994. };
  995.  
  996. static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
  997. {
  998.         struct drm_device *dev = encoder->dev;
  999.         struct radeon_device *rdev = dev->dev_private;
  1000.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1001.         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
  1002.         uint32_t tv_master_cntl = 0;
  1003.         bool is_tv;
  1004.         DRM_DEBUG_KMS("\n");
  1005.  
  1006.         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
  1007.  
  1008.         if (rdev->family == CHIP_R200)
  1009.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  1010.         else {
  1011.                 if (is_tv)
  1012.                         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
  1013.                 else
  1014.                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  1015.                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1016.         }
  1017.  
  1018.         switch (mode) {
  1019.         case DRM_MODE_DPMS_ON:
  1020.                 if (rdev->family == CHIP_R200) {
  1021.                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  1022.                 } else {
  1023.                         if (is_tv)
  1024.                                 tv_master_cntl |= RADEON_TV_ON;
  1025.                         else
  1026.                         crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
  1027.  
  1028.                         if (rdev->family == CHIP_R420 ||
  1029.                                         rdev->family == CHIP_R423 ||
  1030.                                         rdev->family == CHIP_RV410)
  1031.                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
  1032.                                                 R420_TV_DAC_GDACPD |
  1033.                                                 R420_TV_DAC_BDACPD |
  1034.                                                 RADEON_TV_DAC_BGSLEEP);
  1035.                         else
  1036.                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
  1037.                                                 RADEON_TV_DAC_GDACPD |
  1038.                                                 RADEON_TV_DAC_BDACPD |
  1039.                                                 RADEON_TV_DAC_BGSLEEP);
  1040.                 }
  1041.                 break;
  1042.         case DRM_MODE_DPMS_STANDBY:
  1043.         case DRM_MODE_DPMS_SUSPEND:
  1044.         case DRM_MODE_DPMS_OFF:
  1045.                 if (rdev->family == CHIP_R200)
  1046.                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  1047.                 else {
  1048.                         if (is_tv)
  1049.                                 tv_master_cntl &= ~RADEON_TV_ON;
  1050.                         else
  1051.                         crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
  1052.  
  1053.                         if (rdev->family == CHIP_R420 ||
  1054.                                         rdev->family == CHIP_R423 ||
  1055.                                         rdev->family == CHIP_RV410)
  1056.                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
  1057.                                                 R420_TV_DAC_GDACPD |
  1058.                                                 R420_TV_DAC_BDACPD |
  1059.                                                 RADEON_TV_DAC_BGSLEEP);
  1060.                         else
  1061.                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
  1062.                                                 RADEON_TV_DAC_GDACPD |
  1063.                                                 RADEON_TV_DAC_BDACPD |
  1064.                                                 RADEON_TV_DAC_BGSLEEP);
  1065.                 }
  1066.                 break;
  1067.         }
  1068.  
  1069.         if (rdev->family == CHIP_R200) {
  1070.                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  1071.         } else {
  1072.                 if (is_tv)
  1073.                         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
  1074.                 else
  1075.                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  1076.                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1077.         }
  1078.  
  1079.         if (rdev->is_atom_bios)
  1080.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  1081.         else
  1082.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  1083.  
  1084. }
  1085.  
  1086. static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
  1087. {
  1088.         struct radeon_device *rdev = encoder->dev->dev_private;
  1089.  
  1090.         if (rdev->is_atom_bios)
  1091.                 radeon_atom_output_lock(encoder, true);
  1092.         else
  1093.                 radeon_combios_output_lock(encoder, true);
  1094.         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
  1095. }
  1096.  
  1097. static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
  1098. {
  1099.         struct radeon_device *rdev = encoder->dev->dev_private;
  1100.  
  1101.         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
  1102.  
  1103.         if (rdev->is_atom_bios)
  1104.                 radeon_atom_output_lock(encoder, true);
  1105.         else
  1106.                 radeon_combios_output_lock(encoder, true);
  1107. }
  1108.  
  1109. static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
  1110.                 struct drm_display_mode *mode,
  1111.                 struct drm_display_mode *adjusted_mode)
  1112. {
  1113.         struct drm_device *dev = encoder->dev;
  1114.         struct radeon_device *rdev = dev->dev_private;
  1115.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  1116.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1117.         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
  1118.         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
  1119.         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
  1120.         bool is_tv = false;
  1121.  
  1122.         DRM_DEBUG_KMS("\n");
  1123.  
  1124.         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
  1125.  
  1126.         if (rdev->family != CHIP_R200) {
  1127.                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1128.                 if (rdev->family == CHIP_R420 ||
  1129.                                 rdev->family == CHIP_R423 ||
  1130.                                 rdev->family == CHIP_RV410) {
  1131.                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
  1132.                                         RADEON_TV_DAC_BGADJ_MASK |
  1133.                                         R420_TV_DAC_DACADJ_MASK |
  1134.                                         R420_TV_DAC_RDACPD |
  1135.                                         R420_TV_DAC_GDACPD |
  1136.                                         R420_TV_DAC_BDACPD |
  1137.                                         R420_TV_DAC_TVENABLE);
  1138.                 } else {
  1139.                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
  1140.                                         RADEON_TV_DAC_BGADJ_MASK |
  1141.                                         RADEON_TV_DAC_DACADJ_MASK |
  1142.                                         RADEON_TV_DAC_RDACPD |
  1143.                                         RADEON_TV_DAC_GDACPD |
  1144.                                         RADEON_TV_DAC_BDACPD);
  1145.                 }
  1146.  
  1147.                 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
  1148.  
  1149.                 if (is_tv) {
  1150.                         if (tv_dac->tv_std == TV_STD_NTSC ||
  1151.                             tv_dac->tv_std == TV_STD_NTSC_J ||
  1152.                             tv_dac->tv_std == TV_STD_PAL_M ||
  1153.                             tv_dac->tv_std == TV_STD_PAL_60)
  1154.                                 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
  1155.                         else
  1156.                                 tv_dac_cntl |= tv_dac->pal_tvdac_adj;
  1157.  
  1158.                         if (tv_dac->tv_std == TV_STD_NTSC ||
  1159.                             tv_dac->tv_std == TV_STD_NTSC_J)
  1160.                                 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
  1161.                         else
  1162.                                 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
  1163.                 } else
  1164.                         tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
  1165.                                         tv_dac->ps2_tvdac_adj);
  1166.  
  1167.                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1168.         }
  1169.  
  1170.         if (ASIC_IS_R300(rdev)) {
  1171.                 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
  1172.                 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
  1173.         } else if (rdev->family != CHIP_R200)
  1174.                 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
  1175.         else if (rdev->family == CHIP_R200)
  1176.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  1177.  
  1178.         if (rdev->family >= CHIP_R200)
  1179.                 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
  1180.  
  1181.         if (is_tv) {
  1182.                 uint32_t dac_cntl;
  1183.  
  1184.                 dac_cntl = RREG32(RADEON_DAC_CNTL);
  1185.                 dac_cntl &= ~RADEON_DAC_TVO_EN;
  1186.                 WREG32(RADEON_DAC_CNTL, dac_cntl);
  1187.  
  1188.                 if (ASIC_IS_R300(rdev))
  1189.                         gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
  1190.  
  1191.                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
  1192.                 if (radeon_crtc->crtc_id == 0) {
  1193.                         if (ASIC_IS_R300(rdev)) {
  1194.                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1195.                                 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
  1196.                                                      RADEON_DISP_TV_SOURCE_CRTC);
  1197.                         }
  1198.                         if (rdev->family >= CHIP_R200) {
  1199.                                 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
  1200.                         } else {
  1201.                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
  1202.                         }
  1203.                 } else {
  1204.                         if (ASIC_IS_R300(rdev)) {
  1205.                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1206.                                 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
  1207.                         }
  1208.                         if (rdev->family >= CHIP_R200) {
  1209.                                 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
  1210.                         } else {
  1211.                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
  1212.                         }
  1213.                 }
  1214.                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  1215.         } else {
  1216.  
  1217.         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
  1218.  
  1219.         if (radeon_crtc->crtc_id == 0) {
  1220.                 if (ASIC_IS_R300(rdev)) {
  1221.                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1222.                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
  1223.                 } else if (rdev->family == CHIP_R200) {
  1224.                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
  1225.                                           RADEON_FP2_DVO_RATE_SEL_SDR);
  1226.                 } else
  1227.                         disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
  1228.         } else {
  1229.                 if (ASIC_IS_R300(rdev)) {
  1230.                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1231.                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  1232.                 } else if (rdev->family == CHIP_R200) {
  1233.                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
  1234.                                           RADEON_FP2_DVO_RATE_SEL_SDR);
  1235.                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
  1236.                 } else
  1237.                         disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
  1238.         }
  1239.         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  1240.         }
  1241.  
  1242.         if (ASIC_IS_R300(rdev)) {
  1243.                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  1244.                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  1245.         } else if (rdev->family != CHIP_R200)
  1246.                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
  1247.         else if (rdev->family == CHIP_R200)
  1248.                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  1249.  
  1250.         if (rdev->family >= CHIP_R200)
  1251.                 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
  1252.  
  1253.         if (is_tv)
  1254.                 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
  1255.  
  1256.         if (rdev->is_atom_bios)
  1257.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  1258.         else
  1259.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  1260.  
  1261. }
  1262.  
  1263. static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
  1264.                                   struct drm_connector *connector)
  1265. {
  1266.         struct drm_device *dev = encoder->dev;
  1267.         struct radeon_device *rdev = dev->dev_private;
  1268.         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
  1269.         uint32_t disp_output_cntl, gpiopad_a, tmp;
  1270.         bool found = false;
  1271.  
  1272.         /* save regs needed */
  1273.         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
  1274.         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1275.         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  1276.         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  1277.         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1278.         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
  1279.  
  1280.         WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
  1281.  
  1282.         WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
  1283.  
  1284.         WREG32(RADEON_CRTC2_GEN_CNTL,
  1285.                RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
  1286.  
  1287.         tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1288.         tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  1289.         WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
  1290.  
  1291.         WREG32(RADEON_DAC_EXT_CNTL,
  1292.                RADEON_DAC2_FORCE_BLANK_OFF_EN |
  1293.                RADEON_DAC2_FORCE_DATA_EN |
  1294.                RADEON_DAC_FORCE_DATA_SEL_RGB |
  1295.                (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
  1296.  
  1297.         WREG32(RADEON_TV_DAC_CNTL,
  1298.                RADEON_TV_DAC_STD_NTSC |
  1299.                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
  1300.                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
  1301.  
  1302.         RREG32(RADEON_TV_DAC_CNTL);
  1303.         mdelay(4);
  1304.  
  1305.         WREG32(RADEON_TV_DAC_CNTL,
  1306.                RADEON_TV_DAC_NBLANK |
  1307.                RADEON_TV_DAC_NHOLD |
  1308.                RADEON_TV_MONITOR_DETECT_EN |
  1309.                RADEON_TV_DAC_STD_NTSC |
  1310.                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
  1311.                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
  1312.  
  1313.         RREG32(RADEON_TV_DAC_CNTL);
  1314.         mdelay(6);
  1315.  
  1316.         tmp = RREG32(RADEON_TV_DAC_CNTL);
  1317.         if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
  1318.                 found = true;
  1319.                 DRM_DEBUG_KMS("S-video TV connection detected\n");
  1320.         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
  1321.                 found = true;
  1322.                 DRM_DEBUG_KMS("Composite TV connection detected\n");
  1323.         }
  1324.  
  1325.         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1326.         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  1327.         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  1328.         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  1329.         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1330.         WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  1331.         return found;
  1332. }
  1333.  
  1334. static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
  1335.                                     struct drm_connector *connector)
  1336. {
  1337.         struct drm_device *dev = encoder->dev;
  1338.         struct radeon_device *rdev = dev->dev_private;
  1339.         uint32_t tv_dac_cntl, dac_cntl2;
  1340.         uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
  1341.         bool found = false;
  1342.  
  1343.         if (ASIC_IS_R300(rdev))
  1344.                 return r300_legacy_tv_detect(encoder, connector);
  1345.  
  1346.         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1347.         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
  1348.         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1349.         config_cntl = RREG32(RADEON_CONFIG_CNTL);
  1350.         tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
  1351.  
  1352.         tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
  1353.         WREG32(RADEON_DAC_CNTL2, tmp);
  1354.  
  1355.         tmp = tv_master_cntl | RADEON_TV_ON;
  1356.         tmp &= ~(RADEON_TV_ASYNC_RST |
  1357.                  RADEON_RESTART_PHASE_FIX |
  1358.                  RADEON_CRT_FIFO_CE_EN |
  1359.                  RADEON_TV_FIFO_CE_EN |
  1360.                  RADEON_RE_SYNC_NOW_SEL_MASK);
  1361.         tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
  1362.         WREG32(RADEON_TV_MASTER_CNTL, tmp);
  1363.  
  1364.         tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
  1365.                 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
  1366.                 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
  1367.  
  1368.         if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
  1369.                 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
  1370.         else
  1371.                 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
  1372.         WREG32(RADEON_TV_DAC_CNTL, tmp);
  1373.  
  1374.         tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
  1375.                 RADEON_RED_MX_FORCE_DAC_DATA |
  1376.                 RADEON_GRN_MX_FORCE_DAC_DATA |
  1377.                 RADEON_BLU_MX_FORCE_DAC_DATA |
  1378.                 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
  1379.         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
  1380.  
  1381.         mdelay(3);
  1382.         tmp = RREG32(RADEON_TV_DAC_CNTL);
  1383.         if (tmp & RADEON_TV_DAC_GDACDET) {
  1384.                 found = true;
  1385.                 DRM_DEBUG_KMS("S-video TV connection detected\n");
  1386.         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
  1387.                 found = true;
  1388.                 DRM_DEBUG_KMS("Composite TV connection detected\n");
  1389.         }
  1390.  
  1391.         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
  1392.         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1393.         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
  1394.         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1395.         return found;
  1396. }
  1397.  
  1398. static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
  1399.                                                              struct drm_connector *connector)
  1400. {
  1401.         struct drm_device *dev = encoder->dev;
  1402.         struct radeon_device *rdev = dev->dev_private;
  1403.         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
  1404.         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
  1405.         enum drm_connector_status found = connector_status_disconnected;
  1406.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1407.         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
  1408.         bool color = true;
  1409.         struct drm_crtc *crtc;
  1410.  
  1411.         /* find out if crtc2 is in use or if this encoder is using it */
  1412.         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1413.                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  1414.                 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
  1415.                         if (encoder->crtc != crtc) {
  1416.                                 return connector_status_disconnected;
  1417.                         }
  1418.                 }
  1419.         }
  1420.  
  1421.         if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
  1422.             connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
  1423.             connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
  1424.                 bool tv_detect;
  1425.  
  1426.                 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
  1427.                         return connector_status_disconnected;
  1428.  
  1429.                 tv_detect = radeon_legacy_tv_detect(encoder, connector);
  1430.                 if (tv_detect && tv_dac)
  1431.                         found = connector_status_connected;
  1432.                 return found;
  1433.         }
  1434.  
  1435.         /* don't probe if the encoder is being used for something else not CRT related */
  1436.         if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
  1437.                 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
  1438.                 return connector_status_disconnected;
  1439.         }
  1440.  
  1441.         /* save the regs we need */
  1442.         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  1443.         gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
  1444.         disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
  1445.         disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
  1446.         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  1447.         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1448.         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  1449.         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1450.  
  1451.         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
  1452.                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
  1453.         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
  1454.  
  1455.         if (ASIC_IS_R300(rdev))
  1456.                 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
  1457.  
  1458.         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
  1459.         tmp |= RADEON_CRTC2_CRT2_ON |
  1460.                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
  1461.  
  1462.         WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
  1463.  
  1464.         if (ASIC_IS_R300(rdev)) {
  1465.                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1466.                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  1467.                 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
  1468.         } else {
  1469.                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
  1470.                 WREG32(RADEON_DISP_HW_DEBUG, tmp);
  1471.         }
  1472.  
  1473.         tmp = RADEON_TV_DAC_NBLANK |
  1474.                 RADEON_TV_DAC_NHOLD |
  1475.                 RADEON_TV_MONITOR_DETECT_EN |
  1476.                 RADEON_TV_DAC_STD_PS2;
  1477.  
  1478.         WREG32(RADEON_TV_DAC_CNTL, tmp);
  1479.  
  1480.         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
  1481.                 RADEON_DAC2_FORCE_DATA_EN;
  1482.  
  1483.         if (color)
  1484.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
  1485.         else
  1486.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
  1487.  
  1488.         if (ASIC_IS_R300(rdev))
  1489.                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
  1490.         else
  1491.                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
  1492.  
  1493.         WREG32(RADEON_DAC_EXT_CNTL, tmp);
  1494.  
  1495.         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
  1496.         WREG32(RADEON_DAC_CNTL2, tmp);
  1497.  
  1498.         udelay(10000);
  1499.  
  1500.         if (ASIC_IS_R300(rdev)) {
  1501.                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
  1502.                         found = connector_status_connected;
  1503.         } else {
  1504.                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
  1505.                         found = connector_status_connected;
  1506.         }
  1507.  
  1508.         /* restore regs we used */
  1509.         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1510.         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  1511.         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1512.         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  1513.  
  1514.         if (ASIC_IS_R300(rdev)) {
  1515.                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  1516.                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  1517.         } else {
  1518.                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
  1519.         }
  1520.         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  1521.  
  1522.         return found;
  1523.  
  1524. }
  1525.  
  1526. static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
  1527.         .dpms = radeon_legacy_tv_dac_dpms,
  1528.         .mode_fixup = radeon_legacy_mode_fixup,
  1529.         .prepare = radeon_legacy_tv_dac_prepare,
  1530.         .mode_set = radeon_legacy_tv_dac_mode_set,
  1531.         .commit = radeon_legacy_tv_dac_commit,
  1532.         .detect = radeon_legacy_tv_dac_detect,
  1533.         .disable = radeon_legacy_encoder_disable,
  1534. };
  1535.  
  1536.  
  1537. static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
  1538.         .destroy = radeon_enc_destroy,
  1539. };
  1540.  
  1541.  
  1542. static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
  1543. {
  1544.         struct drm_device *dev = encoder->base.dev;
  1545.         struct radeon_device *rdev = dev->dev_private;
  1546.         struct radeon_encoder_int_tmds *tmds = NULL;
  1547.         bool ret;
  1548.  
  1549.         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
  1550.  
  1551.         if (!tmds)
  1552.                 return NULL;
  1553.  
  1554.         if (rdev->is_atom_bios)
  1555.                 ret = radeon_atombios_get_tmds_info(encoder, tmds);
  1556.         else
  1557.                 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
  1558.  
  1559.         if (ret == false)
  1560.                 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
  1561.  
  1562.         return tmds;
  1563. }
  1564.  
  1565. static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
  1566. {
  1567.         struct drm_device *dev = encoder->base.dev;
  1568.         struct radeon_device *rdev = dev->dev_private;
  1569.         struct radeon_encoder_ext_tmds *tmds = NULL;
  1570.         bool ret;
  1571.  
  1572.         if (rdev->is_atom_bios)
  1573.                 return NULL;
  1574.  
  1575.         tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
  1576.  
  1577.         if (!tmds)
  1578.                 return NULL;
  1579.  
  1580.         ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
  1581.  
  1582.         if (ret == false)
  1583.                 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
  1584.  
  1585.         return tmds;
  1586. }
  1587.  
  1588. void
  1589. radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
  1590. {
  1591.         struct radeon_device *rdev = dev->dev_private;
  1592.         struct drm_encoder *encoder;
  1593.         struct radeon_encoder *radeon_encoder;
  1594.  
  1595.         /* see if we already added it */
  1596.         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1597.                 radeon_encoder = to_radeon_encoder(encoder);
  1598.                 if (radeon_encoder->encoder_enum == encoder_enum) {
  1599.                         radeon_encoder->devices |= supported_device;
  1600.                         return;
  1601.                 }
  1602.  
  1603.         }
  1604.  
  1605.         /* add a new one */
  1606.         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
  1607.         if (!radeon_encoder)
  1608.                 return;
  1609.  
  1610.         encoder = &radeon_encoder->base;
  1611.         if (rdev->flags & RADEON_SINGLE_CRTC)
  1612.                 encoder->possible_crtcs = 0x1;
  1613.         else
  1614.         encoder->possible_crtcs = 0x3;
  1615.  
  1616.         radeon_encoder->enc_priv = NULL;
  1617.  
  1618.         radeon_encoder->encoder_enum = encoder_enum;
  1619.         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
  1620.         radeon_encoder->devices = supported_device;
  1621.         radeon_encoder->rmx_type = RMX_OFF;
  1622.  
  1623.         switch (radeon_encoder->encoder_id) {
  1624.         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1625.                 encoder->possible_crtcs = 0x1;
  1626.                 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
  1627.                 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
  1628.                 if (rdev->is_atom_bios)
  1629.                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
  1630.                 else
  1631.                         radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
  1632.                 radeon_encoder->rmx_type = RMX_FULL;
  1633.                 break;
  1634.         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1635.                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
  1636.                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
  1637.                 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
  1638.                 break;
  1639.         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1640.                 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
  1641.                 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
  1642.                 if (rdev->is_atom_bios)
  1643.                         radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
  1644.                 else
  1645.                         radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
  1646.                 break;
  1647.         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1648.                 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
  1649.                 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
  1650.                 if (rdev->is_atom_bios)
  1651.                         radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
  1652.                 else
  1653.                         radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
  1654.                 break;
  1655.         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1656.                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
  1657.                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
  1658.                 if (!rdev->is_atom_bios)
  1659.                         radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
  1660.                 break;
  1661.         }
  1662. }
  1663.