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  1. /*
  2.  * Copyright 2007-8 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the "Software"),
  7.  * to deal in the Software without restriction, including without limitation
  8.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9.  * and/or sell copies of the Software, and to permit persons to whom the
  10.  * Software is furnished to do so, subject to the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice shall be included in
  13.  * all copies or substantial portions of the Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21.  * OTHER DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors: Dave Airlie
  24.  *          Alex Deucher
  25.  */
  26. #include "drmP.h"
  27. #include "drm_crtc_helper.h"
  28. #include "radeon_drm.h"
  29. #include "radeon.h"
  30. #include "atom.h"
  31.  
  32. static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  33. {
  34.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  35.         struct drm_encoder_helper_funcs *encoder_funcs;
  36.  
  37.         encoder_funcs = encoder->helper_private;
  38.         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  39.         radeon_encoder->active_device = 0;
  40. }
  41.  
  42. static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
  43. {
  44.         struct drm_device *dev = encoder->dev;
  45.         struct radeon_device *rdev = dev->dev_private;
  46.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  47.         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  48.         int panel_pwr_delay = 2000;
  49.         DRM_DEBUG("\n");
  50.  
  51.         if (radeon_encoder->enc_priv) {
  52.                 if (rdev->is_atom_bios) {
  53.                         struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  54.                         panel_pwr_delay = lvds->panel_pwr_delay;
  55.                 } else {
  56.                         struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  57.                         panel_pwr_delay = lvds->panel_pwr_delay;
  58.                 }
  59.         }
  60.  
  61.         switch (mode) {
  62.         case DRM_MODE_DPMS_ON:
  63.                 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  64.                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  65.                 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  66.                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  67.                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  68.                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  69.                 udelay(1000);
  70.  
  71.                 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  72.                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  73.                 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  74.  
  75.                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  76.                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
  77.                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
  78.                 udelay(panel_pwr_delay * 1000);
  79.                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  80.                 break;
  81.         case DRM_MODE_DPMS_STANDBY:
  82.         case DRM_MODE_DPMS_SUSPEND:
  83.         case DRM_MODE_DPMS_OFF:
  84.                 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  85.                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
  86.                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  87.                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  88.                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
  89.                 udelay(panel_pwr_delay * 1000);
  90.                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  91.                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  92.                 break;
  93.         }
  94.  
  95.         if (rdev->is_atom_bios)
  96.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  97.         else
  98.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  99. }
  100.  
  101. static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
  102. {
  103.         struct radeon_device *rdev = encoder->dev->dev_private;
  104.  
  105.         if (rdev->is_atom_bios)
  106.                 radeon_atom_output_lock(encoder, true);
  107.         else
  108.                 radeon_combios_output_lock(encoder, true);
  109.         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
  110. }
  111.  
  112. static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
  113. {
  114.         struct radeon_device *rdev = encoder->dev->dev_private;
  115.  
  116.         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
  117.         if (rdev->is_atom_bios)
  118.                 radeon_atom_output_lock(encoder, false);
  119.         else
  120.                 radeon_combios_output_lock(encoder, false);
  121. }
  122.  
  123. static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
  124.                                         struct drm_display_mode *mode,
  125.                                         struct drm_display_mode *adjusted_mode)
  126. {
  127.         struct drm_device *dev = encoder->dev;
  128.         struct radeon_device *rdev = dev->dev_private;
  129.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  130.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  131.         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
  132.  
  133.         DRM_DEBUG("\n");
  134.  
  135.         lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  136.         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
  137.  
  138.         lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
  139.         if ((!rdev->is_atom_bios)) {
  140.                 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
  141.                 if (lvds) {
  142.                         DRM_DEBUG("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
  143.                         lvds_gen_cntl = lvds->lvds_gen_cntl;
  144.                         lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
  145.                                               (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
  146.                         lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
  147.                                              (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
  148.                 } else
  149.                         lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  150.         } else
  151.                 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  152.         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
  153.         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
  154.                            RADEON_LVDS_BLON |
  155.                            RADEON_LVDS_EN |
  156.                            RADEON_LVDS_RST_FM);
  157.  
  158.         if (ASIC_IS_R300(rdev))
  159.                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
  160.  
  161.         if (radeon_crtc->crtc_id == 0) {
  162.                 if (ASIC_IS_R300(rdev)) {
  163.                         if (radeon_encoder->rmx_type != RMX_OFF)
  164.                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
  165.                 } else
  166.                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
  167.         } else {
  168.                 if (ASIC_IS_R300(rdev))
  169.                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
  170.                 else
  171.                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
  172.         }
  173.  
  174.         WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
  175.         WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  176.         WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
  177.  
  178.         if (rdev->family == CHIP_RV410)
  179.                 WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
  180.  
  181.         if (rdev->is_atom_bios)
  182.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  183.         else
  184.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  185. }
  186.  
  187. static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
  188.                                           struct drm_display_mode *mode,
  189.                                           struct drm_display_mode *adjusted_mode)
  190. {
  191.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  192.  
  193.         /* set the active encoder to connector routing */
  194.         radeon_encoder_set_active_device(encoder);
  195.         drm_mode_set_crtcinfo(adjusted_mode, 0);
  196.  
  197.         if (radeon_encoder->rmx_type != RMX_OFF)
  198.                 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
  199.  
  200.         return true;
  201. }
  202.  
  203. static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
  204.         .dpms = radeon_legacy_lvds_dpms,
  205.         .mode_fixup = radeon_legacy_lvds_mode_fixup,
  206.         .prepare = radeon_legacy_lvds_prepare,
  207.         .mode_set = radeon_legacy_lvds_mode_set,
  208.         .commit = radeon_legacy_lvds_commit,
  209.         .disable = radeon_legacy_encoder_disable,
  210. };
  211.  
  212.  
  213. static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
  214.         .destroy = radeon_enc_destroy,
  215. };
  216.  
  217. static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
  218.                                                  struct drm_display_mode *mode,
  219.                                                  struct drm_display_mode *adjusted_mode)
  220. {
  221.         /* set the active encoder to connector routing */
  222.         radeon_encoder_set_active_device(encoder);
  223.         drm_mode_set_crtcinfo(adjusted_mode, 0);
  224.  
  225.         return true;
  226. }
  227.  
  228. static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
  229. {
  230.         struct drm_device *dev = encoder->dev;
  231.         struct radeon_device *rdev = dev->dev_private;
  232.         uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  233.         uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
  234.         uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  235.  
  236.         DRM_DEBUG("\n");
  237.  
  238.         switch (mode) {
  239.         case DRM_MODE_DPMS_ON:
  240.                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
  241.                 dac_cntl &= ~RADEON_DAC_PDWN;
  242.                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
  243.                                     RADEON_DAC_PDWN_G |
  244.                                     RADEON_DAC_PDWN_B);
  245.                 break;
  246.         case DRM_MODE_DPMS_STANDBY:
  247.         case DRM_MODE_DPMS_SUSPEND:
  248.         case DRM_MODE_DPMS_OFF:
  249.                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
  250.                 dac_cntl |= RADEON_DAC_PDWN;
  251.                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
  252.                                    RADEON_DAC_PDWN_G |
  253.                                    RADEON_DAC_PDWN_B);
  254.                 break;
  255.         }
  256.  
  257.         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  258.         WREG32(RADEON_DAC_CNTL, dac_cntl);
  259.         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  260.  
  261.         if (rdev->is_atom_bios)
  262.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  263.         else
  264.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  265. }
  266.  
  267. static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
  268. {
  269.         struct radeon_device *rdev = encoder->dev->dev_private;
  270.  
  271.         if (rdev->is_atom_bios)
  272.                 radeon_atom_output_lock(encoder, true);
  273.         else
  274.                 radeon_combios_output_lock(encoder, true);
  275.         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
  276. }
  277.  
  278. static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
  279. {
  280.         struct radeon_device *rdev = encoder->dev->dev_private;
  281.  
  282.         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
  283.  
  284.         if (rdev->is_atom_bios)
  285.                 radeon_atom_output_lock(encoder, false);
  286.         else
  287.                 radeon_combios_output_lock(encoder, false);
  288. }
  289.  
  290. static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
  291.                                                struct drm_display_mode *mode,
  292.                                                struct drm_display_mode *adjusted_mode)
  293. {
  294.         struct drm_device *dev = encoder->dev;
  295.         struct radeon_device *rdev = dev->dev_private;
  296.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  297.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  298.         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
  299.  
  300.         DRM_DEBUG("\n");
  301.  
  302.         if (radeon_crtc->crtc_id == 0) {
  303.                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
  304.                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
  305.                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
  306.                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  307.                 } else {
  308.                         dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
  309.                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  310.                 }
  311.         } else {
  312.                 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
  313.                         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
  314.                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
  315.                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
  316.                         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  317.                 } else {
  318.                         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
  319.                         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  320.                 }
  321.         }
  322.  
  323.         dac_cntl = (RADEON_DAC_MASK_ALL |
  324.                     RADEON_DAC_VGA_ADR_EN |
  325.                     /* TODO 6-bits */
  326.                     RADEON_DAC_8BIT_EN);
  327.  
  328.         WREG32_P(RADEON_DAC_CNTL,
  329.                        dac_cntl,
  330.                        RADEON_DAC_RANGE_CNTL |
  331.                        RADEON_DAC_BLANKING);
  332.  
  333.         if (radeon_encoder->enc_priv) {
  334.                 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
  335.                 dac_macro_cntl = p_dac->ps2_pdac_adj;
  336.         } else
  337.                 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  338.         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
  339.         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  340.  
  341.         if (rdev->is_atom_bios)
  342.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  343.         else
  344.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  345. }
  346.  
  347. static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
  348.                                                                   struct drm_connector *connector)
  349. {
  350.         struct drm_device *dev = encoder->dev;
  351.         struct radeon_device *rdev = dev->dev_private;
  352.         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
  353.         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
  354.         enum drm_connector_status found = connector_status_disconnected;
  355.         bool color = true;
  356.  
  357.         /* save the regs we need */
  358.         vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
  359.         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  360.         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  361.         dac_cntl = RREG32(RADEON_DAC_CNTL);
  362.         dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
  363.  
  364.         tmp = vclk_ecp_cntl &
  365.                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
  366.         WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
  367.  
  368.         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
  369.         WREG32(RADEON_CRTC_EXT_CNTL, tmp);
  370.  
  371.         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
  372.                 RADEON_DAC_FORCE_DATA_EN;
  373.  
  374.         if (color)
  375.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
  376.         else
  377.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
  378.  
  379.         if (ASIC_IS_R300(rdev))
  380.                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
  381.         else
  382.                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
  383.  
  384.         WREG32(RADEON_DAC_EXT_CNTL, tmp);
  385.  
  386.         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
  387.         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
  388.         WREG32(RADEON_DAC_CNTL, tmp);
  389.  
  390.         tmp &= ~(RADEON_DAC_PDWN_R |
  391.                  RADEON_DAC_PDWN_G |
  392.                  RADEON_DAC_PDWN_B);
  393.  
  394.         WREG32(RADEON_DAC_MACRO_CNTL, tmp);
  395.  
  396.         udelay(2000);
  397.  
  398.         if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
  399.                 found = connector_status_connected;
  400.  
  401.         /* restore the regs we used */
  402.         WREG32(RADEON_DAC_CNTL, dac_cntl);
  403.         WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
  404.         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  405.         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  406.         WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
  407.  
  408.         return found;
  409. }
  410.  
  411. static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
  412.         .dpms = radeon_legacy_primary_dac_dpms,
  413.         .mode_fixup = radeon_legacy_primary_dac_mode_fixup,
  414.         .prepare = radeon_legacy_primary_dac_prepare,
  415.         .mode_set = radeon_legacy_primary_dac_mode_set,
  416.         .commit = radeon_legacy_primary_dac_commit,
  417.         .detect = radeon_legacy_primary_dac_detect,
  418.         .disable = radeon_legacy_encoder_disable,
  419. };
  420.  
  421.  
  422. static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
  423.         .destroy = radeon_enc_destroy,
  424. };
  425.  
  426. static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
  427.                                               struct drm_display_mode *mode,
  428.                                               struct drm_display_mode *adjusted_mode)
  429. {
  430.  
  431.         drm_mode_set_crtcinfo(adjusted_mode, 0);
  432.  
  433.         return true;
  434. }
  435.  
  436. static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
  437. {
  438.         struct drm_device *dev = encoder->dev;
  439.         struct radeon_device *rdev = dev->dev_private;
  440.         uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
  441.         DRM_DEBUG("\n");
  442.  
  443.         switch (mode) {
  444.         case DRM_MODE_DPMS_ON:
  445.                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  446.                 break;
  447.         case DRM_MODE_DPMS_STANDBY:
  448.         case DRM_MODE_DPMS_SUSPEND:
  449.         case DRM_MODE_DPMS_OFF:
  450.                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  451.                 break;
  452.         }
  453.  
  454.         WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
  455.  
  456.         if (rdev->is_atom_bios)
  457.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  458.         else
  459.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  460. }
  461.  
  462. static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
  463. {
  464.         struct radeon_device *rdev = encoder->dev->dev_private;
  465.  
  466.         if (rdev->is_atom_bios)
  467.                 radeon_atom_output_lock(encoder, true);
  468.         else
  469.                 radeon_combios_output_lock(encoder, true);
  470.         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
  471. }
  472.  
  473. static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
  474. {
  475.         struct radeon_device *rdev = encoder->dev->dev_private;
  476.  
  477.         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
  478.  
  479.         if (rdev->is_atom_bios)
  480.                 radeon_atom_output_lock(encoder, true);
  481.         else
  482.                 radeon_combios_output_lock(encoder, true);
  483. }
  484.  
  485. static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
  486.                                             struct drm_display_mode *mode,
  487.                                             struct drm_display_mode *adjusted_mode)
  488. {
  489.         struct drm_device *dev = encoder->dev;
  490.         struct radeon_device *rdev = dev->dev_private;
  491.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  492.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  493.         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
  494.         int i;
  495.  
  496.         DRM_DEBUG("\n");
  497.  
  498.         tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
  499.         tmp &= 0xfffff;
  500.         if (rdev->family == CHIP_RV280) {
  501.                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
  502.                 tmp ^= (1 << 22);
  503.                 tmds_pll_cntl ^= (1 << 22);
  504.         }
  505.  
  506.         if (radeon_encoder->enc_priv) {
  507.                 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
  508.  
  509.                 for (i = 0; i < 4; i++) {
  510.                         if (tmds->tmds_pll[i].freq == 0)
  511.                                 break;
  512.                         if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
  513.                                 tmp = tmds->tmds_pll[i].value ;
  514.                                 break;
  515.                         }
  516.                 }
  517.         }
  518.  
  519.         if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
  520.                 if (tmp & 0xfff00000)
  521.                         tmds_pll_cntl = tmp;
  522.                 else {
  523.                         tmds_pll_cntl &= 0xfff00000;
  524.                         tmds_pll_cntl |= tmp;
  525.                 }
  526.         } else
  527.                 tmds_pll_cntl = tmp;
  528.  
  529.         tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
  530.                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
  531.  
  532.     if (rdev->family == CHIP_R200 ||
  533.         rdev->family == CHIP_R100 ||
  534.         ASIC_IS_R300(rdev))
  535.             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
  536.     else /* RV chips got this bit reversed */
  537.             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
  538.  
  539.     fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
  540.                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
  541.                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
  542.  
  543.     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
  544.  
  545.     fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
  546.                      RADEON_FP_DFP_SYNC_SEL |
  547.                      RADEON_FP_CRT_SYNC_SEL |
  548.                      RADEON_FP_CRTC_LOCK_8DOT |
  549.                      RADEON_FP_USE_SHADOW_EN |
  550.                      RADEON_FP_CRTC_USE_SHADOW_VEND |
  551.                      RADEON_FP_CRT_SYNC_ALT);
  552.  
  553.     if (1) /*  FIXME rgbBits == 8 */
  554.             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
  555.     else
  556.             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
  557.  
  558.     if (radeon_crtc->crtc_id == 0) {
  559.             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
  560.                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
  561.                     if (radeon_encoder->rmx_type != RMX_OFF)
  562.                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
  563.                     else
  564.                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
  565.             } else
  566.                     fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
  567.     } else {
  568.             if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
  569.                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
  570.                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
  571.             } else
  572.                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
  573.     }
  574.  
  575.     WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
  576.     WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
  577.     WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
  578.  
  579.         if (rdev->is_atom_bios)
  580.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  581.         else
  582.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  583. }
  584.  
  585. static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
  586.         .dpms = radeon_legacy_tmds_int_dpms,
  587.         .mode_fixup = radeon_legacy_tmds_int_mode_fixup,
  588.         .prepare = radeon_legacy_tmds_int_prepare,
  589.         .mode_set = radeon_legacy_tmds_int_mode_set,
  590.         .commit = radeon_legacy_tmds_int_commit,
  591.         .disable = radeon_legacy_encoder_disable,
  592. };
  593.  
  594.  
  595. static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
  596.         .destroy = radeon_enc_destroy,
  597. };
  598.  
  599. static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
  600.                                               struct drm_display_mode *mode,
  601.                                               struct drm_display_mode *adjusted_mode)
  602. {
  603.         /* set the active encoder to connector routing */
  604.         radeon_encoder_set_active_device(encoder);
  605.         drm_mode_set_crtcinfo(adjusted_mode, 0);
  606.  
  607.         return true;
  608. }
  609.  
  610. static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
  611. {
  612.         struct drm_device *dev = encoder->dev;
  613.         struct radeon_device *rdev = dev->dev_private;
  614.         uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  615.         DRM_DEBUG("\n");
  616.  
  617.         switch (mode) {
  618.         case DRM_MODE_DPMS_ON:
  619.                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
  620.                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  621.                 break;
  622.         case DRM_MODE_DPMS_STANDBY:
  623.         case DRM_MODE_DPMS_SUSPEND:
  624.         case DRM_MODE_DPMS_OFF:
  625.                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
  626.                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  627.                 break;
  628.         }
  629.  
  630.         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  631.  
  632.         if (rdev->is_atom_bios)
  633.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  634.         else
  635.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  636. }
  637.  
  638. static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
  639. {
  640.         struct radeon_device *rdev = encoder->dev->dev_private;
  641.  
  642.         if (rdev->is_atom_bios)
  643.                 radeon_atom_output_lock(encoder, true);
  644.         else
  645.                 radeon_combios_output_lock(encoder, true);
  646.         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
  647. }
  648.  
  649. static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
  650. {
  651.         struct radeon_device *rdev = encoder->dev->dev_private;
  652.         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
  653.  
  654.         if (rdev->is_atom_bios)
  655.                 radeon_atom_output_lock(encoder, false);
  656.         else
  657.                 radeon_combios_output_lock(encoder, false);
  658. }
  659.  
  660. static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
  661.                                             struct drm_display_mode *mode,
  662.                                             struct drm_display_mode *adjusted_mode)
  663. {
  664.         struct drm_device *dev = encoder->dev;
  665.         struct radeon_device *rdev = dev->dev_private;
  666.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  667.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  668.         uint32_t fp2_gen_cntl;
  669.  
  670.         DRM_DEBUG("\n");
  671.  
  672.         if (rdev->is_atom_bios) {
  673.                 radeon_encoder->pixel_clock = adjusted_mode->clock;
  674.                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
  675.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  676.         } else {
  677.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  678.  
  679.                 if (1) /*  FIXME rgbBits == 8 */
  680.                         fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
  681.                 else
  682.                         fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
  683.  
  684.                 fp2_gen_cntl &= ~(RADEON_FP2_ON |
  685.                                   RADEON_FP2_DVO_EN |
  686.                                   RADEON_FP2_DVO_RATE_SEL_SDR);
  687.  
  688.                 /* XXX: these are oem specific */
  689.                 if (ASIC_IS_R300(rdev)) {
  690.                         if ((dev->pdev->device == 0x4850) &&
  691.                             (dev->pdev->subsystem_vendor == 0x1028) &&
  692.                             (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
  693.                                 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
  694.                         else
  695.                                 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
  696.  
  697.                         /*if (mode->clock > 165000)
  698.                           fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
  699.                 }
  700.         }
  701.  
  702.         if (radeon_crtc->crtc_id == 0) {
  703.                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
  704.                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
  705.                         if (radeon_encoder->rmx_type != RMX_OFF)
  706.                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
  707.                         else
  708.                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
  709.                 } else
  710.                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
  711.         } else {
  712.                 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
  713.                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
  714.                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
  715.                 } else
  716.                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
  717.         }
  718.  
  719.         WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  720.  
  721.         if (rdev->is_atom_bios)
  722.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  723.         else
  724.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  725. }
  726.  
  727. static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
  728.         .dpms = radeon_legacy_tmds_ext_dpms,
  729.         .mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
  730.         .prepare = radeon_legacy_tmds_ext_prepare,
  731.         .mode_set = radeon_legacy_tmds_ext_mode_set,
  732.         .commit = radeon_legacy_tmds_ext_commit,
  733.         .disable = radeon_legacy_encoder_disable,
  734. };
  735.  
  736.  
  737. static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
  738.         .destroy = radeon_enc_destroy,
  739. };
  740.  
  741. static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
  742.                                             struct drm_display_mode *mode,
  743.                                             struct drm_display_mode *adjusted_mode)
  744. {
  745.         /* set the active encoder to connector routing */
  746.         radeon_encoder_set_active_device(encoder);
  747.         drm_mode_set_crtcinfo(adjusted_mode, 0);
  748.  
  749.         return true;
  750. }
  751.  
  752. static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
  753. {
  754.         struct drm_device *dev = encoder->dev;
  755.         struct radeon_device *rdev = dev->dev_private;
  756.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  757.         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
  758.         uint32_t tv_master_cntl = 0;
  759.         bool is_tv;
  760.         DRM_DEBUG("\n");
  761.  
  762.         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
  763.  
  764.         if (rdev->family == CHIP_R200)
  765.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  766.         else {
  767.                 if (is_tv)
  768.                         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
  769.                 else
  770.                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  771.                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  772.         }
  773.  
  774.         switch (mode) {
  775.         case DRM_MODE_DPMS_ON:
  776.                 if (rdev->family == CHIP_R200) {
  777.                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  778.                 } else {
  779.                         if (is_tv)
  780.                                 tv_master_cntl |= RADEON_TV_ON;
  781.                         else
  782.                         crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
  783.  
  784.                         if (rdev->family == CHIP_R420 ||
  785.                                         rdev->family == CHIP_R423 ||
  786.                                         rdev->family == CHIP_RV410)
  787.                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
  788.                                                 R420_TV_DAC_GDACPD |
  789.                                                 R420_TV_DAC_BDACPD |
  790.                                                 RADEON_TV_DAC_BGSLEEP);
  791.                         else
  792.                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
  793.                                                 RADEON_TV_DAC_GDACPD |
  794.                                                 RADEON_TV_DAC_BDACPD |
  795.                                                 RADEON_TV_DAC_BGSLEEP);
  796.                 }
  797.                 break;
  798.         case DRM_MODE_DPMS_STANDBY:
  799.         case DRM_MODE_DPMS_SUSPEND:
  800.         case DRM_MODE_DPMS_OFF:
  801.                 if (rdev->family == CHIP_R200)
  802.                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
  803.                 else {
  804.                         if (is_tv)
  805.                                 tv_master_cntl &= ~RADEON_TV_ON;
  806.                         else
  807.                         crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
  808.  
  809.                         if (rdev->family == CHIP_R420 ||
  810.                                         rdev->family == CHIP_R423 ||
  811.                                         rdev->family == CHIP_RV410)
  812.                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
  813.                                                 R420_TV_DAC_GDACPD |
  814.                                                 R420_TV_DAC_BDACPD |
  815.                                                 RADEON_TV_DAC_BGSLEEP);
  816.                         else
  817.                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
  818.                                                 RADEON_TV_DAC_GDACPD |
  819.                                                 RADEON_TV_DAC_BDACPD |
  820.                                                 RADEON_TV_DAC_BGSLEEP);
  821.                 }
  822.                 break;
  823.         }
  824.  
  825.         if (rdev->family == CHIP_R200) {
  826.                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  827.         } else {
  828.                 if (is_tv)
  829.                         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
  830.                 else
  831.                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  832.                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  833.         }
  834.  
  835.         if (rdev->is_atom_bios)
  836.                 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  837.         else
  838.                 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
  839. }
  840.  
  841. static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
  842. {
  843.         struct radeon_device *rdev = encoder->dev->dev_private;
  844.  
  845.         if (rdev->is_atom_bios)
  846.                 radeon_atom_output_lock(encoder, true);
  847.         else
  848.                 radeon_combios_output_lock(encoder, true);
  849.         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
  850. }
  851.  
  852. static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
  853. {
  854.         struct radeon_device *rdev = encoder->dev->dev_private;
  855.  
  856.         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
  857.  
  858.         if (rdev->is_atom_bios)
  859.                 radeon_atom_output_lock(encoder, true);
  860.         else
  861.                 radeon_combios_output_lock(encoder, true);
  862. }
  863.  
  864. static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
  865.                 struct drm_display_mode *mode,
  866.                 struct drm_display_mode *adjusted_mode)
  867. {
  868.         struct drm_device *dev = encoder->dev;
  869.         struct radeon_device *rdev = dev->dev_private;
  870.         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
  871.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  872.         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
  873.         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
  874.         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
  875.         bool is_tv = false;
  876.  
  877.         DRM_DEBUG("\n");
  878.  
  879.         is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
  880.  
  881.         if (rdev->family != CHIP_R200) {
  882.                 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  883.                 if (rdev->family == CHIP_R420 ||
  884.                                 rdev->family == CHIP_R423 ||
  885.                                 rdev->family == CHIP_RV410) {
  886.                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
  887.                                         RADEON_TV_DAC_BGADJ_MASK |
  888.                                         R420_TV_DAC_DACADJ_MASK |
  889.                                         R420_TV_DAC_RDACPD |
  890.                                         R420_TV_DAC_GDACPD |
  891.                                         R420_TV_DAC_BDACPD |
  892.                                         R420_TV_DAC_TVENABLE);
  893.                 } else {
  894.                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
  895.                                         RADEON_TV_DAC_BGADJ_MASK |
  896.                                         RADEON_TV_DAC_DACADJ_MASK |
  897.                                         RADEON_TV_DAC_RDACPD |
  898.                                         RADEON_TV_DAC_GDACPD |
  899.                                         RADEON_TV_DAC_BDACPD);
  900.                 }
  901.  
  902.                 /*  FIXME TV */
  903.                 if (tv_dac) {
  904.                         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
  905.                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
  906.                                         RADEON_TV_DAC_NHOLD |
  907.                                         RADEON_TV_DAC_STD_PS2 |
  908.                                         tv_dac->ps2_tvdac_adj);
  909.                 } else
  910.                         tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
  911.                                         RADEON_TV_DAC_NHOLD |
  912.                                         RADEON_TV_DAC_STD_PS2);
  913.  
  914.                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  915.         }
  916.  
  917.         if (ASIC_IS_R300(rdev)) {
  918.                 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
  919.                 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
  920.         }
  921.  
  922.         if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev))
  923.                 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
  924.         else
  925.                 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
  926.  
  927.         if (rdev->family == CHIP_R200)
  928.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  929.  
  930.         if (is_tv) {
  931.                 uint32_t dac_cntl;
  932.  
  933.                 dac_cntl = RREG32(RADEON_DAC_CNTL);
  934.                 dac_cntl &= ~RADEON_DAC_TVO_EN;
  935.                 WREG32(RADEON_DAC_CNTL, dac_cntl);
  936.  
  937.                 if (ASIC_IS_R300(rdev))
  938.                         gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
  939.  
  940.                 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
  941.                 if (radeon_crtc->crtc_id == 0) {
  942.                         if (ASIC_IS_R300(rdev)) {
  943.                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  944.                                 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
  945.                                                      RADEON_DISP_TV_SOURCE_CRTC);
  946.                         }
  947.                         if (rdev->family >= CHIP_R200) {
  948.                                 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
  949.                         } else {
  950.                                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
  951.                         }
  952.                 } else {
  953.                         if (ASIC_IS_R300(rdev)) {
  954.                                 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  955.                                 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
  956.                         }
  957.                         if (rdev->family >= CHIP_R200) {
  958.                                 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
  959.                         } else {
  960.                                 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
  961.                         }
  962.                 }
  963.                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  964.         } else {
  965.  
  966.         dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
  967.  
  968.         if (radeon_crtc->crtc_id == 0) {
  969.                 if (ASIC_IS_R300(rdev)) {
  970.                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  971.                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
  972.                 } else if (rdev->family == CHIP_R200) {
  973.                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
  974.                                           RADEON_FP2_DVO_RATE_SEL_SDR);
  975.                 } else
  976.                         disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
  977.         } else {
  978.                 if (ASIC_IS_R300(rdev)) {
  979.                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
  980.                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  981.                 } else if (rdev->family == CHIP_R200) {
  982.                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
  983.                                           RADEON_FP2_DVO_RATE_SEL_SDR);
  984.                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
  985.                 } else
  986.                         disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
  987.         }
  988.         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  989.         }
  990.  
  991.         if (ASIC_IS_R300(rdev)) {
  992.                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  993.                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  994.         }
  995.  
  996.         if (rdev->family >= CHIP_R200)
  997.                 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
  998.         else
  999.                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
  1000.  
  1001.         if (rdev->family == CHIP_R200)
  1002.                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  1003.  
  1004.         if (is_tv)
  1005.                 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
  1006.  
  1007.         if (rdev->is_atom_bios)
  1008.                 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  1009.         else
  1010.                 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
  1011.  
  1012. }
  1013.  
  1014. static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
  1015.                                   struct drm_connector *connector)
  1016. {
  1017.         struct drm_device *dev = encoder->dev;
  1018.         struct radeon_device *rdev = dev->dev_private;
  1019.         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
  1020.         uint32_t disp_output_cntl, gpiopad_a, tmp;
  1021.         bool found = false;
  1022.  
  1023.         /* save regs needed */
  1024.         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
  1025.         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1026.         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  1027.         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  1028.         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1029.         disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
  1030.  
  1031.         WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
  1032.  
  1033.         WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
  1034.  
  1035.         WREG32(RADEON_CRTC2_GEN_CNTL,
  1036.                RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
  1037.  
  1038.         tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1039.         tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  1040.         WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
  1041.  
  1042.         WREG32(RADEON_DAC_EXT_CNTL,
  1043.                RADEON_DAC2_FORCE_BLANK_OFF_EN |
  1044.                RADEON_DAC2_FORCE_DATA_EN |
  1045.                RADEON_DAC_FORCE_DATA_SEL_RGB |
  1046.                (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
  1047.  
  1048.         WREG32(RADEON_TV_DAC_CNTL,
  1049.                RADEON_TV_DAC_STD_NTSC |
  1050.                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
  1051.                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
  1052.  
  1053.         RREG32(RADEON_TV_DAC_CNTL);
  1054.         mdelay(4);
  1055.  
  1056.         WREG32(RADEON_TV_DAC_CNTL,
  1057.                RADEON_TV_DAC_NBLANK |
  1058.                RADEON_TV_DAC_NHOLD |
  1059.                RADEON_TV_MONITOR_DETECT_EN |
  1060.                RADEON_TV_DAC_STD_NTSC |
  1061.                (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
  1062.                (6 << RADEON_TV_DAC_DACADJ_SHIFT));
  1063.  
  1064.         RREG32(RADEON_TV_DAC_CNTL);
  1065.         mdelay(6);
  1066.  
  1067.         tmp = RREG32(RADEON_TV_DAC_CNTL);
  1068.         if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
  1069.                 found = true;
  1070.                 DRM_DEBUG("S-video TV connection detected\n");
  1071.         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
  1072.                 found = true;
  1073.                 DRM_DEBUG("Composite TV connection detected\n");
  1074.         }
  1075.  
  1076.         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1077.         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  1078.         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  1079.         WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  1080.         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1081.         WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  1082.         return found;
  1083. }
  1084.  
  1085. static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
  1086.                                     struct drm_connector *connector)
  1087. {
  1088.         struct drm_device *dev = encoder->dev;
  1089.         struct radeon_device *rdev = dev->dev_private;
  1090.         uint32_t tv_dac_cntl, dac_cntl2;
  1091.         uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
  1092.         bool found = false;
  1093.  
  1094.         if (ASIC_IS_R300(rdev))
  1095.                 return r300_legacy_tv_detect(encoder, connector);
  1096.  
  1097.         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1098.         tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
  1099.         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1100.         config_cntl = RREG32(RADEON_CONFIG_CNTL);
  1101.         tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
  1102.  
  1103.         tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
  1104.         WREG32(RADEON_DAC_CNTL2, tmp);
  1105.  
  1106.         tmp = tv_master_cntl | RADEON_TV_ON;
  1107.         tmp &= ~(RADEON_TV_ASYNC_RST |
  1108.                  RADEON_RESTART_PHASE_FIX |
  1109.                  RADEON_CRT_FIFO_CE_EN |
  1110.                  RADEON_TV_FIFO_CE_EN |
  1111.                  RADEON_RE_SYNC_NOW_SEL_MASK);
  1112.         tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
  1113.         WREG32(RADEON_TV_MASTER_CNTL, tmp);
  1114.  
  1115.         tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
  1116.                 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
  1117.                 (8 << RADEON_TV_DAC_BGADJ_SHIFT);
  1118.  
  1119.         if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
  1120.                 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
  1121.         else
  1122.                 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
  1123.         WREG32(RADEON_TV_DAC_CNTL, tmp);
  1124.  
  1125.         tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
  1126.                 RADEON_RED_MX_FORCE_DAC_DATA |
  1127.                 RADEON_GRN_MX_FORCE_DAC_DATA |
  1128.                 RADEON_BLU_MX_FORCE_DAC_DATA |
  1129.                 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
  1130.         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
  1131.  
  1132.         mdelay(3);
  1133.         tmp = RREG32(RADEON_TV_DAC_CNTL);
  1134.         if (tmp & RADEON_TV_DAC_GDACDET) {
  1135.                 found = true;
  1136.                 DRM_DEBUG("S-video TV connection detected\n");
  1137.         } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
  1138.                 found = true;
  1139.                 DRM_DEBUG("Composite TV connection detected\n");
  1140.         }
  1141.  
  1142.         WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
  1143.         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1144.         WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
  1145.         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1146.         return found;
  1147. }
  1148.  
  1149. static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
  1150.                                                              struct drm_connector *connector)
  1151. {
  1152.         struct drm_device *dev = encoder->dev;
  1153.         struct radeon_device *rdev = dev->dev_private;
  1154.         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
  1155.         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
  1156.         enum drm_connector_status found = connector_status_disconnected;
  1157.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  1158.         struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
  1159.         bool color = true;
  1160.  
  1161.         if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
  1162.             connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
  1163.             connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
  1164.                 bool tv_detect;
  1165.  
  1166.                 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
  1167.                         return connector_status_disconnected;
  1168.  
  1169.                 tv_detect = radeon_legacy_tv_detect(encoder, connector);
  1170.                 if (tv_detect && tv_dac)
  1171.                         found = connector_status_connected;
  1172.                 return found;
  1173.         }
  1174.  
  1175.         /* don't probe if the encoder is being used for something else not CRT related */
  1176.         if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
  1177.                 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
  1178.                 return connector_status_disconnected;
  1179.         }
  1180.  
  1181.         /* save the regs we need */
  1182.         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
  1183.         gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
  1184.         disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
  1185.         disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
  1186.         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  1187.         tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  1188.         dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
  1189.         dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
  1190.  
  1191.         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
  1192.                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
  1193.         WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
  1194.  
  1195.         if (ASIC_IS_R300(rdev))
  1196.                 WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
  1197.  
  1198.         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
  1199.         tmp |= RADEON_CRTC2_CRT2_ON |
  1200.                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
  1201.  
  1202.         WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
  1203.  
  1204.         if (ASIC_IS_R300(rdev)) {
  1205.                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
  1206.                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
  1207.                 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
  1208.         } else {
  1209.                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
  1210.                 WREG32(RADEON_DISP_HW_DEBUG, tmp);
  1211.         }
  1212.  
  1213.         tmp = RADEON_TV_DAC_NBLANK |
  1214.                 RADEON_TV_DAC_NHOLD |
  1215.                 RADEON_TV_MONITOR_DETECT_EN |
  1216.                 RADEON_TV_DAC_STD_PS2;
  1217.  
  1218.         WREG32(RADEON_TV_DAC_CNTL, tmp);
  1219.  
  1220.         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
  1221.                 RADEON_DAC2_FORCE_DATA_EN;
  1222.  
  1223.         if (color)
  1224.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
  1225.         else
  1226.                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
  1227.  
  1228.         if (ASIC_IS_R300(rdev))
  1229.                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
  1230.         else
  1231.                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
  1232.  
  1233.         WREG32(RADEON_DAC_EXT_CNTL, tmp);
  1234.  
  1235.         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
  1236.         WREG32(RADEON_DAC_CNTL2, tmp);
  1237.  
  1238.         udelay(10000);
  1239.  
  1240.         if (ASIC_IS_R300(rdev)) {
  1241.                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
  1242.                         found = connector_status_connected;
  1243.         } else {
  1244.                 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
  1245.                         found = connector_status_connected;
  1246.         }
  1247.  
  1248.         /* restore regs we used */
  1249.         WREG32(RADEON_DAC_CNTL2, dac_cntl2);
  1250.         WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
  1251.         WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  1252.         WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  1253.  
  1254.         if (ASIC_IS_R300(rdev)) {
  1255.                 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
  1256.                 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
  1257.         } else {
  1258.                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
  1259.         }
  1260.         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
  1261.  
  1262.         return found;
  1263.  
  1264. }
  1265.  
  1266. static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
  1267.         .dpms = radeon_legacy_tv_dac_dpms,
  1268.         .mode_fixup = radeon_legacy_tv_dac_mode_fixup,
  1269.         .prepare = radeon_legacy_tv_dac_prepare,
  1270.         .mode_set = radeon_legacy_tv_dac_mode_set,
  1271.         .commit = radeon_legacy_tv_dac_commit,
  1272.         .detect = radeon_legacy_tv_dac_detect,
  1273.         .disable = radeon_legacy_encoder_disable,
  1274. };
  1275.  
  1276.  
  1277. static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
  1278.         .destroy = radeon_enc_destroy,
  1279. };
  1280.  
  1281.  
  1282. static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
  1283. {
  1284.         struct drm_device *dev = encoder->base.dev;
  1285.         struct radeon_device *rdev = dev->dev_private;
  1286.         struct radeon_encoder_int_tmds *tmds = NULL;
  1287.         bool ret;
  1288.  
  1289.         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
  1290.  
  1291.         if (!tmds)
  1292.                 return NULL;
  1293.  
  1294.         if (rdev->is_atom_bios)
  1295.                 ret = radeon_atombios_get_tmds_info(encoder, tmds);
  1296.         else
  1297.                 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
  1298.  
  1299.         if (ret == false)
  1300.                 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
  1301.  
  1302.         return tmds;
  1303. }
  1304.  
  1305. void
  1306. radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
  1307. {
  1308.         struct radeon_device *rdev = dev->dev_private;
  1309.         struct drm_encoder *encoder;
  1310.         struct radeon_encoder *radeon_encoder;
  1311.  
  1312.         /* see if we already added it */
  1313.         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1314.                 radeon_encoder = to_radeon_encoder(encoder);
  1315.                 if (radeon_encoder->encoder_id == encoder_id) {
  1316.                         radeon_encoder->devices |= supported_device;
  1317.                         return;
  1318.                 }
  1319.  
  1320.         }
  1321.  
  1322.         /* add a new one */
  1323.         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
  1324.         if (!radeon_encoder)
  1325.                 return;
  1326.  
  1327.         encoder = &radeon_encoder->base;
  1328.         if (rdev->flags & RADEON_SINGLE_CRTC)
  1329.                 encoder->possible_crtcs = 0x1;
  1330.         else
  1331.         encoder->possible_crtcs = 0x3;
  1332.         encoder->possible_clones = 0;
  1333.  
  1334.         radeon_encoder->enc_priv = NULL;
  1335.  
  1336.         radeon_encoder->encoder_id = encoder_id;
  1337.         radeon_encoder->devices = supported_device;
  1338.         radeon_encoder->rmx_type = RMX_OFF;
  1339.  
  1340.         switch (radeon_encoder->encoder_id) {
  1341.         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
  1342.                 encoder->possible_crtcs = 0x1;
  1343.                 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
  1344.                 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
  1345.                 if (rdev->is_atom_bios)
  1346.                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
  1347.                 else
  1348.                         radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
  1349.                 radeon_encoder->rmx_type = RMX_FULL;
  1350.                 break;
  1351.         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
  1352.                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
  1353.                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
  1354.                 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
  1355.                 break;
  1356.         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
  1357.                 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
  1358.                 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
  1359.                 if (rdev->is_atom_bios)
  1360.                         radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
  1361.                 else
  1362.                         radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
  1363.                 break;
  1364.         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
  1365.                 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
  1366.                 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
  1367.                 if (rdev->is_atom_bios)
  1368.                         radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
  1369.                 else
  1370.                         radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
  1371.                 break;
  1372.         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
  1373.                 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
  1374.                 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
  1375.                 if (!rdev->is_atom_bios)
  1376.                         radeon_combios_get_ext_tmds_info(radeon_encoder);
  1377.                 break;
  1378.         }
  1379. }
  1380.