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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. //#include <linux/console.h>
  29.  
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/radeon_drm.h>
  33. #include "radeon_reg.h"
  34. #include "radeon.h"
  35. #include "radeon_asic.h"
  36. #include "atom.h"
  37.  
  38. #include <drm/drm_pciids.h>
  39.  
  40.  
  41. int radeon_dynclks          = -1;
  42. int radeon_r4xx_atom        = 0;
  43. int radeon_agpmode          = -1;
  44. int radeon_gart_size        = 512; /* default gart size */
  45. int radeon_benchmarking     = 0;
  46. int radeon_connector_table  = 0;
  47. int radeon_tv               = 0;
  48. int radeon_modeset          = 1;
  49.  
  50. void parse_cmdline(char *cmdline, mode_t *mode, char *log, int *kms);
  51. int init_display(struct radeon_device *rdev, mode_t *mode);
  52. int init_display_kms(struct radeon_device *rdev, mode_t *mode);
  53.  
  54. int get_modes(mode_t *mode, int *count);
  55. int set_user_mode(mode_t *mode);
  56.  
  57.  
  58.  /* Legacy VGA regions */
  59. #define VGA_RSRC_NONE          0x00
  60. #define VGA_RSRC_LEGACY_IO     0x01
  61. #define VGA_RSRC_LEGACY_MEM    0x02
  62. #define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
  63. /* Non-legacy access */
  64. #define VGA_RSRC_NORMAL_IO     0x04
  65. #define VGA_RSRC_NORMAL_MEM    0x08
  66.  
  67.  
  68.  
  69. /*
  70.  * Clear GPU surface registers.
  71.  */
  72. void radeon_surface_init(struct radeon_device *rdev)
  73. {
  74.     ENTER();
  75.  
  76.     /* FIXME: check this out */
  77.     if (rdev->family < CHIP_R600) {
  78.         int i;
  79.  
  80.                 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
  81.                         if (rdev->surface_regs[i].bo)
  82.                                 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
  83.                         else
  84.                                 radeon_clear_surface_reg(rdev, i);
  85.         }
  86.                 /* enable surfaces */
  87.                 WREG32(RADEON_SURFACE_CNTL, 0);
  88.     }
  89. }
  90.  
  91. /*
  92.  * GPU scratch registers helpers function.
  93.  */
  94. void radeon_scratch_init(struct radeon_device *rdev)
  95. {
  96.     int i;
  97.  
  98.     /* FIXME: check this out */
  99.     if (rdev->family < CHIP_R300) {
  100.         rdev->scratch.num_reg = 5;
  101.     } else {
  102.         rdev->scratch.num_reg = 7;
  103.     }
  104.     for (i = 0; i < rdev->scratch.num_reg; i++) {
  105.         rdev->scratch.free[i] = true;
  106.         rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
  107.     }
  108. }
  109.  
  110. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  111. {
  112.         int i;
  113.  
  114.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  115.                 if (rdev->scratch.free[i]) {
  116.                         rdev->scratch.free[i] = false;
  117.                         *reg = rdev->scratch.reg[i];
  118.                         return 0;
  119.                 }
  120.         }
  121.         return -EINVAL;
  122. }
  123.  
  124. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  125. {
  126.         int i;
  127.  
  128.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  129.                 if (rdev->scratch.reg[i] == reg) {
  130.                         rdev->scratch.free[i] = true;
  131.                         return;
  132.                 }
  133.         }
  134. }
  135.  
  136. /*
  137.  * MC common functions
  138.  */
  139. int radeon_mc_setup(struct radeon_device *rdev)
  140. {
  141.         uint32_t tmp;
  142.  
  143.         /* Some chips have an "issue" with the memory controller, the
  144.          * location must be aligned to the size. We just align it down,
  145.          * too bad if we walk over the top of system memory, we don't
  146.          * use DMA without a remapped anyway.
  147.          * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
  148.          */
  149.         /* FGLRX seems to setup like this, VRAM a 0, then GART.
  150.          */
  151.         /*
  152.          * Note: from R6xx the address space is 40bits but here we only
  153.          * use 32bits (still have to see a card which would exhaust 4G
  154.          * address space).
  155.          */
  156.         if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
  157.                 /* vram location was already setup try to put gtt after
  158.                  * if it fits */
  159.                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
  160.                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
  161.                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
  162.                         rdev->mc.gtt_location = tmp;
  163.                 } else {
  164.                         if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
  165.                                 printk(KERN_ERR "[drm] GTT too big to fit "
  166.                                        "before or after vram location.\n");
  167.                                 return -EINVAL;
  168.                         }
  169.                         rdev->mc.gtt_location = 0;
  170.                 }
  171.         } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
  172.                 /* gtt location was already setup try to put vram before
  173.                  * if it fits */
  174.                 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
  175.                         rdev->mc.vram_location = 0;
  176.                 } else {
  177.                         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
  178.                         tmp += (rdev->mc.mc_vram_size - 1);
  179.                         tmp &= ~(rdev->mc.mc_vram_size - 1);
  180.                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
  181.                                 rdev->mc.vram_location = tmp;
  182.                         } else {
  183.                                 printk(KERN_ERR "[drm] vram too big to fit "
  184.                                        "before or after GTT location.\n");
  185.                                 return -EINVAL;
  186.                         }
  187.                 }
  188.         } else {
  189.                 rdev->mc.vram_location = 0;
  190.                 tmp = rdev->mc.mc_vram_size;
  191.                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
  192.                 rdev->mc.gtt_location = tmp;
  193.         }
  194.         rdev->mc.vram_start = rdev->mc.vram_location;
  195.         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
  196.         rdev->mc.gtt_start = rdev->mc.gtt_location;
  197.         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  198.         DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
  199.         DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
  200.                  (unsigned)rdev->mc.vram_location,
  201.                  (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
  202.         DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
  203.         DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
  204.                  (unsigned)rdev->mc.gtt_location,
  205.                  (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
  206.         return 0;
  207. }
  208.  
  209.  
  210. /*
  211.  * GPU helpers function.
  212.  */
  213. bool radeon_card_posted(struct radeon_device *rdev)
  214. {
  215.         uint32_t reg;
  216.  
  217.         /* first check CRTCs */
  218.         if (ASIC_IS_AVIVO(rdev)) {
  219.                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
  220.                       RREG32(AVIVO_D2CRTC_CONTROL);
  221.                 if (reg & AVIVO_CRTC_EN) {
  222.                         return true;
  223.                 }
  224.         } else {
  225.                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
  226.                       RREG32(RADEON_CRTC2_GEN_CNTL);
  227.                 if (reg & RADEON_CRTC_EN) {
  228.                         return true;
  229.                 }
  230.         }
  231.  
  232.         /* then check MEM_SIZE, in case the crtcs are off */
  233.         if (rdev->family >= CHIP_R600)
  234.                 reg = RREG32(R600_CONFIG_MEMSIZE);
  235.         else
  236.                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
  237.  
  238.         if (reg)
  239.                 return true;
  240.  
  241.         return false;
  242.  
  243. }
  244.  
  245. bool radeon_boot_test_post_card(struct radeon_device *rdev)
  246. {
  247.         if (radeon_card_posted(rdev))
  248.                 return true;
  249.  
  250.         if (rdev->bios) {
  251.                 DRM_INFO("GPU not posted. posting now...\n");
  252.                 if (rdev->is_atom_bios)
  253.                         atom_asic_init(rdev->mode_info.atom_context);
  254.                 else
  255.                         radeon_combios_asic_init(rdev->ddev);
  256.                 return true;
  257.         } else {
  258.                 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
  259.                 return false;
  260.         }
  261. }
  262.  
  263. int radeon_dummy_page_init(struct radeon_device *rdev)
  264. {
  265.     rdev->dummy_page.page = AllocPage();
  266.         if (rdev->dummy_page.page == NULL)
  267.                 return -ENOMEM;
  268.     rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);
  269.         if (!rdev->dummy_page.addr) {
  270. //       __free_page(rdev->dummy_page.page);
  271.                 rdev->dummy_page.page = NULL;
  272.                 return -ENOMEM;
  273.         }
  274.         return 0;
  275. }
  276.  
  277. void radeon_dummy_page_fini(struct radeon_device *rdev)
  278. {
  279.         if (rdev->dummy_page.page == NULL)
  280.                 return;
  281.     KernelFree(rdev->dummy_page.addr);
  282.         rdev->dummy_page.page = NULL;
  283. }
  284.  
  285.  
  286. /*
  287.  * Registers accessors functions.
  288.  */
  289. uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  290. {
  291.     DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  292.     BUG_ON(1);
  293.     return 0;
  294. }
  295.  
  296. void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  297. {
  298.     DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  299.           reg, v);
  300.     BUG_ON(1);
  301. }
  302.  
  303. void radeon_register_accessor_init(struct radeon_device *rdev)
  304. {
  305.     rdev->mc_rreg = &radeon_invalid_rreg;
  306.     rdev->mc_wreg = &radeon_invalid_wreg;
  307.     rdev->pll_rreg = &radeon_invalid_rreg;
  308.     rdev->pll_wreg = &radeon_invalid_wreg;
  309.     rdev->pciep_rreg = &radeon_invalid_rreg;
  310.     rdev->pciep_wreg = &radeon_invalid_wreg;
  311.  
  312.     /* Don't change order as we are overridding accessor. */
  313.     if (rdev->family < CHIP_RV515) {
  314.                 rdev->pcie_reg_mask = 0xff;
  315.         } else {
  316.                 rdev->pcie_reg_mask = 0x7ff;
  317.     }
  318.     /* FIXME: not sure here */
  319.     if (rdev->family <= CHIP_R580) {
  320.         rdev->pll_rreg = &r100_pll_rreg;
  321.         rdev->pll_wreg = &r100_pll_wreg;
  322.     }
  323.         if (rdev->family >= CHIP_R420) {
  324.                 rdev->mc_rreg = &r420_mc_rreg;
  325.                 rdev->mc_wreg = &r420_mc_wreg;
  326.         }
  327.     if (rdev->family >= CHIP_RV515) {
  328.         rdev->mc_rreg = &rv515_mc_rreg;
  329.         rdev->mc_wreg = &rv515_mc_wreg;
  330.     }
  331.     if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  332.         rdev->mc_rreg = &rs400_mc_rreg;
  333.         rdev->mc_wreg = &rs400_mc_wreg;
  334.     }
  335.     if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  336.         rdev->mc_rreg = &rs690_mc_rreg;
  337.         rdev->mc_wreg = &rs690_mc_wreg;
  338.     }
  339.     if (rdev->family == CHIP_RS600) {
  340.         rdev->mc_rreg = &rs600_mc_rreg;
  341.         rdev->mc_wreg = &rs600_mc_wreg;
  342.     }
  343.         if (rdev->family >= CHIP_R600) {
  344.                 rdev->pciep_rreg = &r600_pciep_rreg;
  345.                 rdev->pciep_wreg = &r600_pciep_wreg;
  346.         }
  347. }
  348.  
  349.  
  350. /*
  351.  * ASIC
  352.  */
  353. int radeon_asic_init(struct radeon_device *rdev)
  354. {
  355.     radeon_register_accessor_init(rdev);
  356.         switch (rdev->family) {
  357.         case CHIP_R100:
  358.         case CHIP_RV100:
  359.         case CHIP_RS100:
  360.         case CHIP_RV200:
  361.         case CHIP_RS200:
  362.         case CHIP_R200:
  363.         case CHIP_RV250:
  364.         case CHIP_RS300:
  365.         case CHIP_RV280:
  366.         rdev->asic = &r100_asic;
  367.                 break;
  368.         case CHIP_R300:
  369.         case CHIP_R350:
  370.         case CHIP_RV350:
  371.         case CHIP_RV380:
  372.         rdev->asic = &r300_asic;
  373.                 if (rdev->flags & RADEON_IS_PCIE) {
  374.                         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
  375.                         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
  376.                 }
  377.                 break;
  378.         case CHIP_R420:
  379.         case CHIP_R423:
  380.         case CHIP_RV410:
  381.         rdev->asic = &r420_asic;
  382.                 break;
  383.         case CHIP_RS400:
  384.         case CHIP_RS480:
  385.        rdev->asic = &rs400_asic;
  386.                 break;
  387.         case CHIP_RS600:
  388.         rdev->asic = &rs600_asic;
  389.                 break;
  390.         case CHIP_RS690:
  391.         case CHIP_RS740:
  392.         rdev->asic = &rs690_asic;
  393.                 break;
  394.         case CHIP_RV515:
  395.         rdev->asic = &rv515_asic;
  396.                 break;
  397.         case CHIP_R520:
  398.         case CHIP_RV530:
  399.         case CHIP_RV560:
  400.         case CHIP_RV570:
  401.         case CHIP_R580:
  402.         rdev->asic = &r520_asic;
  403.                 break;
  404.         case CHIP_R600:
  405.         case CHIP_RV610:
  406.         case CHIP_RV630:
  407.         case CHIP_RV620:
  408.         case CHIP_RV635:
  409.         case CHIP_RV670:
  410.         case CHIP_RS780:
  411.         case CHIP_RS880:
  412.                 rdev->asic = &r600_asic;
  413.                 break;
  414.         case CHIP_RV770:
  415.         case CHIP_RV730:
  416.         case CHIP_RV710:
  417.         case CHIP_RV740:
  418.                 rdev->asic = &rv770_asic;
  419.                 break;
  420.         default:
  421.                 /* FIXME: not supported yet */
  422.                 return -EINVAL;
  423.         }
  424.         return 0;
  425. }
  426.  
  427.  
  428. /*
  429.  * Wrapper around modesetting bits.
  430.  */
  431. int radeon_clocks_init(struct radeon_device *rdev)
  432. {
  433.         int r;
  434.  
  435.     r = radeon_static_clocks_init(rdev->ddev);
  436.         if (r) {
  437.                 return r;
  438.         }
  439.         DRM_INFO("Clocks initialized !\n");
  440.         return 0;
  441. }
  442.  
  443. void radeon_clocks_fini(struct radeon_device *rdev)
  444. {
  445. }
  446.  
  447. /* ATOM accessor methods */
  448. static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
  449. {
  450.     struct radeon_device *rdev = info->dev->dev_private;
  451.     uint32_t r;
  452.  
  453.     r = rdev->pll_rreg(rdev, reg);
  454.     return r;
  455. }
  456.  
  457. static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
  458. {
  459.     struct radeon_device *rdev = info->dev->dev_private;
  460.  
  461.     rdev->pll_wreg(rdev, reg, val);
  462. }
  463.  
  464. static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
  465. {
  466.     struct radeon_device *rdev = info->dev->dev_private;
  467.     uint32_t r;
  468.  
  469.     r = rdev->mc_rreg(rdev, reg);
  470.     return r;
  471. }
  472.  
  473. static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
  474. {
  475.     struct radeon_device *rdev = info->dev->dev_private;
  476.  
  477.     rdev->mc_wreg(rdev, reg, val);
  478. }
  479.  
  480. static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
  481. {
  482.     struct radeon_device *rdev = info->dev->dev_private;
  483.  
  484.     WREG32(reg*4, val);
  485. }
  486.  
  487. static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
  488. {
  489.     struct radeon_device *rdev = info->dev->dev_private;
  490.     uint32_t r;
  491.  
  492.     r = RREG32(reg*4);
  493.     return r;
  494. }
  495.  
  496. int radeon_atombios_init(struct radeon_device *rdev)
  497. {
  498.         struct card_info *atom_card_info =
  499.             kzalloc(sizeof(struct card_info), GFP_KERNEL);
  500.  
  501.         if (!atom_card_info)
  502.                 return -ENOMEM;
  503.  
  504.         rdev->mode_info.atom_card_info = atom_card_info;
  505.         atom_card_info->dev = rdev->ddev;
  506.         atom_card_info->reg_read = cail_reg_read;
  507.         atom_card_info->reg_write = cail_reg_write;
  508.         atom_card_info->mc_read = cail_mc_read;
  509.         atom_card_info->mc_write = cail_mc_write;
  510.         atom_card_info->pll_read = cail_pll_read;
  511.         atom_card_info->pll_write = cail_pll_write;
  512.  
  513.         rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
  514.     radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
  515.         atom_allocate_fb_scratch(rdev->mode_info.atom_context);
  516.     return 0;
  517. }
  518.  
  519. void radeon_atombios_fini(struct radeon_device *rdev)
  520. {
  521.         if (rdev->mode_info.atom_context) {
  522.                 kfree(rdev->mode_info.atom_context->scratch);
  523.         kfree(rdev->mode_info.atom_context);
  524.         }
  525.         kfree(rdev->mode_info.atom_card_info);
  526. }
  527.  
  528. int radeon_combios_init(struct radeon_device *rdev)
  529. {
  530.         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
  531.         return 0;
  532. }
  533.  
  534. void radeon_combios_fini(struct radeon_device *rdev)
  535. {
  536. }
  537.  
  538. /* if we get transitioned to only one device, tak VGA back */
  539. static unsigned int radeon_vga_set_decode(void *cookie, bool state)
  540. {
  541.         struct radeon_device *rdev = cookie;
  542.         radeon_vga_set_state(rdev, state);
  543.         if (state)
  544.                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
  545.                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  546.         else
  547.                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
  548. }
  549.  
  550. void radeon_agp_disable(struct radeon_device *rdev)
  551. {
  552.         rdev->flags &= ~RADEON_IS_AGP;
  553.         if (rdev->family >= CHIP_R600) {
  554.                 DRM_INFO("Forcing AGP to PCIE mode\n");
  555.                 rdev->flags |= RADEON_IS_PCIE;
  556.         } else if (rdev->family >= CHIP_RV515 ||
  557.                         rdev->family == CHIP_RV380 ||
  558.                         rdev->family == CHIP_RV410 ||
  559.                         rdev->family == CHIP_R423) {
  560.                 DRM_INFO("Forcing AGP to PCIE mode\n");
  561.                 rdev->flags |= RADEON_IS_PCIE;
  562.                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
  563.                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
  564.         } else {
  565.                 DRM_INFO("Forcing AGP to PCI mode\n");
  566.                 rdev->flags |= RADEON_IS_PCI;
  567.                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
  568.                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
  569.         }
  570. }
  571.  
  572. /*
  573.  * Radeon device.
  574.  */
  575. int radeon_device_init(struct radeon_device *rdev,
  576.                struct drm_device *ddev,
  577.                struct pci_dev *pdev,
  578.                uint32_t flags)
  579. {
  580.         int r;
  581.         int dma_bits;
  582.  
  583.     DRM_INFO("radeon: Initializing kernel modesetting.\n");
  584.     rdev->shutdown = false;
  585.     rdev->ddev = ddev;
  586.     rdev->pdev = pdev;
  587.     rdev->flags = flags;
  588.     rdev->family = flags & RADEON_FAMILY_MASK;
  589.     rdev->is_atom_bios = false;
  590.     rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
  591.     rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  592.     rdev->gpu_lockup = false;
  593.         rdev->accel_working = false;
  594.     /* mutex initialization are all done here so we
  595.      * can recall function without having locking issues */
  596.  //   mutex_init(&rdev->cs_mutex);
  597.  //   mutex_init(&rdev->ib_pool.mutex);
  598.  //   mutex_init(&rdev->cp.mutex);
  599.  //   rwlock_init(&rdev->fence_drv.lock);
  600.  
  601.         /* Set asic functions */
  602.         r = radeon_asic_init(rdev);
  603.         if (r) {
  604.                 return r;
  605.         }
  606.  
  607.         if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
  608.                 radeon_agp_disable(rdev);
  609.     }
  610.  
  611.         /* set DMA mask + need_dma32 flags.
  612.          * PCIE - can handle 40-bits.
  613.          * IGP - can handle 40-bits (in theory)
  614.          * AGP - generally dma32 is safest
  615.          * PCI - only dma32
  616.          */
  617.         rdev->need_dma32 = false;
  618.         if (rdev->flags & RADEON_IS_AGP)
  619.                 rdev->need_dma32 = true;
  620.         if (rdev->flags & RADEON_IS_PCI)
  621.                 rdev->need_dma32 = true;
  622.  
  623.         dma_bits = rdev->need_dma32 ? 32 : 40;
  624.         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
  625.     if (r) {
  626.         printk(KERN_WARNING "radeon: No suitable DMA available.\n");
  627.     }
  628.  
  629.     /* Registers mapping */
  630.     /* TODO: block userspace mapping of io register */
  631.     rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
  632.  
  633.     rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
  634.  
  635.     rdev->rmmio =  (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
  636.                                    PG_SW+PG_NOCACHE);
  637.  
  638.     if (rdev->rmmio == NULL) {
  639.         return -ENOMEM;
  640.     }
  641.     DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
  642.     DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
  643.  
  644.         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
  645. //      r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
  646. //      if (r) {
  647. //              return -EINVAL;
  648. //      }
  649.  
  650.         r = radeon_init(rdev);
  651.         if (r)
  652.             return r;
  653.  
  654.         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
  655.                 /* Acceleration not working on AGP card try again
  656.                  * with fallback to PCI or PCIE GART
  657.                  */
  658.                 radeon_gpu_reset(rdev);
  659.                 radeon_fini(rdev);
  660.                 radeon_agp_disable(rdev);
  661.                 r = radeon_init(rdev);
  662.                 if (r)
  663.                 return r;
  664.         }
  665. //      if (radeon_testing) {
  666. //              radeon_test_moves(rdev);
  667. //    }
  668. //      if (radeon_benchmarking) {
  669. //              radeon_benchmark(rdev);
  670. //    }
  671.         return 0;
  672. }
  673.  
  674.  
  675. /*
  676.  * Driver load/unload
  677.  */
  678. int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  679. {
  680.     struct radeon_device *rdev;
  681.     int r;
  682.  
  683.     ENTER();
  684.  
  685.     rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  686.     if (rdev == NULL) {
  687.         return -ENOMEM;
  688.     };
  689.  
  690.     dev->dev_private = (void *)rdev;
  691.  
  692.     /* update BUS flag */
  693.     if (drm_device_is_agp(dev)) {
  694.         flags |= RADEON_IS_AGP;
  695.     } else if (drm_device_is_pcie(dev)) {
  696.         flags |= RADEON_IS_PCIE;
  697.     } else {
  698.         flags |= RADEON_IS_PCI;
  699.     }
  700.  
  701.     /* radeon_device_init should report only fatal error
  702.      * like memory allocation failure or iomapping failure,
  703.      * or memory manager initialization failure, it must
  704.      * properly initialize the GPU MC controller and permit
  705.      * VRAM allocation
  706.      */
  707.     r = radeon_device_init(rdev, dev, dev->pdev, flags);
  708.     if (r) {
  709.         DRM_ERROR("Fatal error while trying to initialize radeon.\n");
  710.         return r;
  711.     }
  712.     /* Again modeset_init should fail only on fatal error
  713.      * otherwise it should provide enough functionalities
  714.      * for shadowfb to run
  715.      */
  716.     if( radeon_modeset )
  717.     {
  718.         r = radeon_modeset_init(rdev);
  719.         if (r) {
  720.             return r;
  721.         }
  722.     };
  723.     return 0;
  724. }
  725.  
  726. mode_t usermode;
  727.  
  728.  
  729. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  730. {
  731.     static struct drm_device *dev;
  732.     int ret;
  733.  
  734.     ENTER();
  735.  
  736.     dev = kzalloc(sizeof(*dev), 0);
  737.     if (!dev)
  738.         return -ENOMEM;
  739.  
  740.  //   ret = pci_enable_device(pdev);
  741.  //   if (ret)
  742.  //       goto err_g1;
  743.  
  744.  //   pci_set_master(pdev);
  745.  
  746.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  747.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  748.  //       goto err_g2;
  749.  //   }
  750.  
  751.     dev->pdev = pdev;
  752.     dev->pci_device = pdev->device;
  753.     dev->pci_vendor = pdev->vendor;
  754.  
  755.     ret = radeon_driver_load_kms(dev, ent->driver_data );
  756.     if (ret)
  757.         goto err_g4;
  758.  
  759.  //   list_add_tail(&dev->driver_item, &driver->device_list);
  760.  
  761.  //   DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
  762.  //        driver->name, driver->major, driver->minor, driver->patchlevel,
  763.  //        driver->date, pci_name(pdev), dev->primary->index);
  764.  
  765.     if( radeon_modeset )
  766.         init_display_kms(dev->dev_private, &usermode);
  767.     else
  768.         init_display(dev->dev_private, &usermode);
  769.  
  770.     LEAVE();
  771.  
  772.     return 0;
  773.  
  774. err_g4:
  775. //    drm_put_minor(&dev->primary);
  776. //err_g3:
  777. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  778. //        drm_put_minor(&dev->control);
  779. //err_g2:
  780. //    pci_disable_device(pdev);
  781. //err_g1:
  782.     free(dev);
  783.  
  784.     LEAVE();
  785.  
  786.     return ret;
  787. }
  788.  
  789. resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
  790. {
  791.     return pci_resource_start(dev->pdev, resource);
  792. }
  793.  
  794. resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
  795. {
  796.     return pci_resource_len(dev->pdev, resource);
  797. }
  798.  
  799.  
  800. uint32_t __div64_32(uint64_t *n, uint32_t base)
  801. {
  802.         uint64_t rem = *n;
  803.         uint64_t b = base;
  804.         uint64_t res, d = 1;
  805.         uint32_t high = rem >> 32;
  806.  
  807.         /* Reduce the thing a bit first */
  808.         res = 0;
  809.         if (high >= base) {
  810.                 high /= base;
  811.                 res = (uint64_t) high << 32;
  812.                 rem -= (uint64_t) (high*base) << 32;
  813.         }
  814.  
  815.         while ((int64_t)b > 0 && b < rem) {
  816.                 b = b+b;
  817.                 d = d+d;
  818.         }
  819.  
  820.         do {
  821.                 if (rem >= b) {
  822.                         rem -= b;
  823.                         res += d;
  824.                 }
  825.                 b >>= 1;
  826.                 d >>= 1;
  827.         } while (d);
  828.  
  829.         *n = res;
  830.         return rem;
  831. }
  832.  
  833.  
  834. static struct pci_device_id pciidlist[] = {
  835.     radeon_PCI_IDS
  836. };
  837.  
  838.  
  839. #define API_VERSION     0x01000100
  840.  
  841. #define SRV_GETVERSION  0
  842. #define SRV_ENUM_MODES  1
  843. #define SRV_SET_MODE    2
  844.  
  845. int _stdcall display_handler(ioctl_t *io)
  846. {
  847.     int    retval = -1;
  848.     u32_t *inp;
  849.     u32_t *outp;
  850.  
  851.     inp = io->input;
  852.     outp = io->output;
  853.  
  854.     switch(io->io_code)
  855.     {
  856.         case SRV_GETVERSION:
  857.             if(io->out_size==4)
  858.             {
  859.                 *outp  = API_VERSION;
  860.                 retval = 0;
  861.             }
  862.             break;
  863.  
  864.         case SRV_ENUM_MODES:
  865.             dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
  866.                        inp, io->inp_size, io->out_size );
  867.  
  868.             if( radeon_modeset &&
  869.                 (outp != NULL) && (io->out_size == 4) &&
  870.                 (io->inp_size == *outp * sizeof(mode_t)) )
  871.             {
  872.                 retval = get_modes((mode_t*)inp, outp);
  873.             };
  874.             break;
  875.  
  876.         case SRV_SET_MODE:
  877.             dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
  878.                        inp, io->inp_size);
  879.  
  880.             if(  radeon_modeset   &&
  881.                 (inp != NULL) &&
  882.                 (io->inp_size == sizeof(mode_t)) )
  883.             {
  884.                 retval = set_user_mode((mode_t*)inp);
  885.             };
  886.             break;
  887.     };
  888.  
  889.     return retval;
  890. }
  891.  
  892. static char  log[256];
  893. static dev_t device;
  894.  
  895. u32_t drvEntry(int action, char *cmdline)
  896. {
  897.     struct pci_device_id  *ent;
  898.  
  899.     int     err;
  900.     u32_t   retval = 0;
  901.  
  902.     if(action != 1)
  903.         return 0;
  904.  
  905.     if( GetService("DISPLAY") != 0 )
  906.         return 0;
  907.  
  908.     if( cmdline && *cmdline )
  909.         parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
  910.  
  911.     if(!dbg_open(log))
  912.     {
  913.         strcpy(log, "/rd/1/drivers/atikms.log");
  914.  
  915.         if(!dbg_open(log))
  916.         {
  917.             printf("Can't open %s\nExit\n", log);
  918.             return 0;
  919.         };
  920.     }
  921.     dbgprintf("Radeon RC09 cmdline %s\n", cmdline);
  922.  
  923.     enum_pci_devices();
  924.  
  925.     ent = find_pci_device(&device, pciidlist);
  926.  
  927.     if( unlikely(ent == NULL) )
  928.     {
  929.         dbgprintf("device not found\n");
  930.         return 0;
  931.     };
  932.  
  933.     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
  934.                                 device.pci_dev.device);
  935.  
  936.     err = drm_get_dev(&device.pci_dev, ent);
  937.  
  938.     err = RegService("DISPLAY", display_handler);
  939.  
  940.     if( err != 0)
  941.         dbgprintf("Set DISPLAY handler\n");
  942.  
  943.     return err;
  944. };
  945.