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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. //#include <linux/console.h>
  29.  
  30. #include <drm/drmP.h>
  31. #include <drm/drm_crtc_helper.h>
  32. #include <drm/radeon_drm.h>
  33. #include "radeon_reg.h"
  34. #include "radeon.h"
  35. #include "radeon_asic.h"
  36. #include "atom.h"
  37.  
  38. #include <drm/drm_pciids.h>
  39.  
  40. #include <syscall.h>
  41.  
  42. int radeon_dynclks = -1;
  43. int radeon_r4xx_atom = 0;
  44. int radeon_agpmode   = -1;
  45. int radeon_gart_size = 512; /* default gart size */
  46. int radeon_benchmarking = 0;
  47. int radeon_connector_table = 0;
  48. int radeon_tv = 0;
  49.  
  50. int pre_init_display(struct radeon_device *rdev);
  51. int post_init_display(struct radeon_device *rdev);
  52.  
  53. /*
  54.  * Clear GPU surface registers.
  55.  */
  56. void radeon_surface_init(struct radeon_device *rdev)
  57. {
  58.     ENTER();
  59.  
  60.     /* FIXME: check this out */
  61.     if (rdev->family < CHIP_R600) {
  62.         int i;
  63.  
  64.         for (i = 0; i < 8; i++) {
  65.             WREG32(RADEON_SURFACE0_INFO +
  66.                    i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
  67.                    0);
  68.         }
  69.                 /* enable surfaces */
  70.                 WREG32(RADEON_SURFACE_CNTL, 0);
  71.     }
  72. }
  73.  
  74. /*
  75.  * GPU scratch registers helpers function.
  76.  */
  77. void radeon_scratch_init(struct radeon_device *rdev)
  78. {
  79.     int i;
  80.  
  81.     /* FIXME: check this out */
  82.     if (rdev->family < CHIP_R300) {
  83.         rdev->scratch.num_reg = 5;
  84.     } else {
  85.         rdev->scratch.num_reg = 7;
  86.     }
  87.     for (i = 0; i < rdev->scratch.num_reg; i++) {
  88.         rdev->scratch.free[i] = true;
  89.         rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
  90.     }
  91. }
  92.  
  93. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  94. {
  95.         int i;
  96.  
  97.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  98.                 if (rdev->scratch.free[i]) {
  99.                         rdev->scratch.free[i] = false;
  100.                         *reg = rdev->scratch.reg[i];
  101.                         return 0;
  102.                 }
  103.         }
  104.         return -EINVAL;
  105. }
  106.  
  107. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  108. {
  109.         int i;
  110.  
  111.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  112.                 if (rdev->scratch.reg[i] == reg) {
  113.                         rdev->scratch.free[i] = true;
  114.                         return;
  115.                 }
  116.         }
  117. }
  118.  
  119. /*
  120.  * MC common functions
  121.  */
  122. int radeon_mc_setup(struct radeon_device *rdev)
  123. {
  124.         uint32_t tmp;
  125.  
  126.         /* Some chips have an "issue" with the memory controller, the
  127.          * location must be aligned to the size. We just align it down,
  128.          * too bad if we walk over the top of system memory, we don't
  129.          * use DMA without a remapped anyway.
  130.          * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
  131.          */
  132.         /* FGLRX seems to setup like this, VRAM a 0, then GART.
  133.          */
  134.         /*
  135.          * Note: from R6xx the address space is 40bits but here we only
  136.          * use 32bits (still have to see a card which would exhaust 4G
  137.          * address space).
  138.          */
  139.         if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
  140.                 /* vram location was already setup try to put gtt after
  141.                  * if it fits */
  142.                 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
  143.                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
  144.                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
  145.                         rdev->mc.gtt_location = tmp;
  146.                 } else {
  147.                         if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
  148.                                 printk(KERN_ERR "[drm] GTT too big to fit "
  149.                                        "before or after vram location.\n");
  150.                                 return -EINVAL;
  151.                         }
  152.                         rdev->mc.gtt_location = 0;
  153.                 }
  154.         } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
  155.                 /* gtt location was already setup try to put vram before
  156.                  * if it fits */
  157.                 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
  158.                         rdev->mc.vram_location = 0;
  159.                 } else {
  160.                         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
  161.                         tmp += (rdev->mc.mc_vram_size - 1);
  162.                         tmp &= ~(rdev->mc.mc_vram_size - 1);
  163.                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
  164.                                 rdev->mc.vram_location = tmp;
  165.                         } else {
  166.                                 printk(KERN_ERR "[drm] vram too big to fit "
  167.                                        "before or after GTT location.\n");
  168.                                 return -EINVAL;
  169.                         }
  170.                 }
  171.         } else {
  172.                 rdev->mc.vram_location = 0;
  173.                 tmp = rdev->mc.mc_vram_size;
  174.                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
  175.                 rdev->mc.gtt_location = tmp;
  176.         }
  177.         rdev->mc.vram_start = rdev->mc.vram_location;
  178.         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
  179.         rdev->mc.gtt_start = rdev->mc.gtt_location;
  180.         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  181.         DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
  182.         DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
  183.                  (unsigned)rdev->mc.vram_location,
  184.                  (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
  185.         DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
  186.         DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
  187.                  (unsigned)rdev->mc.gtt_location,
  188.                  (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
  189.         return 0;
  190. }
  191.  
  192.  
  193. /*
  194.  * GPU helpers function.
  195.  */
  196. bool radeon_card_posted(struct radeon_device *rdev)
  197. {
  198.         uint32_t reg;
  199.  
  200.     ENTER();
  201.  
  202.         /* first check CRTCs */
  203.         if (ASIC_IS_AVIVO(rdev)) {
  204.                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
  205.                       RREG32(AVIVO_D2CRTC_CONTROL);
  206.                 if (reg & AVIVO_CRTC_EN) {
  207.                         return true;
  208.                 }
  209.         } else {
  210.                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
  211.                       RREG32(RADEON_CRTC2_GEN_CNTL);
  212.                 if (reg & RADEON_CRTC_EN) {
  213.                         return true;
  214.                 }
  215.         }
  216.  
  217.         /* then check MEM_SIZE, in case the crtcs are off */
  218.         if (rdev->family >= CHIP_R600)
  219.                 reg = RREG32(R600_CONFIG_MEMSIZE);
  220.         else
  221.                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
  222.  
  223.         if (reg)
  224.                 return true;
  225.  
  226.         return false;
  227.  
  228. }
  229.  
  230.  
  231. /*
  232.  * Registers accessors functions.
  233.  */
  234. uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  235. {
  236.     DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  237.     BUG_ON(1);
  238.     return 0;
  239. }
  240.  
  241. void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  242. {
  243.     DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  244.           reg, v);
  245.     BUG_ON(1);
  246. }
  247.  
  248. void radeon_register_accessor_init(struct radeon_device *rdev)
  249. {
  250.     rdev->mc_rreg = &radeon_invalid_rreg;
  251.     rdev->mc_wreg = &radeon_invalid_wreg;
  252.     rdev->pll_rreg = &radeon_invalid_rreg;
  253.     rdev->pll_wreg = &radeon_invalid_wreg;
  254.     rdev->pciep_rreg = &radeon_invalid_rreg;
  255.     rdev->pciep_wreg = &radeon_invalid_wreg;
  256.  
  257.     /* Don't change order as we are overridding accessor. */
  258.     if (rdev->family < CHIP_RV515) {
  259.                 rdev->pcie_reg_mask = 0xff;
  260.         } else {
  261.                 rdev->pcie_reg_mask = 0x7ff;
  262.     }
  263.     /* FIXME: not sure here */
  264.     if (rdev->family <= CHIP_R580) {
  265.         rdev->pll_rreg = &r100_pll_rreg;
  266.         rdev->pll_wreg = &r100_pll_wreg;
  267.     }
  268.         if (rdev->family >= CHIP_R420) {
  269.                 rdev->mc_rreg = &r420_mc_rreg;
  270.                 rdev->mc_wreg = &r420_mc_wreg;
  271.         }
  272.     if (rdev->family >= CHIP_RV515) {
  273.         rdev->mc_rreg = &rv515_mc_rreg;
  274.         rdev->mc_wreg = &rv515_mc_wreg;
  275.     }
  276.     if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  277.         rdev->mc_rreg = &rs400_mc_rreg;
  278.         rdev->mc_wreg = &rs400_mc_wreg;
  279.     }
  280.     if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  281.         rdev->mc_rreg = &rs690_mc_rreg;
  282.         rdev->mc_wreg = &rs690_mc_wreg;
  283.     }
  284.     if (rdev->family == CHIP_RS600) {
  285.         rdev->mc_rreg = &rs600_mc_rreg;
  286.         rdev->mc_wreg = &rs600_mc_wreg;
  287.     }
  288. //    if (rdev->family >= CHIP_R600) {
  289. //        rdev->pciep_rreg = &r600_pciep_rreg;
  290. //        rdev->pciep_wreg = &r600_pciep_wreg;
  291. //    }
  292. }
  293.  
  294.  
  295. /*
  296.  * ASIC
  297.  */
  298. int radeon_asic_init(struct radeon_device *rdev)
  299. {
  300.     radeon_register_accessor_init(rdev);
  301.         switch (rdev->family) {
  302.         case CHIP_R100:
  303.         case CHIP_RV100:
  304.         case CHIP_RS100:
  305.         case CHIP_RV200:
  306.         case CHIP_RS200:
  307.         case CHIP_R200:
  308.         case CHIP_RV250:
  309.         case CHIP_RS300:
  310.         case CHIP_RV280:
  311.         rdev->asic = &r100_asic;
  312.                 break;
  313.         case CHIP_R300:
  314.         case CHIP_R350:
  315.         case CHIP_RV350:
  316.         case CHIP_RV380:
  317.         rdev->asic = &r300_asic;
  318.                 if (rdev->flags & RADEON_IS_PCIE) {
  319.                         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
  320.                         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
  321.                 }
  322.                 break;
  323.         case CHIP_R420:
  324.         case CHIP_R423:
  325.         case CHIP_RV410:
  326.         rdev->asic = &r420_asic;
  327.                 break;
  328.         case CHIP_RS400:
  329.         case CHIP_RS480:
  330.        rdev->asic = &rs400_asic;
  331.                 break;
  332.         case CHIP_RS600:
  333.         rdev->asic = &rs600_asic;
  334.                 break;
  335.         case CHIP_RS690:
  336.         case CHIP_RS740:
  337.         rdev->asic = &rs690_asic;
  338.                 break;
  339.         case CHIP_RV515:
  340.         rdev->asic = &rv515_asic;
  341.                 break;
  342.         case CHIP_R520:
  343.         case CHIP_RV530:
  344.         case CHIP_RV560:
  345.         case CHIP_RV570:
  346.         case CHIP_R580:
  347.         rdev->asic = &r520_asic;
  348.                 break;
  349.         case CHIP_R600:
  350.         case CHIP_RV610:
  351.         case CHIP_RV630:
  352.         case CHIP_RV620:
  353.         case CHIP_RV635:
  354.         case CHIP_RV670:
  355.         case CHIP_RS780:
  356.         case CHIP_RS880:
  357. //              rdev->asic = &r600_asic;
  358.                 break;
  359.         case CHIP_RV770:
  360.         case CHIP_RV730:
  361.         case CHIP_RV710:
  362.         case CHIP_RV740:
  363. //              rdev->asic = &rv770_asic;
  364.                 break;
  365.         default:
  366.                 /* FIXME: not supported yet */
  367.                 return -EINVAL;
  368.         }
  369.         return 0;
  370. }
  371.  
  372.  
  373. /*
  374.  * Wrapper around modesetting bits.
  375.  */
  376. int radeon_clocks_init(struct radeon_device *rdev)
  377. {
  378.         int r;
  379.  
  380.     ENTER();
  381.  
  382.     r = radeon_static_clocks_init(rdev->ddev);
  383.         if (r) {
  384.                 return r;
  385.         }
  386.         DRM_INFO("Clocks initialized !\n");
  387.         return 0;
  388. }
  389.  
  390. void radeon_clocks_fini(struct radeon_device *rdev)
  391. {
  392. }
  393.  
  394. /* ATOM accessor methods */
  395. static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
  396. {
  397.     struct radeon_device *rdev = info->dev->dev_private;
  398.     uint32_t r;
  399.  
  400.     r = rdev->pll_rreg(rdev, reg);
  401.     return r;
  402. }
  403.  
  404. static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
  405. {
  406.     struct radeon_device *rdev = info->dev->dev_private;
  407.  
  408.     rdev->pll_wreg(rdev, reg, val);
  409. }
  410.  
  411. static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
  412. {
  413.     struct radeon_device *rdev = info->dev->dev_private;
  414.     uint32_t r;
  415.  
  416.     r = rdev->mc_rreg(rdev, reg);
  417.     return r;
  418. }
  419.  
  420. static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
  421. {
  422.     struct radeon_device *rdev = info->dev->dev_private;
  423.  
  424.     rdev->mc_wreg(rdev, reg, val);
  425. }
  426.  
  427. static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
  428. {
  429.     struct radeon_device *rdev = info->dev->dev_private;
  430.  
  431.     WREG32(reg*4, val);
  432. }
  433.  
  434. static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
  435. {
  436.     struct radeon_device *rdev = info->dev->dev_private;
  437.     uint32_t r;
  438.  
  439.     r = RREG32(reg*4);
  440.     return r;
  441. }
  442.  
  443. static struct card_info atom_card_info = {
  444.     .dev = NULL,
  445.     .reg_read = cail_reg_read,
  446.     .reg_write = cail_reg_write,
  447.     .mc_read = cail_mc_read,
  448.     .mc_write = cail_mc_write,
  449.     .pll_read = cail_pll_read,
  450.     .pll_write = cail_pll_write,
  451. };
  452.  
  453. int radeon_atombios_init(struct radeon_device *rdev)
  454. {
  455.     ENTER();
  456.  
  457.     atom_card_info.dev = rdev->ddev;
  458.     rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
  459.     radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
  460.     return 0;
  461. }
  462.  
  463. void radeon_atombios_fini(struct radeon_device *rdev)
  464. {
  465.         kfree(rdev->mode_info.atom_context);
  466. }
  467.  
  468. int radeon_combios_init(struct radeon_device *rdev)
  469. {
  470.         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
  471.         return 0;
  472. }
  473.  
  474. void radeon_combios_fini(struct radeon_device *rdev)
  475. {
  476. }
  477.  
  478. int radeon_modeset_init(struct radeon_device *rdev);
  479. void radeon_modeset_fini(struct radeon_device *rdev);
  480.  
  481. void radeon_agp_disable(struct radeon_device *rdev)
  482. {
  483.         rdev->flags &= ~RADEON_IS_AGP;
  484.         if (rdev->family >= CHIP_R600) {
  485.                 DRM_INFO("Forcing AGP to PCIE mode\n");
  486.                 rdev->flags |= RADEON_IS_PCIE;
  487.         } else if (rdev->family >= CHIP_RV515 ||
  488.                         rdev->family == CHIP_RV380 ||
  489.                         rdev->family == CHIP_RV410 ||
  490.                         rdev->family == CHIP_R423) {
  491.                 DRM_INFO("Forcing AGP to PCIE mode\n");
  492.                 rdev->flags |= RADEON_IS_PCIE;
  493.                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
  494.                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
  495.         } else {
  496.                 DRM_INFO("Forcing AGP to PCI mode\n");
  497.                 rdev->flags |= RADEON_IS_PCI;
  498.                 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
  499.                 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
  500.         }
  501. }
  502.  
  503. /*
  504.  * Radeon device.
  505.  */
  506. int radeon_device_init(struct radeon_device *rdev,
  507.                struct drm_device *ddev,
  508.                struct pci_dev *pdev,
  509.                uint32_t flags)
  510. {
  511.         int r;
  512.         int dma_bits;
  513.  
  514.     ENTER();
  515.  
  516.     DRM_INFO("radeon: Initializing kernel modesetting.\n");
  517.     rdev->shutdown = false;
  518.     rdev->ddev = ddev;
  519.     rdev->pdev = pdev;
  520.     rdev->flags = flags;
  521.     rdev->family = flags & RADEON_FAMILY_MASK;
  522.     rdev->is_atom_bios = false;
  523.     rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
  524.     rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  525.     rdev->gpu_lockup = false;
  526.         rdev->accel_working = false;
  527.     /* mutex initialization are all done here so we
  528.      * can recall function without having locking issues */
  529.  //   mutex_init(&rdev->cs_mutex);
  530.  //   mutex_init(&rdev->ib_pool.mutex);
  531.  //   mutex_init(&rdev->cp.mutex);
  532.  //   rwlock_init(&rdev->fence_drv.lock);
  533.  
  534.         /* Set asic functions */
  535.         r = radeon_asic_init(rdev);
  536.         if (r) {
  537.                 return r;
  538.         }
  539.  
  540.     if (radeon_agpmode == -1) {
  541.                 radeon_agp_disable(rdev);
  542.     }
  543.  
  544.         /* set DMA mask + need_dma32 flags.
  545.          * PCIE - can handle 40-bits.
  546.          * IGP - can handle 40-bits (in theory)
  547.          * AGP - generally dma32 is safest
  548.          * PCI - only dma32
  549.          */
  550.         rdev->need_dma32 = false;
  551.         if (rdev->flags & RADEON_IS_AGP)
  552.                 rdev->need_dma32 = true;
  553.         if (rdev->flags & RADEON_IS_PCI)
  554.                 rdev->need_dma32 = true;
  555.  
  556.         dma_bits = rdev->need_dma32 ? 32 : 40;
  557.         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
  558.     if (r) {
  559.         printk(KERN_WARNING "radeon: No suitable DMA available.\n");
  560.     }
  561.  
  562.     /* Registers mapping */
  563.     /* TODO: block userspace mapping of io register */
  564.     rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
  565.  
  566.     rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
  567.  
  568.     rdev->rmmio =  (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
  569.                                    PG_SW+PG_NOCACHE);
  570.  
  571.     if (rdev->rmmio == NULL) {
  572.         return -ENOMEM;
  573.     }
  574.     DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
  575.     DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
  576.  
  577.         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
  578. //      r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
  579. //      if (r) {
  580. //              return -EINVAL;
  581. //      }
  582.  
  583.         r = radeon_init(rdev);
  584.         if (r)
  585.             return r;
  586.  
  587.         if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
  588.                 /* Acceleration not working on AGP card try again
  589.                  * with fallback to PCI or PCIE GART
  590.                  */
  591.                 radeon_gpu_reset(rdev);
  592.                 radeon_fini(rdev);
  593.                 radeon_agp_disable(rdev);
  594.                 r = radeon_init(rdev);
  595.                 if (r)
  596.                 return r;
  597.         }
  598. //      if (radeon_testing) {
  599. //              radeon_test_moves(rdev);
  600. //    }
  601. //      if (radeon_benchmarking) {
  602. //              radeon_benchmark(rdev);
  603. //    }
  604.         return 0;
  605. }
  606.  
  607.  
  608. static struct pci_device_id pciidlist[] = {
  609.     radeon_PCI_IDS
  610. };
  611.  
  612.  
  613. u32_t drvEntry(int action, char *cmdline)
  614. {
  615.     struct pci_device_id  *ent;
  616.  
  617.     dev_t   device;
  618.     int     err;
  619.     u32_t   retval = 0;
  620.  
  621.     if(action != 1)
  622.         return 0;
  623.  
  624.     if(!dbg_open("/hd0/2/atikms.log"))
  625.     {
  626.         printf("Can't open /hd0/2/atikms.log\nExit\n");
  627.         return 0;
  628.     }
  629.  
  630.     if(cmdline)
  631.         dbgprintf("cmdline: %s\n", cmdline);
  632.  
  633.     enum_pci_devices();
  634.  
  635.     ent = find_pci_device(&device, pciidlist);
  636.  
  637.     if( unlikely(ent == NULL) )
  638.     {
  639.         dbgprintf("device not found\n");
  640.         return 0;
  641.     };
  642.  
  643.     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
  644.                                 device.pci_dev.device);
  645.  
  646.     err = drm_get_dev(&device.pci_dev, ent);
  647.  
  648.     return retval;
  649. };
  650.  
  651.  
  652.  
  653. /*
  654.  * Driver load/unload
  655.  */
  656. int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  657. {
  658.     struct radeon_device *rdev;
  659.     int r;
  660.  
  661.     ENTER();
  662.  
  663.     rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  664.     if (rdev == NULL) {
  665.         return -ENOMEM;
  666.     };
  667.  
  668.     dev->dev_private = (void *)rdev;
  669.  
  670.     /* update BUS flag */
  671. //    if (drm_device_is_agp(dev)) {
  672.         flags |= RADEON_IS_AGP;
  673. //    } else if (drm_device_is_pcie(dev)) {
  674. //        flags |= RADEON_IS_PCIE;
  675. //    } else {
  676. //        flags |= RADEON_IS_PCI;
  677. //    }
  678.  
  679.     /* radeon_device_init should report only fatal error
  680.      * like memory allocation failure or iomapping failure,
  681.      * or memory manager initialization failure, it must
  682.      * properly initialize the GPU MC controller and permit
  683.      * VRAM allocation
  684.      */
  685.     r = radeon_device_init(rdev, dev, dev->pdev, flags);
  686.     if (r) {
  687.         DRM_ERROR("Fatal error while trying to initialize radeon.\n");
  688.         return r;
  689.     }
  690.     /* Again modeset_init should fail only on fatal error
  691.      * otherwise it should provide enough functionalities
  692.      * for shadowfb to run
  693.      */
  694.     r = radeon_modeset_init(rdev);
  695.     if (r) {
  696.         return r;
  697.     }
  698.     return 0;
  699. }
  700.  
  701.  
  702. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  703. {
  704.     struct drm_device *dev;
  705.     int ret;
  706.  
  707.     ENTER();
  708.  
  709.     dev = malloc(sizeof(*dev));
  710.     if (!dev)
  711.         return -ENOMEM;
  712.  
  713.  //   ret = pci_enable_device(pdev);
  714.  //   if (ret)
  715.  //       goto err_g1;
  716.  
  717.  //   pci_set_master(pdev);
  718.  
  719.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  720.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  721.  //       goto err_g2;
  722.  //   }
  723.  
  724.     dev->pdev = pdev;
  725.     dev->pci_device = pdev->device;
  726.     dev->pci_vendor = pdev->vendor;
  727.  
  728.  //   if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  729.  //       pci_set_drvdata(pdev, dev);
  730.  //       ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
  731.  //       if (ret)
  732.  //           goto err_g2;
  733.  //   }
  734.  
  735.  //   if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY)))
  736.  //       goto err_g3;
  737.  
  738.  //   if (dev->driver->load) {
  739.  //       ret = dev->driver->load(dev, ent->driver_data);
  740.  //       if (ret)
  741.  //           goto err_g4;
  742.  //   }
  743.  
  744.     ret = radeon_driver_load_kms(dev, ent->driver_data );
  745.     if (ret)
  746.         goto err_g4;
  747.  
  748.  //   list_add_tail(&dev->driver_item, &driver->device_list);
  749.  
  750.  //   DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
  751.  //        driver->name, driver->major, driver->minor, driver->patchlevel,
  752.  //        driver->date, pci_name(pdev), dev->primary->index);
  753.  
  754.     pre_init_display(dev->dev_private);
  755.     set_mode(dev, 1280, 1024);
  756.     post_init_display(dev->dev_private);
  757.  
  758.     LEAVE();
  759.  
  760.     return 0;
  761.  
  762. err_g4:
  763. //    drm_put_minor(&dev->primary);
  764. //err_g3:
  765. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  766. //        drm_put_minor(&dev->control);
  767. //err_g2:
  768. //    pci_disable_device(pdev);
  769. //err_g1:
  770.     free(dev);
  771.  
  772.     LEAVE();
  773.  
  774.     return ret;
  775. }
  776.  
  777. resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
  778. {
  779.     return pci_resource_start(dev->pdev, resource);
  780. }
  781.  
  782. resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
  783. {
  784.     return pci_resource_len(dev->pdev, resource);
  785. }
  786.  
  787.  
  788. uint32_t __div64_32(uint64_t *n, uint32_t base)
  789. {
  790.         uint64_t rem = *n;
  791.         uint64_t b = base;
  792.         uint64_t res, d = 1;
  793.         uint32_t high = rem >> 32;
  794.  
  795.         /* Reduce the thing a bit first */
  796.         res = 0;
  797.         if (high >= base) {
  798.                 high /= base;
  799.                 res = (uint64_t) high << 32;
  800.                 rem -= (uint64_t) (high*base) << 32;
  801.         }
  802.  
  803.         while ((int64_t)b > 0 && b < rem) {
  804.                 b = b+b;
  805.                 d = d+d;
  806.         }
  807.  
  808.         do {
  809.                 if (rem >= b) {
  810.                         rem -= b;
  811.                         res += d;
  812.                 }
  813.                 b >>= 1;
  814.                 d >>= 1;
  815.         } while (d);
  816.  
  817.         *n = res;
  818.         return rem;
  819. }
  820.  
  821.