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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. //#include <linux/console.h>
  29.  
  30. #include <drmP.h>
  31. #include <drm_crtc_helper.h>
  32. #include "radeon_drm.h"
  33. #include "radeon_reg.h"
  34. #include "radeon.h"
  35. #include "radeon_asic.h"
  36. #include "atom.h"
  37.  
  38. #include <syscall.h>
  39.  
  40. int radeon_dynclks = -1;
  41. int radeon_r4xx_atom = 0;
  42. int radeon_agpmode   = -1;
  43. int radeon_gart_size = 512; /* default gart size */
  44. int radeon_benchmarking = 0;
  45. int radeon_connector_table = 0;
  46.  
  47.  
  48. /*
  49.  * Clear GPU surface registers.
  50.  */
  51. static void radeon_surface_init(struct radeon_device *rdev)
  52. {
  53.     dbgprintf("%s\n",__FUNCTION__);
  54.  
  55.     /* FIXME: check this out */
  56.     if (rdev->family < CHIP_R600) {
  57.         int i;
  58.  
  59.         for (i = 0; i < 8; i++) {
  60.             WREG32(RADEON_SURFACE0_INFO +
  61.                    i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
  62.                    0);
  63.         }
  64.     }
  65. }
  66.  
  67. /*
  68.  * GPU scratch registers helpers function.
  69.  */
  70. static void radeon_scratch_init(struct radeon_device *rdev)
  71. {
  72.     int i;
  73.  
  74.     /* FIXME: check this out */
  75.     if (rdev->family < CHIP_R300) {
  76.         rdev->scratch.num_reg = 5;
  77.     } else {
  78.         rdev->scratch.num_reg = 7;
  79.     }
  80.     for (i = 0; i < rdev->scratch.num_reg; i++) {
  81.         rdev->scratch.free[i] = true;
  82.         rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
  83.     }
  84. }
  85.  
  86. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
  87. {
  88.         int i;
  89.  
  90.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  91.                 if (rdev->scratch.free[i]) {
  92.                         rdev->scratch.free[i] = false;
  93.                         *reg = rdev->scratch.reg[i];
  94.                         return 0;
  95.                 }
  96.         }
  97.         return -EINVAL;
  98. }
  99.  
  100. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
  101. {
  102.         int i;
  103.  
  104.         for (i = 0; i < rdev->scratch.num_reg; i++) {
  105.                 if (rdev->scratch.reg[i] == reg) {
  106.                         rdev->scratch.free[i] = true;
  107.                         return;
  108.                 }
  109.         }
  110. }
  111.  
  112. /*
  113.  * MC common functions
  114.  */
  115. int radeon_mc_setup(struct radeon_device *rdev)
  116. {
  117.         uint32_t tmp;
  118.  
  119.         /* Some chips have an "issue" with the memory controller, the
  120.          * location must be aligned to the size. We just align it down,
  121.          * too bad if we walk over the top of system memory, we don't
  122.          * use DMA without a remapped anyway.
  123.          * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
  124.          */
  125.         /* FGLRX seems to setup like this, VRAM a 0, then GART.
  126.          */
  127.         /*
  128.          * Note: from R6xx the address space is 40bits but here we only
  129.          * use 32bits (still have to see a card which would exhaust 4G
  130.          * address space).
  131.          */
  132.         if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
  133.                 /* vram location was already setup try to put gtt after
  134.                  * if it fits */
  135.                 tmp = rdev->mc.vram_location + rdev->mc.vram_size;
  136.                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
  137.                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
  138.                         rdev->mc.gtt_location = tmp;
  139.                 } else {
  140.                         if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
  141.                                 printk(KERN_ERR "[drm] GTT too big to fit "
  142.                                        "before or after vram location.\n");
  143.                                 return -EINVAL;
  144.                         }
  145.                         rdev->mc.gtt_location = 0;
  146.                 }
  147.         } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
  148.                 /* gtt location was already setup try to put vram before
  149.                  * if it fits */
  150.                 if (rdev->mc.vram_size < rdev->mc.gtt_location) {
  151.                         rdev->mc.vram_location = 0;
  152.                 } else {
  153.                         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
  154.                         tmp += (rdev->mc.vram_size - 1);
  155.                         tmp &= ~(rdev->mc.vram_size - 1);
  156.                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
  157.                                 rdev->mc.vram_location = tmp;
  158.                         } else {
  159.                                 printk(KERN_ERR "[drm] vram too big to fit "
  160.                                        "before or after GTT location.\n");
  161.                                 return -EINVAL;
  162.                         }
  163.                 }
  164.         } else {
  165.                 rdev->mc.vram_location = 0;
  166.                 rdev->mc.gtt_location = rdev->mc.vram_size;
  167.         }
  168.         DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
  169.         DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
  170.                  rdev->mc.vram_location,
  171.                  rdev->mc.vram_location + rdev->mc.vram_size - 1);
  172.         DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
  173.         DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
  174.                  rdev->mc.gtt_location,
  175.                  rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
  176.         return 0;
  177. }
  178.  
  179.  
  180. /*
  181.  * GPU helpers function.
  182.  */
  183. static bool radeon_card_posted(struct radeon_device *rdev)
  184. {
  185.         uint32_t reg;
  186.  
  187.     dbgprintf("%s\n",__FUNCTION__);
  188.  
  189.         /* first check CRTCs */
  190.         if (ASIC_IS_AVIVO(rdev)) {
  191.                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
  192.                       RREG32(AVIVO_D2CRTC_CONTROL);
  193.                 if (reg & AVIVO_CRTC_EN) {
  194.                         return true;
  195.                 }
  196.         } else {
  197.                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
  198.                       RREG32(RADEON_CRTC2_GEN_CNTL);
  199.                 if (reg & RADEON_CRTC_EN) {
  200.                         return true;
  201.                 }
  202.         }
  203.  
  204.         /* then check MEM_SIZE, in case the crtcs are off */
  205.         if (rdev->family >= CHIP_R600)
  206.                 reg = RREG32(R600_CONFIG_MEMSIZE);
  207.         else
  208.                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
  209.  
  210.         if (reg)
  211.                 return true;
  212.  
  213.         return false;
  214.  
  215. }
  216.  
  217.  
  218. /*
  219.  * Registers accessors functions.
  220.  */
  221. uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  222. {
  223.     DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  224.     BUG_ON(1);
  225.     return 0;
  226. }
  227.  
  228. void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  229. {
  230.     DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  231.           reg, v);
  232.     BUG_ON(1);
  233. }
  234.  
  235. void radeon_register_accessor_init(struct radeon_device *rdev)
  236. {
  237.  
  238.     dbgprintf("%s\n",__FUNCTION__);
  239.  
  240.     rdev->mm_rreg = &r100_mm_rreg;
  241.     rdev->mm_wreg = &r100_mm_wreg;
  242.     rdev->mc_rreg = &radeon_invalid_rreg;
  243.     rdev->mc_wreg = &radeon_invalid_wreg;
  244.     rdev->pll_rreg = &radeon_invalid_rreg;
  245.     rdev->pll_wreg = &radeon_invalid_wreg;
  246.     rdev->pcie_rreg = &radeon_invalid_rreg;
  247.     rdev->pcie_wreg = &radeon_invalid_wreg;
  248.     rdev->pciep_rreg = &radeon_invalid_rreg;
  249.     rdev->pciep_wreg = &radeon_invalid_wreg;
  250.  
  251.     /* Don't change order as we are overridding accessor. */
  252.     if (rdev->family < CHIP_RV515) {
  253.         rdev->pcie_rreg = &rv370_pcie_rreg;
  254.         rdev->pcie_wreg = &rv370_pcie_wreg;
  255.     }
  256.     if (rdev->family >= CHIP_RV515) {
  257.         rdev->pcie_rreg = &rv515_pcie_rreg;
  258.         rdev->pcie_wreg = &rv515_pcie_wreg;
  259.     }
  260.     /* FIXME: not sure here */
  261.     if (rdev->family <= CHIP_R580) {
  262.         rdev->pll_rreg = &r100_pll_rreg;
  263.         rdev->pll_wreg = &r100_pll_wreg;
  264.     }
  265.     if (rdev->family >= CHIP_RV515) {
  266.         rdev->mc_rreg = &rv515_mc_rreg;
  267.         rdev->mc_wreg = &rv515_mc_wreg;
  268.     }
  269.     if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
  270.         rdev->mc_rreg = &rs400_mc_rreg;
  271.         rdev->mc_wreg = &rs400_mc_wreg;
  272.     }
  273.     if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
  274.         rdev->mc_rreg = &rs690_mc_rreg;
  275.         rdev->mc_wreg = &rs690_mc_wreg;
  276.     }
  277.     if (rdev->family == CHIP_RS600) {
  278.         rdev->mc_rreg = &rs600_mc_rreg;
  279.         rdev->mc_wreg = &rs600_mc_wreg;
  280.     }
  281.     if (rdev->family >= CHIP_R600) {
  282.         rdev->pciep_rreg = &r600_pciep_rreg;
  283.         rdev->pciep_wreg = &r600_pciep_wreg;
  284.     }
  285. }
  286.  
  287.  
  288. /*
  289.  * ASIC
  290.  */
  291. int radeon_asic_init(struct radeon_device *rdev)
  292. {
  293.  
  294.     dbgprintf("%s\n",__FUNCTION__);
  295.  
  296.     radeon_register_accessor_init(rdev);
  297.         switch (rdev->family) {
  298.         case CHIP_R100:
  299.         case CHIP_RV100:
  300.         case CHIP_RS100:
  301.         case CHIP_RV200:
  302.         case CHIP_RS200:
  303.         case CHIP_R200:
  304.         case CHIP_RV250:
  305.         case CHIP_RS300:
  306.         case CHIP_RV280:
  307.         rdev->asic = &r100_asic;
  308.                 break;
  309.         case CHIP_R300:
  310.         case CHIP_R350:
  311.         case CHIP_RV350:
  312.         case CHIP_RV380:
  313.         rdev->asic = &r300_asic;
  314.                 break;
  315.         case CHIP_R420:
  316.         case CHIP_R423:
  317.         case CHIP_RV410:
  318.         rdev->asic = &r420_asic;
  319.                 break;
  320.         case CHIP_RS400:
  321.         case CHIP_RS480:
  322.        rdev->asic = &rs400_asic;
  323.                 break;
  324.         case CHIP_RS600:
  325.        rdev->asic = &rs600_asic;
  326.                 break;
  327.         case CHIP_RS690:
  328.         case CHIP_RS740:
  329.         rdev->asic = &rs690_asic;
  330.                 break;
  331.         case CHIP_RV515:
  332.         rdev->asic = &rv515_asic;
  333.                 break;
  334.         case CHIP_R520:
  335.         case CHIP_RV530:
  336.         case CHIP_RV560:
  337.         case CHIP_RV570:
  338.         case CHIP_R580:
  339.         rdev->asic = &r520_asic;
  340.                 break;
  341.         case CHIP_R600:
  342.         case CHIP_RV610:
  343.         case CHIP_RV630:
  344.         case CHIP_RV620:
  345.         case CHIP_RV635:
  346.         case CHIP_RV670:
  347.         case CHIP_RS780:
  348.         case CHIP_RV770:
  349.         case CHIP_RV730:
  350.         case CHIP_RV710:
  351.         default:
  352.                 /* FIXME: not supported yet */
  353.                 return -EINVAL;
  354.         }
  355.         return 0;
  356. }
  357.  
  358.  
  359. /*
  360.  * Wrapper around modesetting bits.
  361.  */
  362. int radeon_clocks_init(struct radeon_device *rdev)
  363. {
  364.         int r;
  365.  
  366.     dbgprintf("%s\n",__FUNCTION__);
  367.  
  368.     radeon_get_clock_info(rdev->ddev);
  369.     r = radeon_static_clocks_init(rdev->ddev);
  370.         if (r) {
  371.                 return r;
  372.         }
  373.         DRM_INFO("Clocks initialized !\n");
  374.         return 0;
  375. }
  376.  
  377. void radeon_clocks_fini(struct radeon_device *rdev)
  378. {
  379. }
  380.  
  381. /* ATOM accessor methods */
  382. static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
  383. {
  384.     struct radeon_device *rdev = info->dev->dev_private;
  385.     uint32_t r;
  386.  
  387.     r = rdev->pll_rreg(rdev, reg);
  388.     return r;
  389. }
  390.  
  391. static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
  392. {
  393.     struct radeon_device *rdev = info->dev->dev_private;
  394.  
  395.     rdev->pll_wreg(rdev, reg, val);
  396. }
  397.  
  398. static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
  399. {
  400.     struct radeon_device *rdev = info->dev->dev_private;
  401.     uint32_t r;
  402.  
  403.     r = rdev->mc_rreg(rdev, reg);
  404.     return r;
  405. }
  406.  
  407. static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
  408. {
  409.     struct radeon_device *rdev = info->dev->dev_private;
  410.  
  411.     rdev->mc_wreg(rdev, reg, val);
  412. }
  413.  
  414. static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
  415. {
  416.     struct radeon_device *rdev = info->dev->dev_private;
  417.  
  418.     WREG32(reg*4, val);
  419. }
  420.  
  421. static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
  422. {
  423.     struct radeon_device *rdev = info->dev->dev_private;
  424.     uint32_t r;
  425.  
  426.     r = RREG32(reg*4);
  427.     return r;
  428. }
  429.  
  430. static struct card_info atom_card_info = {
  431.     .dev = NULL,
  432.     .reg_read = cail_reg_read,
  433.     .reg_write = cail_reg_write,
  434.     .mc_read = cail_mc_read,
  435.     .mc_write = cail_mc_write,
  436.     .pll_read = cail_pll_read,
  437.     .pll_write = cail_pll_write,
  438. };
  439.  
  440. int radeon_atombios_init(struct radeon_device *rdev)
  441. {
  442.     dbgprintf("%s\n",__FUNCTION__);
  443.  
  444.     atom_card_info.dev = rdev->ddev;
  445.     rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
  446.     radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
  447.     return 0;
  448. }
  449.  
  450. void radeon_atombios_fini(struct radeon_device *rdev)
  451. {
  452.         kfree(rdev->mode_info.atom_context);
  453. }
  454.  
  455. int radeon_combios_init(struct radeon_device *rdev)
  456. {
  457.         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
  458.         return 0;
  459. }
  460.  
  461. void radeon_combios_fini(struct radeon_device *rdev)
  462. {
  463. }
  464.  
  465. int radeon_modeset_init(struct radeon_device *rdev);
  466. void radeon_modeset_fini(struct radeon_device *rdev);
  467.  
  468. /*
  469.  * Radeon device.
  470.  */
  471. int radeon_device_init(struct radeon_device *rdev,
  472.                struct drm_device *ddev,
  473.                struct pci_dev *pdev,
  474.                uint32_t flags)
  475. {
  476.         int r, ret;
  477.  
  478.     dbgprintf("%s\n",__FUNCTION__);
  479.  
  480.     DRM_INFO("radeon: Initializing kernel modesetting.\n");
  481.     rdev->shutdown = false;
  482.     rdev->ddev = ddev;
  483.     rdev->pdev = pdev;
  484.     rdev->flags = flags;
  485.     rdev->family = flags & RADEON_FAMILY_MASK;
  486.     rdev->is_atom_bios = false;
  487.     rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
  488.     rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  489.     rdev->gpu_lockup = false;
  490.     /* mutex initialization are all done here so we
  491.      * can recall function without having locking issues */
  492.  //   mutex_init(&rdev->cs_mutex);
  493.  //   mutex_init(&rdev->ib_pool.mutex);
  494.  //   mutex_init(&rdev->cp.mutex);
  495.  //   rwlock_init(&rdev->fence_drv.lock);
  496.  
  497.     if (radeon_agpmode == -1) {
  498.         rdev->flags &= ~RADEON_IS_AGP;
  499.         if (rdev->family > CHIP_RV515 ||
  500.             rdev->family == CHIP_RV380 ||
  501.             rdev->family == CHIP_RV410 ||
  502.             rdev->family == CHIP_R423) {
  503.             DRM_INFO("Forcing AGP to PCIE mode\n");
  504.             rdev->flags |= RADEON_IS_PCIE;
  505.         } else {
  506.             DRM_INFO("Forcing AGP to PCI mode\n");
  507.             rdev->flags |= RADEON_IS_PCI;
  508.         }
  509.     }
  510.  
  511.     /* Set asic functions */
  512.     r = radeon_asic_init(rdev);
  513.     if (r) {
  514.         return r;
  515.     }
  516.  
  517.     r = rdev->asic->init(rdev);
  518.  
  519.     if (r) {
  520.         return r;
  521.     }
  522.  
  523.     /* Report DMA addressing limitation */
  524.     r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
  525.     if (r) {
  526.         printk(KERN_WARNING "radeon: No suitable DMA available.\n");
  527.     }
  528.  
  529.     /* Registers mapping */
  530.     /* TODO: block userspace mapping of io register */
  531.     rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
  532.  
  533.     rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
  534.  
  535.     rdev->rmmio =  (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
  536.                                    PG_SW+PG_NOCACHE);
  537.  
  538.     if (rdev->rmmio == NULL) {
  539.         return -ENOMEM;
  540.     }
  541.     DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
  542.     DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
  543.  
  544.     /* Setup errata flags */
  545.     radeon_errata(rdev);
  546.     /* Initialize scratch registers */
  547.     radeon_scratch_init(rdev);
  548.         /* Initialize surface registers */
  549.     radeon_surface_init(rdev);
  550.  
  551.     /* TODO: disable VGA need to use VGA request */
  552.     /* BIOS*/
  553.     if (!radeon_get_bios(rdev)) {
  554.         if (ASIC_IS_AVIVO(rdev))
  555.             return -EINVAL;
  556.     }
  557.     if (rdev->is_atom_bios) {
  558.         r = radeon_atombios_init(rdev);
  559.         if (r) {
  560.             return r;
  561.         }
  562.     } else {
  563.         r = radeon_combios_init(rdev);
  564.         if (r) {
  565.             return r;
  566.         }
  567.     }
  568.     /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  569.     if (radeon_gpu_reset(rdev)) {
  570.         /* FIXME: what do we want to do here ? */
  571.     }
  572.     /* check if cards are posted or not */
  573.     if (!radeon_card_posted(rdev) && rdev->bios) {
  574.         DRM_INFO("GPU not posted. posting now...\n");
  575.         if (rdev->is_atom_bios) {
  576.             atom_asic_init(rdev->mode_info.atom_context);
  577.         } else {
  578.                         radeon_combios_asic_init(rdev->ddev);
  579.         }
  580.     }
  581.     /* Get vram informations */
  582.     radeon_vram_info(rdev);
  583.     /* Device is severly broken if aper size > vram size.
  584.      * for RN50/M6/M7 - Novell bug 204882 ?
  585.      */
  586.     if (rdev->mc.vram_size < rdev->mc.aper_size) {
  587.         rdev->mc.aper_size = rdev->mc.vram_size;
  588.     }
  589.     /* Add an MTRR for the VRAM */
  590. //    rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
  591. //                      MTRR_TYPE_WRCOMB, 1);
  592.     DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
  593.          rdev->mc.vram_size >> 20,
  594.          (unsigned)rdev->mc.aper_size >> 20);
  595.     DRM_INFO("RAM width %dbits %cDR\n",
  596.          rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
  597.  
  598.     /* Initialize clocks */
  599.     r = radeon_clocks_init(rdev);
  600.     if (r) {
  601.         return r;
  602.     }
  603.  
  604.     /* Initialize memory controller (also test AGP) */
  605.     r = radeon_mc_init(rdev);
  606.     if (r) {
  607.         return r;
  608.         }
  609.     /* Fence driver */
  610. //    r = radeon_fence_driver_init(rdev);
  611. //    if (r) {
  612. //        return r;
  613. //    }
  614. //    r = radeon_irq_kms_init(rdev);
  615. //    if (r) {
  616. //        return r;
  617. //    }
  618.     /* Memory manager */
  619.     r = radeon_object_init(rdev);
  620.     if (r) {
  621.         return r;
  622.     }
  623.     /* Initialize GART (initialize after TTM so we can allocate
  624.      * memory through TTM but finalize after TTM) */
  625.     r = radeon_gart_enable(rdev);
  626.     if (!r) {
  627.         r = radeon_gem_init(rdev);
  628.     }
  629.  
  630.     /* 1M ring buffer */
  631.     if (!r) {
  632.         r = radeon_cp_init(rdev, 1024 * 1024);
  633.     }
  634. //    if (!r) {
  635. //        r = radeon_wb_init(rdev);
  636. //        if (r) {
  637. //            DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
  638. //            return r;
  639. //        }
  640. //    }
  641.  
  642. #if 0
  643.     if (!r) {
  644.         r = radeon_ib_pool_init(rdev);
  645.         if (r) {
  646.             DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
  647.             return r;
  648.         }
  649.     }
  650.     if (!r) {
  651.         r = radeon_ib_test(rdev);
  652.         if (r) {
  653.             DRM_ERROR("radeon: failled testing IB (%d).\n", r);
  654.             return r;
  655.         }
  656.     }
  657. #endif
  658.  
  659.     ret = r;
  660.     r = radeon_modeset_init(rdev);
  661.     if (r) {
  662.         return r;
  663.     }
  664. //    if (rdev->fbdev_rfb && rdev->fbdev_rfb->obj) {
  665. //        rdev->fbdev_robj = rdev->fbdev_rfb->obj->driver_private;
  666. //    }
  667.     if (!ret) {
  668.         DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
  669.     }
  670.         if (radeon_benchmarking) {
  671. //        radeon_benchmark(rdev);
  672.         }
  673.         return ret;
  674.  
  675. //    return -1;
  676. }
  677.  
  678. static struct pci_device_id pciidlist[] = {
  679.     radeon_PCI_IDS
  680. };
  681.  
  682.  
  683. u32_t __stdcall drvEntry(int action)
  684. {
  685.     struct pci_device_id  *ent;
  686.  
  687.     dev_t   device;
  688.     int     err;
  689.     u32_t   retval = 0;
  690.  
  691.     if(action != 1)
  692.         return 0;
  693.  
  694.     if(!dbg_open("/hd0/2/atikms.log"))
  695.     {
  696.         printf("Can't open /hd0/2/atikms.log\nExit\n");
  697.         return 0;
  698.     }
  699.  
  700.     enum_pci_devices();
  701.  
  702.     ent = find_pci_device(&device, pciidlist);
  703.  
  704.     if( unlikely(ent == NULL) )
  705.     {
  706.         dbgprintf("device not found\n");
  707.         return 0;
  708.     };
  709.  
  710.     dbgprintf("device %x:%x\n", device.pci_dev.vendor,
  711.                                 device.pci_dev.device);
  712.  
  713.     err = drm_get_dev(&device.pci_dev, ent);
  714.  
  715.     return retval;
  716. };
  717.  
  718. /*
  719. static struct drm_driver kms_driver = {
  720.     .driver_features =
  721.         DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG |
  722.         DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM,
  723.     .dev_priv_size = 0,
  724.     .load = radeon_driver_load_kms,
  725.     .firstopen = radeon_driver_firstopen_kms,
  726.     .open = radeon_driver_open_kms,
  727.     .preclose = radeon_driver_preclose_kms,
  728.     .postclose = radeon_driver_postclose_kms,
  729.     .lastclose = radeon_driver_lastclose_kms,
  730.     .unload = radeon_driver_unload_kms,
  731.     .suspend = radeon_suspend_kms,
  732.     .resume = radeon_resume_kms,
  733.     .get_vblank_counter = radeon_get_vblank_counter_kms,
  734.     .enable_vblank = radeon_enable_vblank_kms,
  735.     .disable_vblank = radeon_disable_vblank_kms,
  736.     .master_create = radeon_master_create_kms,
  737.     .master_destroy = radeon_master_destroy_kms,
  738. #if defined(CONFIG_DEBUG_FS)
  739.     .debugfs_init = radeon_debugfs_init,
  740.     .debugfs_cleanup = radeon_debugfs_cleanup,
  741. #endif
  742.     .irq_preinstall = radeon_driver_irq_preinstall_kms,
  743.     .irq_postinstall = radeon_driver_irq_postinstall_kms,
  744.     .irq_uninstall = radeon_driver_irq_uninstall_kms,
  745.     .irq_handler = radeon_driver_irq_handler_kms,
  746.     .reclaim_buffers = drm_core_reclaim_buffers,
  747.     .get_map_ofs = drm_core_get_map_ofs,
  748.     .get_reg_ofs = drm_core_get_reg_ofs,
  749.     .ioctls = radeon_ioctls_kms,
  750.     .gem_init_object = radeon_gem_object_init,
  751.     .gem_free_object = radeon_gem_object_free,
  752.     .dma_ioctl = radeon_dma_ioctl_kms,
  753.     .fops = {
  754.          .owner = THIS_MODULE,
  755.          .open = drm_open,
  756.          .release = drm_release,
  757.          .ioctl = drm_ioctl,
  758.          .mmap = radeon_mmap,
  759.          .poll = drm_poll,
  760.          .fasync = drm_fasync,
  761. #ifdef CONFIG_COMPAT
  762.          .compat_ioctl = NULL,
  763. #endif
  764.     },
  765.  
  766.     .pci_driver = {
  767.          .name = DRIVER_NAME,
  768.          .id_table = pciidlist,
  769.          .probe = radeon_pci_probe,
  770.          .remove = radeon_pci_remove,
  771.          .suspend = radeon_pci_suspend,
  772.          .resume = radeon_pci_resume,
  773.     },
  774.  
  775.     .name = DRIVER_NAME,
  776.     .desc = DRIVER_DESC,
  777.     .date = DRIVER_DATE,
  778.     .major = KMS_DRIVER_MAJOR,
  779.     .minor = KMS_DRIVER_MINOR,
  780.     .patchlevel = KMS_DRIVER_PATCHLEVEL,
  781. };
  782. */
  783.  
  784.  
  785. /*
  786.  * Driver load/unload
  787.  */
  788. int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  789. {
  790.     struct radeon_device *rdev;
  791.     int r;
  792.  
  793.     dbgprintf("%s\n",__FUNCTION__);
  794.  
  795.     rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  796.     if (rdev == NULL) {
  797.         return -ENOMEM;
  798.     };
  799.  
  800.     dev->dev_private = (void *)rdev;
  801.  
  802.     /* update BUS flag */
  803. //    if (drm_device_is_agp(dev)) {
  804.         flags |= RADEON_IS_AGP;
  805. //    } else if (drm_device_is_pcie(dev)) {
  806. //        flags |= RADEON_IS_PCIE;
  807. //    } else {
  808. //        flags |= RADEON_IS_PCI;
  809. //    }
  810.  
  811.     r = radeon_device_init(rdev, dev, dev->pdev, flags);
  812.     if (r) {
  813.         dbgprintf("Failed to initialize Radeon, disabling IOCTL\n");
  814. //        radeon_device_fini(rdev);
  815.         return r;
  816.     }
  817.     return 0;
  818. }
  819.  
  820. int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  821. {
  822.     struct drm_device *dev;
  823.     int ret;
  824.  
  825.     dbgprintf("%s\n",__FUNCTION__);
  826.  
  827.     dev = malloc(sizeof(*dev));
  828.     if (!dev)
  829.         return -ENOMEM;
  830.  
  831.  //   ret = pci_enable_device(pdev);
  832.  //   if (ret)
  833.  //       goto err_g1;
  834.  
  835.  //   pci_set_master(pdev);
  836.  
  837.  //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
  838.  //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
  839.  //       goto err_g2;
  840.  //   }
  841.  
  842.     dev->pdev = pdev;
  843.     dev->pci_device = pdev->device;
  844.     dev->pci_vendor = pdev->vendor;
  845.  
  846.  //   if (drm_core_check_feature(dev, DRIVER_MODESET)) {
  847.  //       pci_set_drvdata(pdev, dev);
  848.  //       ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
  849.  //       if (ret)
  850.  //           goto err_g2;
  851.  //   }
  852.  
  853.  //   if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY)))
  854.  //       goto err_g3;
  855.  
  856.  //   if (dev->driver->load) {
  857.  //       ret = dev->driver->load(dev, ent->driver_data);
  858.  //       if (ret)
  859.  //           goto err_g4;
  860.  //   }
  861.  
  862.       ret = radeon_driver_load_kms(dev, ent->driver_data );
  863.       if (ret)
  864.         goto err_g4;
  865.  
  866.  //   list_add_tail(&dev->driver_item, &driver->device_list);
  867.  
  868.  //   DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
  869.  //        driver->name, driver->major, driver->minor, driver->patchlevel,
  870.  //        driver->date, pci_name(pdev), dev->primary->index);
  871.  
  872.       set_mode(dev, 1024, 768);
  873.  
  874.     return 0;
  875.  
  876. err_g4:
  877. //    drm_put_minor(&dev->primary);
  878. //err_g3:
  879. //    if (drm_core_check_feature(dev, DRIVER_MODESET))
  880. //        drm_put_minor(&dev->control);
  881. //err_g2:
  882. //    pci_disable_device(pdev);
  883. //err_g1:
  884.     free(dev);
  885.  
  886.     return ret;
  887. }
  888.  
  889. resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
  890. {
  891.     return pci_resource_start(dev->pdev, resource);
  892. }
  893.  
  894. resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
  895. {
  896.     return pci_resource_len(dev->pdev, resource);
  897. }
  898.  
  899.  
  900. uint32_t __div64_32(uint64_t *n, uint32_t base)
  901. {
  902.         uint64_t rem = *n;
  903.         uint64_t b = base;
  904.         uint64_t res, d = 1;
  905.         uint32_t high = rem >> 32;
  906.  
  907.         /* Reduce the thing a bit first */
  908.         res = 0;
  909.         if (high >= base) {
  910.                 high /= base;
  911.                 res = (uint64_t) high << 32;
  912.                 rem -= (uint64_t) (high*base) << 32;
  913.         }
  914.  
  915.         while ((int64_t)b > 0 && b < rem) {
  916.                 b = b+b;
  917.                 d = d+d;
  918.         }
  919.  
  920.         do {
  921.                 if (rem >= b) {
  922.                         rem -= b;
  923.                         res += d;
  924.                 }
  925.                 b >>= 1;
  926.                 d >>= 1;
  927.         } while (d);
  928.  
  929.         *n = res;
  930.         return rem;
  931. }
  932.  
  933.  
  934.  
  935.