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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include "drmP.h"
  29. #include "radeon_reg.h"
  30. #include "radeon.h"
  31. #include "atom.h"
  32.  
  33. /*
  34.  * BIOS.
  35.  */
  36. static bool radeon_read_bios(struct radeon_device *rdev)
  37. {
  38.         uint8_t __iomem *bios;
  39.     size_t    size;
  40.  
  41.         rdev->bios = NULL;
  42.         /* XXX: some cards may return 0 for rom size? ddx has a workaround */
  43.         bios = pci_map_rom(rdev->pdev, &size);
  44.         if (!bios) {
  45.                 return false;
  46.         }
  47.  
  48.         if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
  49. //       pci_unmap_rom(rdev->pdev, bios);
  50.                 return false;
  51.         }
  52.         rdev->bios = kmalloc(size, GFP_KERNEL);
  53.         if (rdev->bios == NULL) {
  54. //       pci_unmap_rom(rdev->pdev, bios);
  55.                 return false;
  56.         }
  57.         memcpy(rdev->bios, bios, size);
  58. //   pci_unmap_rom(rdev->pdev, bios);
  59.         return true;
  60. }
  61.  
  62. static bool r700_read_disabled_bios(struct radeon_device *rdev)
  63. {
  64.         uint32_t viph_control;
  65.         uint32_t bus_cntl;
  66.         uint32_t d1vga_control;
  67.         uint32_t d2vga_control;
  68.         uint32_t vga_render_control;
  69.         uint32_t rom_cntl;
  70.         uint32_t cg_spll_func_cntl = 0;
  71.         uint32_t cg_spll_status;
  72.         bool r;
  73.  
  74.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  75.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  76.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  77.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  78.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  79.         rom_cntl = RREG32(R600_ROM_CNTL);
  80.  
  81.         /* disable VIP */
  82.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  83.         /* enable the rom */
  84.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  85.         /* Disable VGA mode */
  86.         WREG32(AVIVO_D1VGA_CONTROL,
  87.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  88.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  89.         WREG32(AVIVO_D2VGA_CONTROL,
  90.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  91.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  92.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  93.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  94.  
  95.         if (rdev->family == CHIP_RV730) {
  96.                 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
  97.  
  98.                 /* enable bypass mode */
  99.                 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
  100.                                                 R600_SPLL_BYPASS_EN));
  101.  
  102.                 /* wait for SPLL_CHG_STATUS to change to 1 */
  103.                 cg_spll_status = 0;
  104.                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  105.                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  106.  
  107.                 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
  108.         } else
  109.                 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
  110.  
  111.         r = radeon_read_bios(rdev);
  112.  
  113.         /* restore regs */
  114.         if (rdev->family == CHIP_RV730) {
  115.                 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
  116.  
  117.                 /* wait for SPLL_CHG_STATUS to change to 1 */
  118.                 cg_spll_status = 0;
  119.                 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
  120.                         cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
  121.         }
  122.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  123.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  124.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  125.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  126.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  127.         WREG32(R600_ROM_CNTL, rom_cntl);
  128.         return r;
  129. }
  130.  
  131. static bool r600_read_disabled_bios(struct radeon_device *rdev)
  132. {
  133.         uint32_t viph_control;
  134.         uint32_t bus_cntl;
  135.         uint32_t d1vga_control;
  136.         uint32_t d2vga_control;
  137.         uint32_t vga_render_control;
  138.         uint32_t rom_cntl;
  139.         uint32_t general_pwrmgt;
  140.         uint32_t low_vid_lower_gpio_cntl;
  141.         uint32_t medium_vid_lower_gpio_cntl;
  142.         uint32_t high_vid_lower_gpio_cntl;
  143.         uint32_t ctxsw_vid_lower_gpio_cntl;
  144.         uint32_t lower_gpio_enable;
  145.         bool r;
  146.  
  147.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  148.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  149.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  150.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  151.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  152.         rom_cntl = RREG32(R600_ROM_CNTL);
  153.         general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
  154.         low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
  155.         medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
  156.         high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
  157.         ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
  158.         lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
  159.  
  160.         /* disable VIP */
  161.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  162.         /* enable the rom */
  163.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  164.         /* Disable VGA mode */
  165.         WREG32(AVIVO_D1VGA_CONTROL,
  166.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  167.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  168.         WREG32(AVIVO_D2VGA_CONTROL,
  169.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  170.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  171.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  172.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  173.  
  174.         WREG32(R600_ROM_CNTL,
  175.                ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
  176.                 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
  177.                 R600_SCK_OVERWRITE));
  178.  
  179.         WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
  180.         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
  181.                (low_vid_lower_gpio_cntl & ~0x400));
  182.         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
  183.                (medium_vid_lower_gpio_cntl & ~0x400));
  184.         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
  185.                (high_vid_lower_gpio_cntl & ~0x400));
  186.         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
  187.                (ctxsw_vid_lower_gpio_cntl & ~0x400));
  188.         WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
  189.  
  190.         r = radeon_read_bios(rdev);
  191.  
  192.         /* restore regs */
  193.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  194.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  195.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  196.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  197.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  198.         WREG32(R600_ROM_CNTL, rom_cntl);
  199.         WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
  200.         WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
  201.         WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
  202.         WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
  203.         WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
  204.         WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
  205.         return r;
  206. }
  207.  
  208. static bool avivo_read_disabled_bios(struct radeon_device *rdev)
  209. {
  210.         uint32_t seprom_cntl1;
  211.         uint32_t viph_control;
  212.         uint32_t bus_cntl;
  213.         uint32_t d1vga_control;
  214.         uint32_t d2vga_control;
  215.         uint32_t vga_render_control;
  216.         uint32_t gpiopad_a;
  217.         uint32_t gpiopad_en;
  218.         uint32_t gpiopad_mask;
  219.         bool r;
  220.  
  221.         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  222.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  223.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  224.         d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
  225.         d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
  226.         vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
  227.         gpiopad_a = RREG32(RADEON_GPIOPAD_A);
  228.         gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
  229.         gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
  230.  
  231.         WREG32(RADEON_SEPROM_CNTL1,
  232.                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  233.                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  234.         WREG32(RADEON_GPIOPAD_A, 0);
  235.         WREG32(RADEON_GPIOPAD_EN, 0);
  236.         WREG32(RADEON_GPIOPAD_MASK, 0);
  237.  
  238.         /* disable VIP */
  239.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  240.  
  241.         /* enable the rom */
  242.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  243.  
  244.         /* Disable VGA mode */
  245.         WREG32(AVIVO_D1VGA_CONTROL,
  246.                (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  247.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  248.         WREG32(AVIVO_D2VGA_CONTROL,
  249.                (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
  250.                 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
  251.         WREG32(AVIVO_VGA_RENDER_CONTROL,
  252.                (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
  253.  
  254.         r = radeon_read_bios(rdev);
  255.  
  256.         /* restore regs */
  257.         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  258.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  259.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  260.         WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
  261.         WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
  262.         WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
  263.         WREG32(RADEON_GPIOPAD_A, gpiopad_a);
  264.         WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
  265.         WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
  266.         return r;
  267. }
  268.  
  269. static bool legacy_read_disabled_bios(struct radeon_device *rdev)
  270. {
  271.         uint32_t seprom_cntl1;
  272.         uint32_t viph_control;
  273.         uint32_t bus_cntl;
  274.         uint32_t crtc_gen_cntl;
  275.         uint32_t crtc2_gen_cntl;
  276.         uint32_t crtc_ext_cntl;
  277.         uint32_t fp2_gen_cntl;
  278.         bool r;
  279.  
  280.         seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
  281.         viph_control = RREG32(RADEON_VIPH_CONTROL);
  282.         bus_cntl = RREG32(RADEON_BUS_CNTL);
  283.         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
  284.         crtc2_gen_cntl = 0;
  285.         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
  286.         fp2_gen_cntl = 0;
  287.  
  288.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  289.                 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
  290.         }
  291.  
  292.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  293.                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  294.         }
  295.  
  296.         WREG32(RADEON_SEPROM_CNTL1,
  297.                ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
  298.                 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
  299.  
  300.         /* disable VIP */
  301.         WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
  302.  
  303.         /* enable the rom */
  304.         WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
  305.  
  306.         /* Turn off mem requests and CRTC for both controllers */
  307.         WREG32(RADEON_CRTC_GEN_CNTL,
  308.                ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
  309.                 (RADEON_CRTC_DISP_REQ_EN_B |
  310.                  RADEON_CRTC_EXT_DISP_EN)));
  311.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  312.                 WREG32(RADEON_CRTC2_GEN_CNTL,
  313.                        ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
  314.                         RADEON_CRTC2_DISP_REQ_EN_B));
  315.         }
  316.         /* Turn off CRTC */
  317.         WREG32(RADEON_CRTC_EXT_CNTL,
  318.                ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
  319.                 (RADEON_CRTC_SYNC_TRISTAT |
  320.                  RADEON_CRTC_DISPLAY_DIS)));
  321.  
  322.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  323.                 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
  324.         }
  325.  
  326.         r = radeon_read_bios(rdev);
  327.  
  328.         /* restore regs */
  329.         WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
  330.         WREG32(RADEON_VIPH_CONTROL, viph_control);
  331.         WREG32(RADEON_BUS_CNTL, bus_cntl);
  332.         WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
  333.         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  334.                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
  335.         }
  336.         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
  337.         if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
  338.                 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
  339.         }
  340.         return r;
  341. }
  342.  
  343. static bool radeon_read_disabled_bios(struct radeon_device *rdev)
  344. {
  345.         if (rdev->family >= CHIP_RV770)
  346.                 return r700_read_disabled_bios(rdev);
  347.         else if (rdev->family >= CHIP_R600)
  348.                 return r600_read_disabled_bios(rdev);
  349.         else if (rdev->family >= CHIP_RS600)
  350.                 return avivo_read_disabled_bios(rdev);
  351.         else
  352.                 return legacy_read_disabled_bios(rdev);
  353. }
  354.  
  355. bool radeon_get_bios(struct radeon_device *rdev)
  356. {
  357.         bool r;
  358.         uint16_t tmp;
  359.  
  360.         r = radeon_read_bios(rdev);
  361.         if (r == false) {
  362.                 r = radeon_read_disabled_bios(rdev);
  363.         }
  364.         if (r == false || rdev->bios == NULL) {
  365.                 DRM_ERROR("Unable to locate a BIOS ROM\n");
  366.                 rdev->bios = NULL;
  367.                 return false;
  368.         }
  369.         if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
  370.                 goto free_bios;
  371.         }
  372.  
  373.         rdev->bios_header_start = RBIOS16(0x48);
  374.         if (!rdev->bios_header_start) {
  375.                 goto free_bios;
  376.         }
  377.         tmp = rdev->bios_header_start + 4;
  378.         if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
  379.             !memcmp(rdev->bios + tmp, "MOTA", 4)) {
  380.                 rdev->is_atom_bios = true;
  381.         } else {
  382.                 rdev->is_atom_bios = false;
  383.         }
  384.  
  385.         DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
  386.         return true;
  387. free_bios:
  388.         kfree(rdev->bios);
  389.         rdev->bios = NULL;
  390.         return false;
  391. }
  392.