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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30.  
  31. /* TODO: Here are things that needs to be done :
  32.  *      - surface allocator & initializer : (bit like scratch reg) should
  33.  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34.  *        related to surface
  35.  *      - WB : write back stuff (do it bit like scratch reg things)
  36.  *      - Vblank : look at Jesse's rework and what we should do
  37.  *      - r600/r700: gart & cp
  38.  *      - cs : clean cs ioctl use bitmap & things like that.
  39.  *      - power management stuff
  40.  *      - Barrier in gart code
  41.  *      - Unmappabled vram ?
  42.  *      - TESTING, TESTING, TESTING
  43.  */
  44.  
  45. /* Initialization path:
  46.  *  We expect that acceleration initialization might fail for various
  47.  *  reasons even thought we work hard to make it works on most
  48.  *  configurations. In order to still have a working userspace in such
  49.  *  situation the init path must succeed up to the memory controller
  50.  *  initialization point. Failure before this point are considered as
  51.  *  fatal error. Here is the init callchain :
  52.  *      radeon_device_init  perform common structure, mutex initialization
  53.  *      asic_init           setup the GPU memory layout and perform all
  54.  *                          one time initialization (failure in this
  55.  *                          function are considered fatal)
  56.  *      asic_startup        setup the GPU acceleration, in order to
  57.  *                          follow guideline the first thing this
  58.  *                          function should do is setting the GPU
  59.  *                          memory controller (only MC setup failure
  60.  *                          are considered as fatal)
  61.  */
  62.  
  63. #include <linux/atomic.h>
  64. #include <linux/wait.h>
  65. #include <linux/list.h>
  66. #include <linux/kref.h>
  67. #include <linux/interval_tree.h>
  68. #include <asm/div64.h>
  69. #include <linux/fence.h>
  70.  
  71. #include <ttm/ttm_bo_api.h>
  72. #include <ttm/ttm_bo_driver.h>
  73. #include <ttm/ttm_placement.h>
  74. //#include <ttm/ttm_module.h>
  75. #include <ttm/ttm_execbuf_util.h>
  76.  
  77. #include <drm/drm_gem.h>
  78.  
  79. #include <linux/irqreturn.h>
  80. #include <linux/pci.h>
  81.  
  82. #include "radeon_family.h"
  83. #include "radeon_mode.h"
  84. #include "radeon_reg.h"
  85.  
  86. #include <syscall.h>
  87.  
  88. /*
  89.  * Modules parameters.
  90.  */
  91. extern int radeon_no_wb;
  92. extern int radeon_modeset;
  93. extern int radeon_dynclks;
  94. extern int radeon_r4xx_atom;
  95. extern int radeon_agpmode;
  96. extern int radeon_vram_limit;
  97. extern int radeon_gart_size;
  98. extern int radeon_benchmarking;
  99. extern int radeon_testing;
  100. extern int radeon_connector_table;
  101. extern int radeon_tv;
  102. extern int radeon_audio;
  103. extern int radeon_disp_priority;
  104. extern int radeon_hw_i2c;
  105. extern int radeon_pcie_gen2;
  106. extern int radeon_msi;
  107. extern int radeon_lockup_timeout;
  108. extern int radeon_fastfb;
  109. extern int radeon_dpm;
  110. extern int radeon_aspm;
  111. extern int radeon_runtime_pm;
  112. extern int radeon_hard_reset;
  113. extern int radeon_vm_size;
  114. extern int radeon_vm_block_size;
  115. extern int radeon_deep_color;
  116. extern int radeon_use_pflipirq;
  117. extern int radeon_bapm;
  118. extern int radeon_backlight;
  119.  
  120.  
  121. typedef struct pm_message {
  122.     int event;
  123. } pm_message_t;
  124.  
  125. typedef struct
  126. {
  127.   int width;
  128.   int height;
  129.   int bpp;
  130.   int freq;
  131. }videomode_t;
  132.  
  133.  
  134.  
  135. static inline u32 ioread32(const volatile void __iomem *addr)
  136. {
  137.     return in32((u32)addr);
  138. }
  139.  
  140. //static inline void iowrite32(uint32_t b, volatile void __iomem *addr)
  141. //{
  142. //    out32((u32)addr, b);
  143. //}
  144.  
  145.  
  146. /*
  147.  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  148.  * symbol;
  149.  */
  150. #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  151. #define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
  152. /* RADEON_IB_POOL_SIZE must be a power of 2 */
  153. #define RADEON_IB_POOL_SIZE             16
  154. #define RADEON_DEBUGFS_MAX_COMPONENTS   32
  155. #define RADEONFB_CONN_LIMIT             4
  156. #define RADEON_BIOS_NUM_SCRATCH         8
  157.  
  158. /* internal ring indices */
  159. /* r1xx+ has gfx CP ring */
  160. #define RADEON_RING_TYPE_GFX_INDEX  0
  161.  
  162. /* cayman has 2 compute CP rings */
  163. #define CAYMAN_RING_TYPE_CP1_INDEX 1
  164. #define CAYMAN_RING_TYPE_CP2_INDEX 2
  165.  
  166. /* R600+ has an async dma ring */
  167. #define R600_RING_TYPE_DMA_INDEX                3
  168. /* cayman add a second async dma ring */
  169. #define CAYMAN_RING_TYPE_DMA1_INDEX             4
  170.  
  171. /* R600+ */
  172. #define R600_RING_TYPE_UVD_INDEX        5
  173.  
  174. /* TN+ */
  175. #define TN_RING_TYPE_VCE1_INDEX                 6
  176. #define TN_RING_TYPE_VCE2_INDEX                 7
  177.  
  178. /* max number of rings */
  179. #define RADEON_NUM_RINGS                        8
  180.  
  181. /* number of hw syncs before falling back on blocking */
  182. #define RADEON_NUM_SYNCS                        4
  183.  
  184. /* hardcode those limit for now */
  185. #define RADEON_VA_IB_OFFSET                     (1 << 20)
  186. #define RADEON_VA_RESERVED_SIZE         (8 << 20)
  187. #define RADEON_IB_VM_MAX_SIZE           (64 << 10)
  188.  
  189. /* hard reset data */
  190. #define RADEON_ASIC_RESET_DATA                  0x39d5e86b
  191.  
  192. /* reset flags */
  193. #define RADEON_RESET_GFX                        (1 << 0)
  194. #define RADEON_RESET_COMPUTE                    (1 << 1)
  195. #define RADEON_RESET_DMA                        (1 << 2)
  196. #define RADEON_RESET_CP                         (1 << 3)
  197. #define RADEON_RESET_GRBM                       (1 << 4)
  198. #define RADEON_RESET_DMA1                       (1 << 5)
  199. #define RADEON_RESET_RLC                        (1 << 6)
  200. #define RADEON_RESET_SEM                        (1 << 7)
  201. #define RADEON_RESET_IH                         (1 << 8)
  202. #define RADEON_RESET_VMC                        (1 << 9)
  203. #define RADEON_RESET_MC                         (1 << 10)
  204. #define RADEON_RESET_DISPLAY                    (1 << 11)
  205.  
  206. /* CG block flags */
  207. #define RADEON_CG_BLOCK_GFX                     (1 << 0)
  208. #define RADEON_CG_BLOCK_MC                      (1 << 1)
  209. #define RADEON_CG_BLOCK_SDMA                    (1 << 2)
  210. #define RADEON_CG_BLOCK_UVD                     (1 << 3)
  211. #define RADEON_CG_BLOCK_VCE                     (1 << 4)
  212. #define RADEON_CG_BLOCK_HDP                     (1 << 5)
  213. #define RADEON_CG_BLOCK_BIF                     (1 << 6)
  214.  
  215. /* CG flags */
  216. #define RADEON_CG_SUPPORT_GFX_MGCG              (1 << 0)
  217. #define RADEON_CG_SUPPORT_GFX_MGLS              (1 << 1)
  218. #define RADEON_CG_SUPPORT_GFX_CGCG              (1 << 2)
  219. #define RADEON_CG_SUPPORT_GFX_CGLS              (1 << 3)
  220. #define RADEON_CG_SUPPORT_GFX_CGTS              (1 << 4)
  221. #define RADEON_CG_SUPPORT_GFX_CGTS_LS           (1 << 5)
  222. #define RADEON_CG_SUPPORT_GFX_CP_LS             (1 << 6)
  223. #define RADEON_CG_SUPPORT_GFX_RLC_LS            (1 << 7)
  224. #define RADEON_CG_SUPPORT_MC_LS                 (1 << 8)
  225. #define RADEON_CG_SUPPORT_MC_MGCG               (1 << 9)
  226. #define RADEON_CG_SUPPORT_SDMA_LS               (1 << 10)
  227. #define RADEON_CG_SUPPORT_SDMA_MGCG             (1 << 11)
  228. #define RADEON_CG_SUPPORT_BIF_LS                (1 << 12)
  229. #define RADEON_CG_SUPPORT_UVD_MGCG              (1 << 13)
  230. #define RADEON_CG_SUPPORT_VCE_MGCG              (1 << 14)
  231. #define RADEON_CG_SUPPORT_HDP_LS                (1 << 15)
  232. #define RADEON_CG_SUPPORT_HDP_MGCG              (1 << 16)
  233.  
  234. /* PG flags */
  235. #define RADEON_PG_SUPPORT_GFX_PG                (1 << 0)
  236. #define RADEON_PG_SUPPORT_GFX_SMG               (1 << 1)
  237. #define RADEON_PG_SUPPORT_GFX_DMG               (1 << 2)
  238. #define RADEON_PG_SUPPORT_UVD                   (1 << 3)
  239. #define RADEON_PG_SUPPORT_VCE                   (1 << 4)
  240. #define RADEON_PG_SUPPORT_CP                    (1 << 5)
  241. #define RADEON_PG_SUPPORT_GDS                   (1 << 6)
  242. #define RADEON_PG_SUPPORT_RLC_SMU_HS            (1 << 7)
  243. #define RADEON_PG_SUPPORT_SDMA                  (1 << 8)
  244. #define RADEON_PG_SUPPORT_ACP                   (1 << 9)
  245. #define RADEON_PG_SUPPORT_SAMU                  (1 << 10)
  246.  
  247. /* max cursor sizes (in pixels) */
  248. #define CURSOR_WIDTH 64
  249. #define CURSOR_HEIGHT 64
  250.  
  251. #define CIK_CURSOR_WIDTH 128
  252. #define CIK_CURSOR_HEIGHT 128
  253.  
  254. /*
  255.  * Errata workarounds.
  256.  */
  257. enum radeon_pll_errata {
  258.     CHIP_ERRATA_R300_CG             = 0x00000001,
  259.     CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  260.     CHIP_ERRATA_PLL_DELAY           = 0x00000004
  261. };
  262.  
  263.  
  264. struct radeon_device;
  265.  
  266.  
  267. /*
  268.  * BIOS.
  269.  */
  270. bool radeon_get_bios(struct radeon_device *rdev);
  271.  
  272. /*
  273.  * Dummy page
  274.  */
  275. struct radeon_dummy_page {
  276.         struct page     *page;
  277.         dma_addr_t      addr;
  278. };
  279. int radeon_dummy_page_init(struct radeon_device *rdev);
  280. void radeon_dummy_page_fini(struct radeon_device *rdev);
  281.  
  282.  
  283. /*
  284.  * Clocks
  285.  */
  286. struct radeon_clock {
  287.         struct radeon_pll p1pll;
  288.         struct radeon_pll p2pll;
  289.         struct radeon_pll dcpll;
  290.         struct radeon_pll spll;
  291.         struct radeon_pll mpll;
  292.         /* 10 Khz units */
  293.         uint32_t default_mclk;
  294.         uint32_t default_sclk;
  295.         uint32_t default_dispclk;
  296.         uint32_t current_dispclk;
  297.         uint32_t dp_extclk;
  298.         uint32_t max_pixel_clock;
  299. };
  300.  
  301. /*
  302.  * Power management
  303.  */
  304. int radeon_pm_init(struct radeon_device *rdev);
  305. int radeon_pm_late_init(struct radeon_device *rdev);
  306. void radeon_pm_fini(struct radeon_device *rdev);
  307. void radeon_pm_compute_clocks(struct radeon_device *rdev);
  308. void radeon_pm_suspend(struct radeon_device *rdev);
  309. void radeon_pm_resume(struct radeon_device *rdev);
  310. void radeon_combios_get_power_modes(struct radeon_device *rdev);
  311. void radeon_atombios_get_power_modes(struct radeon_device *rdev);
  312. int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
  313.                                    u8 clock_type,
  314.                                    u32 clock,
  315.                                    bool strobe_mode,
  316.                                    struct atom_clock_dividers *dividers);
  317. int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
  318.                                         u32 clock,
  319.                                         bool strobe_mode,
  320.                                         struct atom_mpll_param *mpll_param);
  321. void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
  322. int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
  323.                                           u16 voltage_level, u8 voltage_type,
  324.                                           u32 *gpio_value, u32 *gpio_mask);
  325. void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
  326.                                          u32 eng_clock, u32 mem_clock);
  327. int radeon_atom_get_voltage_step(struct radeon_device *rdev,
  328.                                  u8 voltage_type, u16 *voltage_step);
  329. int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
  330.                              u16 voltage_id, u16 *voltage);
  331. int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
  332.                                                       u16 *voltage,
  333.                                                       u16 leakage_idx);
  334. int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
  335.                                           u16 *leakage_id);
  336. int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
  337.                                                          u16 *vddc, u16 *vddci,
  338.                                                          u16 virtual_voltage_id,
  339.                                                          u16 vbios_voltage_id);
  340. int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
  341.                                 u16 virtual_voltage_id,
  342.                                 u16 *voltage);
  343. int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
  344.                                       u8 voltage_type,
  345.                                       u16 nominal_voltage,
  346.                                       u16 *true_voltage);
  347. int radeon_atom_get_min_voltage(struct radeon_device *rdev,
  348.                                 u8 voltage_type, u16 *min_voltage);
  349. int radeon_atom_get_max_voltage(struct radeon_device *rdev,
  350.                                 u8 voltage_type, u16 *max_voltage);
  351. int radeon_atom_get_voltage_table(struct radeon_device *rdev,
  352.                                   u8 voltage_type, u8 voltage_mode,
  353.                                   struct atom_voltage_table *voltage_table);
  354. bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
  355.                                  u8 voltage_type, u8 voltage_mode);
  356. int radeon_atom_get_svi2_info(struct radeon_device *rdev,
  357.                               u8 voltage_type,
  358.                               u8 *svd_gpio_id, u8 *svc_gpio_id);
  359. void radeon_atom_update_memory_dll(struct radeon_device *rdev,
  360.                                    u32 mem_clock);
  361. void radeon_atom_set_ac_timing(struct radeon_device *rdev,
  362.                                u32 mem_clock);
  363. int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
  364.                                   u8 module_index,
  365.                                   struct atom_mc_reg_table *reg_table);
  366. int radeon_atom_get_memory_info(struct radeon_device *rdev,
  367.                                 u8 module_index, struct atom_memory_info *mem_info);
  368. int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
  369.                                      bool gddr5, u8 module_index,
  370.                                      struct atom_memory_clock_range_table *mclk_range_table);
  371. int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
  372.                              u16 voltage_id, u16 *voltage);
  373. void rs690_pm_info(struct radeon_device *rdev);
  374. extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
  375.                                     unsigned *bankh, unsigned *mtaspect,
  376.                                     unsigned *tile_split);
  377.  
  378. /*
  379.  * Fences.
  380.  */
  381. struct radeon_fence_driver {
  382.         struct radeon_device            *rdev;
  383.         uint32_t                        scratch_reg;
  384.         uint64_t                        gpu_addr;
  385.         volatile uint32_t               *cpu_addr;
  386.         /* sync_seq is protected by ring emission lock */
  387.         uint64_t                        sync_seq[RADEON_NUM_RINGS];
  388.         atomic64_t                      last_seq;
  389.         bool                            initialized, delayed_irq;
  390.         struct delayed_work             lockup_work;
  391. };
  392.  
  393. struct radeon_fence {
  394.         struct fence            base;
  395.  
  396.     struct radeon_device   *rdev;
  397.         uint64_t                        seq;
  398.         /* RB, DMA, etc. */
  399.         unsigned                        ring;
  400.         bool                    is_vm_update;
  401.  
  402.         wait_queue_t            fence_wake;
  403. };
  404.  
  405. int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
  406. int radeon_fence_driver_init(struct radeon_device *rdev);
  407. void radeon_fence_driver_fini(struct radeon_device *rdev);
  408. void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
  409. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
  410. void radeon_fence_process(struct radeon_device *rdev, int ring);
  411. bool radeon_fence_signaled(struct radeon_fence *fence);
  412. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  413. int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
  414. int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
  415. int radeon_fence_wait_any(struct radeon_device *rdev,
  416.                           struct radeon_fence **fences,
  417.                           bool intr);
  418. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  419. void radeon_fence_unref(struct radeon_fence **fence);
  420. unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
  421. bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
  422. void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
  423. static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
  424.                                                       struct radeon_fence *b)
  425. {
  426.         if (!a) {
  427.                 return b;
  428.         }
  429.  
  430.         if (!b) {
  431.                 return a;
  432.         }
  433.  
  434.         BUG_ON(a->ring != b->ring);
  435.  
  436.         if (a->seq > b->seq) {
  437.                 return a;
  438.         } else {
  439.                 return b;
  440.         }
  441. }
  442.  
  443. static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
  444.                                            struct radeon_fence *b)
  445. {
  446.         if (!a) {
  447.                 return false;
  448.         }
  449.  
  450.         if (!b) {
  451.                 return true;
  452.         }
  453.  
  454.         BUG_ON(a->ring != b->ring);
  455.  
  456.         return a->seq < b->seq;
  457. }
  458.  
  459. /*
  460.  * Tiling registers
  461.  */
  462. struct radeon_surface_reg {
  463.         struct radeon_bo *bo;
  464. };
  465.  
  466. #define RADEON_GEM_MAX_SURFACES 8
  467.  
  468. /*
  469.  * TTM.
  470.  */
  471. struct radeon_mman {
  472.         struct ttm_bo_global_ref        bo_global_ref;
  473.         struct drm_global_reference     mem_global_ref;
  474.         struct ttm_bo_device            bdev;
  475.         bool                            mem_global_referenced;
  476.         bool                            initialized;
  477.  
  478. #if defined(CONFIG_DEBUG_FS)
  479.         struct dentry                   *vram;
  480.         struct dentry                   *gtt;
  481. #endif
  482. };
  483.  
  484. struct radeon_bo_list {
  485.         struct radeon_bo                *robj;
  486.         struct ttm_validate_buffer      tv;
  487.         uint64_t                        gpu_offset;
  488.         unsigned                        prefered_domains;
  489.         unsigned                        allowed_domains;
  490.         uint32_t                        tiling_flags;
  491. };
  492.  
  493. /* bo virtual address in a specific vm */
  494. struct radeon_bo_va {
  495.         /* protected by bo being reserved */
  496.         struct list_head                bo_list;
  497.         uint32_t                        flags;
  498.         uint64_t                        addr;
  499.         struct radeon_fence             *last_pt_update;
  500.         unsigned                        ref_count;
  501.  
  502.         /* protected by vm mutex */
  503.         struct interval_tree_node       it;
  504.         struct list_head                vm_status;
  505.  
  506.         /* constant after initialization */
  507.         struct radeon_vm                *vm;
  508.         struct radeon_bo                *bo;
  509. };
  510.  
  511. struct radeon_bo {
  512.         /* Protected by gem.mutex */
  513.         struct list_head                list;
  514.         /* Protected by tbo.reserved */
  515.         u32                             initial_domain;
  516.         struct ttm_place                placements[4];
  517.     struct ttm_placement        placement;
  518.     struct ttm_buffer_object    tbo;
  519.         struct ttm_bo_kmap_obj          kmap;
  520.         u32                             flags;
  521.     unsigned                    pin_count;
  522.     void                       *kptr;
  523.     u32                         tiling_flags;
  524.     u32                         pitch;
  525.     int                         surface_reg;
  526.         /* list of all virtual address to which this bo
  527.          * is associated to
  528.          */
  529.         struct list_head                va;
  530.         /* Constant after initialization */
  531.         struct radeon_device            *rdev;
  532.         struct drm_gem_object           gem_base;
  533.  
  534.         pid_t                           pid;
  535.  
  536.         struct radeon_mn                *mn;
  537. };
  538. #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
  539.  
  540. int radeon_gem_debugfs_init(struct radeon_device *rdev);
  541.  
  542. /* sub-allocation manager, it has to be protected by another lock.
  543.  * By conception this is an helper for other part of the driver
  544.  * like the indirect buffer or semaphore, which both have their
  545.  * locking.
  546.  *
  547.  * Principe is simple, we keep a list of sub allocation in offset
  548.  * order (first entry has offset == 0, last entry has the highest
  549.  * offset).
  550.  *
  551.  * When allocating new object we first check if there is room at
  552.  * the end total_size - (last_object_offset + last_object_size) >=
  553.  * alloc_size. If so we allocate new object there.
  554.  *
  555.  * When there is not enough room at the end, we start waiting for
  556.  * each sub object until we reach object_offset+object_size >=
  557.  * alloc_size, this object then become the sub object we return.
  558.  *
  559.  * Alignment can't be bigger than page size.
  560.  *
  561.  * Hole are not considered for allocation to keep things simple.
  562.  * Assumption is that there won't be hole (all object on same
  563.  * alignment).
  564.  */
  565. struct radeon_sa_manager {
  566.         wait_queue_head_t       wq;
  567.         struct radeon_bo        *bo;
  568.         struct list_head        *hole;
  569.         struct list_head        flist[RADEON_NUM_RINGS];
  570.         struct list_head        olist;
  571.         unsigned                size;
  572.         uint64_t                gpu_addr;
  573.         void                    *cpu_ptr;
  574.         uint32_t                domain;
  575.         uint32_t                align;
  576. };
  577.  
  578. struct radeon_sa_bo;
  579.  
  580. /* sub-allocation buffer */
  581. struct radeon_sa_bo {
  582.         struct list_head                olist;
  583.         struct list_head                flist;
  584.         struct radeon_sa_manager        *manager;
  585.         unsigned                        soffset;
  586.         unsigned                        eoffset;
  587.         struct radeon_fence             *fence;
  588. };
  589.  
  590. /*
  591.  * GEM objects.
  592.  */
  593. struct radeon_gem {
  594.         struct mutex            mutex;
  595.         struct list_head        objects;
  596. };
  597.  
  598. int radeon_gem_init(struct radeon_device *rdev);
  599. void radeon_gem_fini(struct radeon_device *rdev);
  600. int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
  601.                              int alignment, int initial_domain,
  602.                                 u32 flags, bool kernel,
  603.                              struct drm_gem_object **obj);
  604.  
  605. int radeon_mode_dumb_create(struct drm_file *file_priv,
  606.                             struct drm_device *dev,
  607.                             struct drm_mode_create_dumb *args);
  608. int radeon_mode_dumb_mmap(struct drm_file *filp,
  609.                           struct drm_device *dev,
  610.                           uint32_t handle, uint64_t *offset_p);
  611.  
  612. /*
  613.  * Semaphores.
  614.  */
  615. struct radeon_semaphore {
  616.         struct radeon_sa_bo             *sa_bo;
  617.         signed                          waiters;
  618.         uint64_t                        gpu_addr;
  619. };
  620.  
  621. int radeon_semaphore_create(struct radeon_device *rdev,
  622.                             struct radeon_semaphore **semaphore);
  623. bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
  624.                                   struct radeon_semaphore *semaphore);
  625. bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
  626.                                 struct radeon_semaphore *semaphore);
  627. void radeon_semaphore_free(struct radeon_device *rdev,
  628.                            struct radeon_semaphore **semaphore,
  629.                            struct radeon_fence *fence);
  630.  
  631. /*
  632.  * Synchronization
  633.  */
  634. struct radeon_sync {
  635.         struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
  636.         struct radeon_fence     *sync_to[RADEON_NUM_RINGS];
  637.         struct radeon_fence     *last_vm_update;
  638. };
  639.  
  640. void radeon_sync_create(struct radeon_sync *sync);
  641. void radeon_sync_fence(struct radeon_sync *sync,
  642.                               struct radeon_fence *fence);
  643. int radeon_sync_resv(struct radeon_device *rdev,
  644.                      struct radeon_sync *sync,
  645.                      struct reservation_object *resv,
  646.                      bool shared);
  647. int radeon_sync_rings(struct radeon_device *rdev,
  648.                       struct radeon_sync *sync,
  649.                                 int waiting_ring);
  650. void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
  651.                            struct radeon_fence *fence);
  652.  
  653. /*
  654.  * GART structures, functions & helpers
  655.  */
  656. struct radeon_mc;
  657.  
  658. #define RADEON_GPU_PAGE_SIZE 4096
  659. #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
  660. #define RADEON_GPU_PAGE_SHIFT 12
  661. #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
  662.  
  663. #define RADEON_GART_PAGE_DUMMY  0
  664. #define RADEON_GART_PAGE_VALID  (1 << 0)
  665. #define RADEON_GART_PAGE_READ   (1 << 1)
  666. #define RADEON_GART_PAGE_WRITE  (1 << 2)
  667. #define RADEON_GART_PAGE_SNOOP  (1 << 3)
  668.  
  669. struct radeon_gart {
  670.     dma_addr_t          table_addr;
  671.         struct radeon_bo                *robj;
  672.         void                            *ptr;
  673.     unsigned            num_gpu_pages;
  674.     unsigned            num_cpu_pages;
  675.     unsigned            table_size;
  676.     struct page         **pages;
  677.     dma_addr_t          *pages_addr;
  678.     bool                ready;
  679. };
  680.  
  681. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  682. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  683. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  684. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  685. int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  686. void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
  687. int radeon_gart_init(struct radeon_device *rdev);
  688. void radeon_gart_fini(struct radeon_device *rdev);
  689. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  690.                         int pages);
  691. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  692.                      int pages, struct page **pagelist,
  693.                      dma_addr_t *dma_addr, uint32_t flags);
  694.  
  695.  
  696. /*
  697.  * GPU MC structures, functions & helpers
  698.  */
  699. struct radeon_mc {
  700.     resource_size_t     aper_size;
  701.     resource_size_t     aper_base;
  702.     resource_size_t     agp_base;
  703.         /* for some chips with <= 32MB we need to lie
  704.          * about vram size near mc fb location */
  705.         u64                     mc_vram_size;
  706.         u64                     visible_vram_size;
  707.         u64                     gtt_size;
  708.         u64                     gtt_start;
  709.         u64                     gtt_end;
  710.         u64                     vram_start;
  711.         u64                     vram_end;
  712.     unsigned            vram_width;
  713.         u64                     real_vram_size;
  714.     int                 vram_mtrr;
  715.     bool                vram_is_ddr;
  716.         bool                    igp_sideport_enabled;
  717.         u64                     gtt_base_align;
  718.         u64                     mc_mask;
  719. };
  720.  
  721. bool radeon_combios_sideport_present(struct radeon_device *rdev);
  722. bool radeon_atombios_sideport_present(struct radeon_device *rdev);
  723.  
  724. /*
  725.  * GPU scratch registers structures, functions & helpers
  726.  */
  727. struct radeon_scratch {
  728.     unsigned        num_reg;
  729.         uint32_t                reg_base;
  730.     bool            free[32];
  731.     uint32_t        reg[32];
  732. };
  733.  
  734. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  735. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  736.  
  737. /*
  738.  * GPU doorbell structures, functions & helpers
  739.  */
  740. #define RADEON_MAX_DOORBELLS 1024       /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
  741.  
  742. struct radeon_doorbell {
  743.         /* doorbell mmio */
  744.         resource_size_t                 base;
  745.         resource_size_t                 size;
  746.         u32 __iomem             *ptr;
  747.         u32                     num_doorbells;  /* Number of doorbells actually reserved for radeon. */
  748.         unsigned long           used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
  749. };
  750.  
  751. int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
  752. void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
  753. void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
  754.                                   phys_addr_t *aperture_base,
  755.                                   size_t *aperture_size,
  756.                                   size_t *start_offset);
  757.  
  758. /*
  759.  * IRQS.
  760.  */
  761. struct r500_irq_stat_regs {
  762.         u32 disp_int;
  763.         u32 hdmi0_status;
  764. };
  765.  
  766. struct r600_irq_stat_regs {
  767.         u32 disp_int;
  768.         u32 disp_int_cont;
  769.         u32 disp_int_cont2;
  770.         u32 d1grph_int;
  771.         u32 d2grph_int;
  772.         u32 hdmi0_status;
  773.         u32 hdmi1_status;
  774. };
  775.  
  776. struct evergreen_irq_stat_regs {
  777.         u32 disp_int;
  778.         u32 disp_int_cont;
  779.         u32 disp_int_cont2;
  780.         u32 disp_int_cont3;
  781.         u32 disp_int_cont4;
  782.         u32 disp_int_cont5;
  783.         u32 d1grph_int;
  784.         u32 d2grph_int;
  785.         u32 d3grph_int;
  786.         u32 d4grph_int;
  787.         u32 d5grph_int;
  788.         u32 d6grph_int;
  789.         u32 afmt_status1;
  790.         u32 afmt_status2;
  791.         u32 afmt_status3;
  792.         u32 afmt_status4;
  793.         u32 afmt_status5;
  794.         u32 afmt_status6;
  795. };
  796.  
  797. struct cik_irq_stat_regs {
  798.         u32 disp_int;
  799.         u32 disp_int_cont;
  800.         u32 disp_int_cont2;
  801.         u32 disp_int_cont3;
  802.         u32 disp_int_cont4;
  803.         u32 disp_int_cont5;
  804.         u32 disp_int_cont6;
  805.         u32 d1grph_int;
  806.         u32 d2grph_int;
  807.         u32 d3grph_int;
  808.         u32 d4grph_int;
  809.         u32 d5grph_int;
  810.         u32 d6grph_int;
  811. };
  812.  
  813. union radeon_irq_stat_regs {
  814.         struct r500_irq_stat_regs r500;
  815.         struct r600_irq_stat_regs r600;
  816.         struct evergreen_irq_stat_regs evergreen;
  817.         struct cik_irq_stat_regs cik;
  818. };
  819.  
  820. struct radeon_irq {
  821.         bool            installed;
  822.         spinlock_t                      lock;
  823.         atomic_t                        ring_int[RADEON_NUM_RINGS];
  824.         bool                            crtc_vblank_int[RADEON_MAX_CRTCS];
  825.         atomic_t                        pflip[RADEON_MAX_CRTCS];
  826.     wait_queue_head_t   vblank_queue;
  827.         bool                            hpd[RADEON_MAX_HPD_PINS];
  828.         bool                            afmt[RADEON_MAX_AFMT_BLOCKS];
  829.         union radeon_irq_stat_regs stat_regs;
  830.         bool                            dpm_thermal;
  831. };
  832.  
  833. int radeon_irq_kms_init(struct radeon_device *rdev);
  834. void radeon_irq_kms_fini(struct radeon_device *rdev);
  835. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
  836. bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
  837. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
  838. void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
  839. void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
  840. void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
  841. void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
  842. void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
  843. void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
  844.  
  845. /*
  846.  * CP & rings.
  847.  */
  848.  
  849. struct radeon_ib {
  850.         struct radeon_sa_bo             *sa_bo;
  851.         uint32_t                length_dw;
  852.     uint64_t            gpu_addr;
  853.         uint32_t                *ptr;
  854.         int                             ring;
  855.         struct radeon_fence     *fence;
  856.         struct radeon_vm                *vm;
  857.         bool                    is_const_ib;
  858.         struct radeon_sync              sync;
  859. };
  860.  
  861. struct radeon_ring {
  862.         struct radeon_bo        *ring_obj;
  863.         volatile uint32_t       *ring;
  864.         unsigned                rptr_offs;
  865.         unsigned                rptr_save_reg;
  866.         u64                     next_rptr_gpu_addr;
  867.         volatile u32            *next_rptr_cpu_addr;
  868.         unsigned                wptr;
  869.         unsigned                wptr_old;
  870.         unsigned                ring_size;
  871.         unsigned                ring_free_dw;
  872.         int                     count_dw;
  873.         atomic_t                last_rptr;
  874.         atomic64_t              last_activity;
  875.         uint64_t                gpu_addr;
  876.         uint32_t                align_mask;
  877.         uint32_t                ptr_mask;
  878.         bool                    ready;
  879.         u32                     nop;
  880.         u32                     idx;
  881.         u64                     last_semaphore_signal_addr;
  882.         u64                     last_semaphore_wait_addr;
  883.         /* for CIK queues */
  884.         u32 me;
  885.         u32 pipe;
  886.         u32 queue;
  887.         struct radeon_bo        *mqd_obj;
  888.         u32 doorbell_index;
  889.         unsigned                wptr_offs;
  890. };
  891.  
  892. struct radeon_mec {
  893.         struct radeon_bo        *hpd_eop_obj;
  894.         u64                     hpd_eop_gpu_addr;
  895.         u32 num_pipe;
  896.         u32 num_mec;
  897.         u32 num_queue;
  898. };
  899.  
  900. /*
  901.  * VM
  902.  */
  903.  
  904. /* maximum number of VMIDs */
  905. #define RADEON_NUM_VM   16
  906.  
  907. /* number of entries in page table */
  908. #define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
  909.  
  910. /* PTBs (Page Table Blocks) need to be aligned to 32K */
  911. #define RADEON_VM_PTB_ALIGN_SIZE   32768
  912. #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
  913. #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
  914.  
  915. #define R600_PTE_VALID          (1 << 0)
  916. #define R600_PTE_SYSTEM         (1 << 1)
  917. #define R600_PTE_SNOOPED        (1 << 2)
  918. #define R600_PTE_READABLE       (1 << 5)
  919. #define R600_PTE_WRITEABLE      (1 << 6)
  920.  
  921. /* PTE (Page Table Entry) fragment field for different page sizes */
  922. #define R600_PTE_FRAG_4KB       (0 << 7)
  923. #define R600_PTE_FRAG_64KB      (4 << 7)
  924. #define R600_PTE_FRAG_256KB     (6 << 7)
  925.  
  926. /* flags needed to be set so we can copy directly from the GART table */
  927. #define R600_PTE_GART_MASK      ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
  928.                                   R600_PTE_SYSTEM | R600_PTE_VALID )
  929.  
  930. struct radeon_vm_pt {
  931.         struct radeon_bo                *bo;
  932.         uint64_t                        addr;
  933. };
  934.  
  935. struct radeon_vm_id {
  936.         unsigned                id;
  937.         uint64_t                pd_gpu_addr;
  938.         /* last flushed PD/PT update */
  939.         struct radeon_fence     *flushed_updates;
  940.         /* last use of vmid */
  941.         struct radeon_fence     *last_id_use;
  942. };
  943.  
  944. struct radeon_vm {
  945.         struct mutex            mutex;
  946.  
  947.         struct rb_root                  va;
  948.  
  949.         /* protecting invalidated and freed */
  950.         spinlock_t              status_lock;
  951.  
  952.         /* BOs moved, but not yet updated in the PT */
  953.         struct list_head                invalidated;
  954.  
  955.         /* BOs freed, but not yet updated in the PT */
  956.         struct list_head                freed;
  957.  
  958.         /* contains the page directory */
  959.         struct radeon_bo                *page_directory;
  960.         unsigned                        max_pde_used;
  961.  
  962.         /* array of page tables, one for each page directory entry */
  963.         struct radeon_vm_pt             *page_tables;
  964.  
  965.         struct radeon_bo_va             *ib_bo_va;
  966.  
  967.         /* for id and flush management per ring */
  968.         struct radeon_vm_id     ids[RADEON_NUM_RINGS];
  969. };
  970.  
  971. struct radeon_vm_manager {
  972.         struct radeon_fence             *active[RADEON_NUM_VM];
  973.         uint32_t                        max_pfn;
  974.         /* number of VMIDs */
  975.         unsigned                        nvm;
  976.         /* vram base address for page table entry  */
  977.         u64                             vram_base_offset;
  978.         /* is vm enabled? */
  979.         bool                            enabled;
  980.         /* for hw to save the PD addr on suspend/resume */
  981.         uint32_t                        saved_table_addr[RADEON_NUM_VM];
  982. };
  983.  
  984. /*
  985.  * file private structure
  986.  */
  987. struct radeon_fpriv {
  988.         struct radeon_vm                vm;
  989. };
  990.  
  991. /*
  992.  * R6xx+ IH ring
  993.  */
  994. struct r600_ih {
  995.         struct radeon_bo        *ring_obj;
  996.         volatile uint32_t       *ring;
  997.     unsigned            rptr;
  998.     unsigned            ring_size;
  999.     uint64_t            gpu_addr;
  1000.     uint32_t            ptr_mask;
  1001.         atomic_t                lock;
  1002.     bool                enabled;
  1003. };
  1004.  
  1005. /*
  1006.  * RLC stuff
  1007.  */
  1008. #include "clearstate_defs.h"
  1009.  
  1010. struct radeon_rlc {
  1011.         /* for power gating */
  1012.         struct radeon_bo        *save_restore_obj;
  1013.         uint64_t                save_restore_gpu_addr;
  1014.         volatile uint32_t       *sr_ptr;
  1015.         const u32               *reg_list;
  1016.         u32                     reg_list_size;
  1017.         /* for clear state */
  1018.         struct radeon_bo        *clear_state_obj;
  1019.         uint64_t                clear_state_gpu_addr;
  1020.         volatile uint32_t       *cs_ptr;
  1021.         const struct cs_section_def   *cs_data;
  1022.         u32                     clear_state_size;
  1023.         /* for cp tables */
  1024.         struct radeon_bo        *cp_table_obj;
  1025.         uint64_t                cp_table_gpu_addr;
  1026.         volatile uint32_t       *cp_table_ptr;
  1027.         u32                     cp_table_size;
  1028. };
  1029.  
  1030. int radeon_ib_get(struct radeon_device *rdev, int ring,
  1031.                   struct radeon_ib *ib, struct radeon_vm *vm,
  1032.                   unsigned size);
  1033. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
  1034. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
  1035.                        struct radeon_ib *const_ib, bool hdp_flush);
  1036. int radeon_ib_pool_init(struct radeon_device *rdev);
  1037. void radeon_ib_pool_fini(struct radeon_device *rdev);
  1038. int radeon_ib_ring_tests(struct radeon_device *rdev);
  1039. /* Ring access between begin & end cannot sleep */
  1040. bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
  1041.                                       struct radeon_ring *ring);
  1042. void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
  1043. int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
  1044. int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
  1045. void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
  1046.                         bool hdp_flush);
  1047. void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
  1048.                                bool hdp_flush);
  1049. void radeon_ring_undo(struct radeon_ring *ring);
  1050. void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
  1051. int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  1052. void radeon_ring_lockup_update(struct radeon_device *rdev,
  1053.                                struct radeon_ring *ring);
  1054. bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
  1055. unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
  1056.                             uint32_t **data);
  1057. int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
  1058.                         unsigned size, uint32_t *data);
  1059. int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
  1060.                      unsigned rptr_offs, u32 nop);
  1061. void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
  1062.  
  1063.  
  1064. /* r600 async dma */
  1065. void r600_dma_stop(struct radeon_device *rdev);
  1066. int r600_dma_resume(struct radeon_device *rdev);
  1067. void r600_dma_fini(struct radeon_device *rdev);
  1068.  
  1069. void cayman_dma_stop(struct radeon_device *rdev);
  1070. int cayman_dma_resume(struct radeon_device *rdev);
  1071. void cayman_dma_fini(struct radeon_device *rdev);
  1072.  
  1073. /*
  1074.  * CS.
  1075.  */
  1076. struct radeon_cs_chunk {
  1077.         uint32_t                length_dw;
  1078.         uint32_t                *kdata;
  1079.         void __user *user_ptr;
  1080. };
  1081.  
  1082. struct radeon_cs_parser {
  1083.         struct device           *dev;
  1084.         struct radeon_device    *rdev;
  1085.         struct drm_file         *filp;
  1086.         /* chunks */
  1087.         unsigned                nchunks;
  1088.         struct radeon_cs_chunk  *chunks;
  1089.         uint64_t                *chunks_array;
  1090.         /* IB */
  1091.         unsigned                idx;
  1092.         /* relocations */
  1093.         unsigned                nrelocs;
  1094.         struct radeon_bo_list   *relocs;
  1095.         struct radeon_bo_list   *vm_bos;
  1096.         struct list_head        validated;
  1097.         unsigned                dma_reloc_idx;
  1098.         /* indices of various chunks */
  1099.         struct radeon_cs_chunk  *chunk_ib;
  1100.         struct radeon_cs_chunk  *chunk_relocs;
  1101.         struct radeon_cs_chunk  *chunk_flags;
  1102.         struct radeon_cs_chunk  *chunk_const_ib;
  1103.         struct radeon_ib        ib;
  1104.         struct radeon_ib        const_ib;
  1105.         void                    *track;
  1106.         unsigned                family;
  1107.         int parser_error;
  1108.         u32                     cs_flags;
  1109.         u32                     ring;
  1110.         s32                     priority;
  1111.         struct ww_acquire_ctx   ticket;
  1112. };
  1113.  
  1114. static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  1115. {
  1116.         struct radeon_cs_chunk *ibc = p->chunk_ib;
  1117.  
  1118.         if (ibc->kdata)
  1119.                 return ibc->kdata[idx];
  1120.         return p->ib.ptr[idx];
  1121. }
  1122.  
  1123.  
  1124. struct radeon_cs_packet {
  1125.         unsigned        idx;
  1126.         unsigned        type;
  1127.         unsigned        reg;
  1128.         unsigned        opcode;
  1129.         int             count;
  1130.         unsigned        one_reg_wr;
  1131. };
  1132.  
  1133. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  1134.                                       struct radeon_cs_packet *pkt,
  1135.                                       unsigned idx, unsigned reg);
  1136. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  1137.                                       struct radeon_cs_packet *pkt);
  1138.  
  1139.  
  1140. /*
  1141.  * AGP
  1142.  */
  1143. int radeon_agp_init(struct radeon_device *rdev);
  1144. void radeon_agp_resume(struct radeon_device *rdev);
  1145. void radeon_agp_suspend(struct radeon_device *rdev);
  1146. void radeon_agp_fini(struct radeon_device *rdev);
  1147.  
  1148.  
  1149. /*
  1150.  * Writeback
  1151.  */
  1152. struct radeon_wb {
  1153.         struct radeon_bo        *wb_obj;
  1154.         volatile uint32_t       *wb;
  1155.         uint64_t                gpu_addr;
  1156.         bool                    enabled;
  1157.         bool                    use_event;
  1158. };
  1159.  
  1160. #define RADEON_WB_SCRATCH_OFFSET 0
  1161. #define RADEON_WB_RING0_NEXT_RPTR 256
  1162. #define RADEON_WB_CP_RPTR_OFFSET 1024
  1163. #define RADEON_WB_CP1_RPTR_OFFSET 1280
  1164. #define RADEON_WB_CP2_RPTR_OFFSET 1536
  1165. #define R600_WB_DMA_RPTR_OFFSET   1792
  1166. #define R600_WB_IH_WPTR_OFFSET   2048
  1167. #define CAYMAN_WB_DMA1_RPTR_OFFSET   2304
  1168. #define R600_WB_EVENT_OFFSET     3072
  1169. #define CIK_WB_CP1_WPTR_OFFSET     3328
  1170. #define CIK_WB_CP2_WPTR_OFFSET     3584
  1171. #define R600_WB_DMA_RING_TEST_OFFSET 3588
  1172. #define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
  1173.  
  1174. /**
  1175.  * struct radeon_pm - power management datas
  1176.  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
  1177.  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  1178.  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
  1179.  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
  1180.  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
  1181.  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
  1182.  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  1183.  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
  1184.  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
  1185.  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
  1186.  * @needed_bandwidth:   current bandwidth needs
  1187.  *
  1188.  * It keeps track of various data needed to take powermanagement decision.
  1189.  * Bandwidth need is used to determine minimun clock of the GPU and memory.
  1190.  * Equation between gpu/memory clock and available bandwidth is hw dependent
  1191.  * (type of memory, bus size, efficiency, ...)
  1192.  */
  1193.  
  1194. enum radeon_pm_method {
  1195.         PM_METHOD_PROFILE,
  1196.         PM_METHOD_DYNPM,
  1197.         PM_METHOD_DPM,
  1198. };
  1199.  
  1200. enum radeon_dynpm_state {
  1201.         DYNPM_STATE_DISABLED,
  1202.         DYNPM_STATE_MINIMUM,
  1203.         DYNPM_STATE_PAUSED,
  1204.         DYNPM_STATE_ACTIVE,
  1205.         DYNPM_STATE_SUSPENDED,
  1206. };
  1207. enum radeon_dynpm_action {
  1208.         DYNPM_ACTION_NONE,
  1209.         DYNPM_ACTION_MINIMUM,
  1210.         DYNPM_ACTION_DOWNCLOCK,
  1211.         DYNPM_ACTION_UPCLOCK,
  1212.         DYNPM_ACTION_DEFAULT
  1213. };
  1214.  
  1215. enum radeon_voltage_type {
  1216.         VOLTAGE_NONE = 0,
  1217.         VOLTAGE_GPIO,
  1218.         VOLTAGE_VDDC,
  1219.         VOLTAGE_SW
  1220. };
  1221.  
  1222. enum radeon_pm_state_type {
  1223.         /* not used for dpm */
  1224.         POWER_STATE_TYPE_DEFAULT,
  1225.         POWER_STATE_TYPE_POWERSAVE,
  1226.         /* user selectable states */
  1227.         POWER_STATE_TYPE_BATTERY,
  1228.         POWER_STATE_TYPE_BALANCED,
  1229.         POWER_STATE_TYPE_PERFORMANCE,
  1230.         /* internal states */
  1231.         POWER_STATE_TYPE_INTERNAL_UVD,
  1232.         POWER_STATE_TYPE_INTERNAL_UVD_SD,
  1233.         POWER_STATE_TYPE_INTERNAL_UVD_HD,
  1234.         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
  1235.         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
  1236.         POWER_STATE_TYPE_INTERNAL_BOOT,
  1237.         POWER_STATE_TYPE_INTERNAL_THERMAL,
  1238.         POWER_STATE_TYPE_INTERNAL_ACPI,
  1239.         POWER_STATE_TYPE_INTERNAL_ULV,
  1240.         POWER_STATE_TYPE_INTERNAL_3DPERF,
  1241. };
  1242.  
  1243. enum radeon_pm_profile_type {
  1244.         PM_PROFILE_DEFAULT,
  1245.         PM_PROFILE_AUTO,
  1246.         PM_PROFILE_LOW,
  1247.         PM_PROFILE_MID,
  1248.         PM_PROFILE_HIGH,
  1249. };
  1250.  
  1251. #define PM_PROFILE_DEFAULT_IDX 0
  1252. #define PM_PROFILE_LOW_SH_IDX  1
  1253. #define PM_PROFILE_MID_SH_IDX  2
  1254. #define PM_PROFILE_HIGH_SH_IDX 3
  1255. #define PM_PROFILE_LOW_MH_IDX  4
  1256. #define PM_PROFILE_MID_MH_IDX  5
  1257. #define PM_PROFILE_HIGH_MH_IDX 6
  1258. #define PM_PROFILE_MAX         7
  1259.  
  1260. struct radeon_pm_profile {
  1261.         int dpms_off_ps_idx;
  1262.         int dpms_on_ps_idx;
  1263.         int dpms_off_cm_idx;
  1264.         int dpms_on_cm_idx;
  1265. };
  1266.  
  1267. enum radeon_int_thermal_type {
  1268.         THERMAL_TYPE_NONE,
  1269.         THERMAL_TYPE_EXTERNAL,
  1270.         THERMAL_TYPE_EXTERNAL_GPIO,
  1271.         THERMAL_TYPE_RV6XX,
  1272.         THERMAL_TYPE_RV770,
  1273.         THERMAL_TYPE_ADT7473_WITH_INTERNAL,
  1274.         THERMAL_TYPE_EVERGREEN,
  1275.         THERMAL_TYPE_SUMO,
  1276.         THERMAL_TYPE_NI,
  1277.         THERMAL_TYPE_SI,
  1278.         THERMAL_TYPE_EMC2103_WITH_INTERNAL,
  1279.         THERMAL_TYPE_CI,
  1280.         THERMAL_TYPE_KV,
  1281. };
  1282.  
  1283. struct radeon_voltage {
  1284.         enum radeon_voltage_type type;
  1285.         /* gpio voltage */
  1286.         struct radeon_gpio_rec gpio;
  1287.         u32 delay; /* delay in usec from voltage drop to sclk change */
  1288.         bool active_high; /* voltage drop is active when bit is high */
  1289.         /* VDDC voltage */
  1290.         u8 vddc_id; /* index into vddc voltage table */
  1291.         u8 vddci_id; /* index into vddci voltage table */
  1292.         bool vddci_enabled;
  1293.         /* r6xx+ sw */
  1294.         u16 voltage;
  1295.         /* evergreen+ vddci */
  1296.         u16 vddci;
  1297. };
  1298.  
  1299. /* clock mode flags */
  1300. #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
  1301.  
  1302. struct radeon_pm_clock_info {
  1303.         /* memory clock */
  1304.         u32 mclk;
  1305.         /* engine clock */
  1306.         u32 sclk;
  1307.         /* voltage info */
  1308.         struct radeon_voltage voltage;
  1309.         /* standardized clock flags */
  1310.         u32 flags;
  1311. };
  1312.  
  1313. /* state flags */
  1314. #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
  1315.  
  1316. struct radeon_power_state {
  1317.         enum radeon_pm_state_type type;
  1318.         struct radeon_pm_clock_info *clock_info;
  1319.         /* number of valid clock modes in this power state */
  1320.         int num_clock_modes;
  1321.         struct radeon_pm_clock_info *default_clock_mode;
  1322.         /* standardized state flags */
  1323.         u32 flags;
  1324.         u32 misc; /* vbios specific flags */
  1325.         u32 misc2; /* vbios specific flags */
  1326.         int pcie_lanes; /* pcie lanes */
  1327. };
  1328.  
  1329. /*
  1330.  * Some modes are overclocked by very low value, accept them
  1331.  */
  1332. #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
  1333.  
  1334. enum radeon_dpm_auto_throttle_src {
  1335.         RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
  1336.         RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
  1337. };
  1338.  
  1339. enum radeon_dpm_event_src {
  1340.         RADEON_DPM_EVENT_SRC_ANALOG = 0,
  1341.         RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
  1342.         RADEON_DPM_EVENT_SRC_DIGITAL = 2,
  1343.         RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
  1344.         RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
  1345. };
  1346.  
  1347. #define RADEON_MAX_VCE_LEVELS 6
  1348.  
  1349. enum radeon_vce_level {
  1350.         RADEON_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
  1351.         RADEON_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
  1352.         RADEON_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
  1353.         RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
  1354.         RADEON_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
  1355.         RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
  1356. };
  1357.  
  1358. struct radeon_ps {
  1359.         u32 caps; /* vbios flags */
  1360.         u32 class; /* vbios flags */
  1361.         u32 class2; /* vbios flags */
  1362.         /* UVD clocks */
  1363.         u32 vclk;
  1364.         u32 dclk;
  1365.         /* VCE clocks */
  1366.         u32 evclk;
  1367.         u32 ecclk;
  1368.         bool vce_active;
  1369.         enum radeon_vce_level vce_level;
  1370.         /* asic priv */
  1371.         void *ps_priv;
  1372. };
  1373.  
  1374. struct radeon_dpm_thermal {
  1375.         /* thermal interrupt work */
  1376.         struct work_struct work;
  1377.         /* low temperature threshold */
  1378.         int                min_temp;
  1379.         /* high temperature threshold */
  1380.         int                max_temp;
  1381.         /* was interrupt low to high or high to low */
  1382.         bool               high_to_low;
  1383. };
  1384.  
  1385. enum radeon_clk_action
  1386. {
  1387.         RADEON_SCLK_UP = 1,
  1388.         RADEON_SCLK_DOWN
  1389. };
  1390.  
  1391. struct radeon_blacklist_clocks
  1392. {
  1393.         u32 sclk;
  1394.         u32 mclk;
  1395.         enum radeon_clk_action action;
  1396. };
  1397.  
  1398. struct radeon_clock_and_voltage_limits {
  1399.         u32 sclk;
  1400.         u32 mclk;
  1401.         u16 vddc;
  1402.         u16 vddci;
  1403. };
  1404.  
  1405. struct radeon_clock_array {
  1406.         u32 count;
  1407.         u32 *values;
  1408. };
  1409.  
  1410. struct radeon_clock_voltage_dependency_entry {
  1411.         u32 clk;
  1412.         u16 v;
  1413. };
  1414.  
  1415. struct radeon_clock_voltage_dependency_table {
  1416.         u32 count;
  1417.         struct radeon_clock_voltage_dependency_entry *entries;
  1418. };
  1419.  
  1420. union radeon_cac_leakage_entry {
  1421.         struct {
  1422.                 u16 vddc;
  1423.                 u32 leakage;
  1424.         };
  1425.         struct {
  1426.                 u16 vddc1;
  1427.                 u16 vddc2;
  1428.                 u16 vddc3;
  1429.         };
  1430. };
  1431.  
  1432. struct radeon_cac_leakage_table {
  1433.         u32 count;
  1434.         union radeon_cac_leakage_entry *entries;
  1435. };
  1436.  
  1437. struct radeon_phase_shedding_limits_entry {
  1438.         u16 voltage;
  1439.         u32 sclk;
  1440.         u32 mclk;
  1441. };
  1442.  
  1443. struct radeon_phase_shedding_limits_table {
  1444.         u32 count;
  1445.         struct radeon_phase_shedding_limits_entry *entries;
  1446. };
  1447.  
  1448. struct radeon_uvd_clock_voltage_dependency_entry {
  1449.         u32 vclk;
  1450.         u32 dclk;
  1451.         u16 v;
  1452. };
  1453.  
  1454. struct radeon_uvd_clock_voltage_dependency_table {
  1455.         u8 count;
  1456.         struct radeon_uvd_clock_voltage_dependency_entry *entries;
  1457. };
  1458.  
  1459. struct radeon_vce_clock_voltage_dependency_entry {
  1460.         u32 ecclk;
  1461.         u32 evclk;
  1462.         u16 v;
  1463. };
  1464.  
  1465. struct radeon_vce_clock_voltage_dependency_table {
  1466.         u8 count;
  1467.         struct radeon_vce_clock_voltage_dependency_entry *entries;
  1468. };
  1469.  
  1470. struct radeon_ppm_table {
  1471.         u8 ppm_design;
  1472.         u16 cpu_core_number;
  1473.         u32 platform_tdp;
  1474.         u32 small_ac_platform_tdp;
  1475.         u32 platform_tdc;
  1476.         u32 small_ac_platform_tdc;
  1477.         u32 apu_tdp;
  1478.         u32 dgpu_tdp;
  1479.         u32 dgpu_ulv_power;
  1480.         u32 tj_max;
  1481. };
  1482.  
  1483. struct radeon_cac_tdp_table {
  1484.         u16 tdp;
  1485.         u16 configurable_tdp;
  1486.         u16 tdc;
  1487.         u16 battery_power_limit;
  1488.         u16 small_power_limit;
  1489.         u16 low_cac_leakage;
  1490.         u16 high_cac_leakage;
  1491.         u16 maximum_power_delivery_limit;
  1492. };
  1493.  
  1494. struct radeon_dpm_dynamic_state {
  1495.         struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
  1496.         struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
  1497.         struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
  1498.         struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
  1499.         struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
  1500.         struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
  1501.         struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
  1502.         struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
  1503.         struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
  1504.         struct radeon_clock_array valid_sclk_values;
  1505.         struct radeon_clock_array valid_mclk_values;
  1506.         struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
  1507.         struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
  1508.         u32 mclk_sclk_ratio;
  1509.         u32 sclk_mclk_delta;
  1510.         u16 vddc_vddci_delta;
  1511.         u16 min_vddc_for_pcie_gen2;
  1512.         struct radeon_cac_leakage_table cac_leakage_table;
  1513.         struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
  1514.         struct radeon_ppm_table *ppm_table;
  1515.         struct radeon_cac_tdp_table *cac_tdp_table;
  1516. };
  1517.  
  1518. struct radeon_dpm_fan {
  1519.         u16 t_min;
  1520.         u16 t_med;
  1521.         u16 t_high;
  1522.         u16 pwm_min;
  1523.         u16 pwm_med;
  1524.         u16 pwm_high;
  1525.         u8 t_hyst;
  1526.         u32 cycle_delay;
  1527.         u16 t_max;
  1528.         u8 control_mode;
  1529.         u16 default_max_fan_pwm;
  1530.         u16 default_fan_output_sensitivity;
  1531.         u16 fan_output_sensitivity;
  1532.         bool ucode_fan_control;
  1533. };
  1534.  
  1535. enum radeon_pcie_gen {
  1536.         RADEON_PCIE_GEN1 = 0,
  1537.         RADEON_PCIE_GEN2 = 1,
  1538.         RADEON_PCIE_GEN3 = 2,
  1539.         RADEON_PCIE_GEN_INVALID = 0xffff
  1540. };
  1541.  
  1542. enum radeon_dpm_forced_level {
  1543.         RADEON_DPM_FORCED_LEVEL_AUTO = 0,
  1544.         RADEON_DPM_FORCED_LEVEL_LOW = 1,
  1545.         RADEON_DPM_FORCED_LEVEL_HIGH = 2,
  1546. };
  1547.  
  1548. struct radeon_vce_state {
  1549.         /* vce clocks */
  1550.         u32 evclk;
  1551.         u32 ecclk;
  1552.         /* gpu clocks */
  1553.         u32 sclk;
  1554.         u32 mclk;
  1555.         u8 clk_idx;
  1556.         u8 pstate;
  1557. };
  1558.  
  1559. struct radeon_dpm {
  1560.         struct radeon_ps        *ps;
  1561.         /* number of valid power states */
  1562.         int                     num_ps;
  1563.         /* current power state that is active */
  1564.         struct radeon_ps        *current_ps;
  1565.         /* requested power state */
  1566.         struct radeon_ps        *requested_ps;
  1567.         /* boot up power state */
  1568.         struct radeon_ps        *boot_ps;
  1569.         /* default uvd power state */
  1570.         struct radeon_ps        *uvd_ps;
  1571.         /* vce requirements */
  1572.         struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
  1573.         enum radeon_vce_level vce_level;
  1574.         enum radeon_pm_state_type state;
  1575.         enum radeon_pm_state_type user_state;
  1576.         u32                     platform_caps;
  1577.         u32                     voltage_response_time;
  1578.         u32                     backbias_response_time;
  1579.         void                    *priv;
  1580.         u32                     new_active_crtcs;
  1581.         int                     new_active_crtc_count;
  1582.         u32                     current_active_crtcs;
  1583.         int                     current_active_crtc_count;
  1584.         struct radeon_dpm_dynamic_state dyn_state;
  1585.         struct radeon_dpm_fan fan;
  1586.         u32 tdp_limit;
  1587.         u32 near_tdp_limit;
  1588.         u32 near_tdp_limit_adjusted;
  1589.         u32 sq_ramping_threshold;
  1590.         u32 cac_leakage;
  1591.         u16 tdp_od_limit;
  1592.         u32 tdp_adjustment;
  1593.         u16 load_line_slope;
  1594.         bool power_control;
  1595.         bool ac_power;
  1596.         /* special states active */
  1597.         bool                    thermal_active;
  1598.         bool                    uvd_active;
  1599.         bool                    vce_active;
  1600.         /* thermal handling */
  1601.         struct radeon_dpm_thermal thermal;
  1602.         /* forced levels */
  1603.         enum radeon_dpm_forced_level forced_level;
  1604.         /* track UVD streams */
  1605.         unsigned sd;
  1606.         unsigned hd;
  1607. };
  1608.  
  1609. void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
  1610. void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
  1611.  
  1612. struct radeon_pm {
  1613.         struct mutex            mutex;
  1614.         /* write locked while reprogramming mclk */
  1615.         struct rw_semaphore     mclk_lock;
  1616.         u32                     active_crtcs;
  1617.         int                     active_crtc_count;
  1618.         int                     req_vblank;
  1619.         bool                    vblank_sync;
  1620.         fixed20_12              max_bandwidth;
  1621.         fixed20_12              igp_sideport_mclk;
  1622.         fixed20_12              igp_system_mclk;
  1623.         fixed20_12              igp_ht_link_clk;
  1624.         fixed20_12              igp_ht_link_width;
  1625.         fixed20_12              k8_bandwidth;
  1626.         fixed20_12              sideport_bandwidth;
  1627.         fixed20_12              ht_bandwidth;
  1628.         fixed20_12              core_bandwidth;
  1629.         fixed20_12              sclk;
  1630.         fixed20_12              mclk;
  1631.         fixed20_12              needed_bandwidth;
  1632.         struct radeon_power_state *power_state;
  1633.         /* number of valid power states */
  1634.         int                     num_power_states;
  1635.         int                     current_power_state_index;
  1636.         int                     current_clock_mode_index;
  1637.         int                     requested_power_state_index;
  1638.         int                     requested_clock_mode_index;
  1639.         int                     default_power_state_index;
  1640.         u32                     current_sclk;
  1641.         u32                     current_mclk;
  1642.         u16                     current_vddc;
  1643.         u16                     current_vddci;
  1644.         u32                     default_sclk;
  1645.         u32                     default_mclk;
  1646.         u16                     default_vddc;
  1647.         u16                     default_vddci;
  1648.         struct radeon_i2c_chan *i2c_bus;
  1649.         /* selected pm method */
  1650.         enum radeon_pm_method     pm_method;
  1651.         /* dynpm power management */
  1652.         struct delayed_work     dynpm_idle_work;
  1653.         enum radeon_dynpm_state dynpm_state;
  1654.         enum radeon_dynpm_action        dynpm_planned_action;
  1655.         unsigned long           dynpm_action_timeout;
  1656.         bool                    dynpm_can_upclock;
  1657.         bool                    dynpm_can_downclock;
  1658.         /* profile-based power management */
  1659.         enum radeon_pm_profile_type profile;
  1660.         int                     profile_index;
  1661.         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
  1662.         /* internal thermal controller on rv6xx+ */
  1663.         enum radeon_int_thermal_type int_thermal_type;
  1664.         struct device           *int_hwmon_dev;
  1665.         /* fan control parameters */
  1666.         bool                    no_fan;
  1667.         u8                      fan_pulses_per_revolution;
  1668.         u8                      fan_min_rpm;
  1669.         u8                      fan_max_rpm;
  1670.         /* dpm */
  1671.         bool                    dpm_enabled;
  1672.         struct radeon_dpm       dpm;
  1673. };
  1674.  
  1675. int radeon_pm_get_type_index(struct radeon_device *rdev,
  1676.                              enum radeon_pm_state_type ps_type,
  1677.                              int instance);
  1678. /*
  1679.  * UVD
  1680.  */
  1681. #define RADEON_MAX_UVD_HANDLES  10
  1682. #define RADEON_UVD_STACK_SIZE   (1024*1024)
  1683. #define RADEON_UVD_HEAP_SIZE    (1024*1024)
  1684.  
  1685. struct radeon_uvd {
  1686.         struct radeon_bo        *vcpu_bo;
  1687.         void                    *cpu_addr;
  1688.         uint64_t                gpu_addr;
  1689.         void                    *saved_bo;
  1690.         atomic_t                handles[RADEON_MAX_UVD_HANDLES];
  1691.         struct drm_file         *filp[RADEON_MAX_UVD_HANDLES];
  1692.         unsigned                img_size[RADEON_MAX_UVD_HANDLES];
  1693.         struct delayed_work     idle_work;
  1694. };
  1695.  
  1696. int radeon_uvd_init(struct radeon_device *rdev);
  1697. void radeon_uvd_fini(struct radeon_device *rdev);
  1698. int radeon_uvd_suspend(struct radeon_device *rdev);
  1699. int radeon_uvd_resume(struct radeon_device *rdev);
  1700. int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
  1701.                               uint32_t handle, struct radeon_fence **fence);
  1702. int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
  1703.                                uint32_t handle, struct radeon_fence **fence);
  1704. void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
  1705.                                        uint32_t allowed_domains);
  1706. void radeon_uvd_free_handles(struct radeon_device *rdev,
  1707.                              struct drm_file *filp);
  1708. int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
  1709. void radeon_uvd_note_usage(struct radeon_device *rdev);
  1710. int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
  1711.                                   unsigned vclk, unsigned dclk,
  1712.                                   unsigned vco_min, unsigned vco_max,
  1713.                                   unsigned fb_factor, unsigned fb_mask,
  1714.                                   unsigned pd_min, unsigned pd_max,
  1715.                                   unsigned pd_even,
  1716.                                   unsigned *optimal_fb_div,
  1717.                                   unsigned *optimal_vclk_div,
  1718.                                   unsigned *optimal_dclk_div);
  1719. int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
  1720.                                 unsigned cg_upll_func_cntl);
  1721.  
  1722. /*
  1723.  * VCE
  1724.  */
  1725. #define RADEON_MAX_VCE_HANDLES  16
  1726. #define RADEON_VCE_STACK_SIZE   (1024*1024)
  1727. #define RADEON_VCE_HEAP_SIZE    (4*1024*1024)
  1728.  
  1729. struct radeon_vce {
  1730.         struct radeon_bo        *vcpu_bo;
  1731.         uint64_t                gpu_addr;
  1732.         unsigned                fw_version;
  1733.         unsigned                fb_version;
  1734.         atomic_t                handles[RADEON_MAX_VCE_HANDLES];
  1735.         struct drm_file         *filp[RADEON_MAX_VCE_HANDLES];
  1736.         unsigned                img_size[RADEON_MAX_VCE_HANDLES];
  1737.         struct delayed_work     idle_work;
  1738. };
  1739.  
  1740. int radeon_vce_init(struct radeon_device *rdev);
  1741. void radeon_vce_fini(struct radeon_device *rdev);
  1742. int radeon_vce_suspend(struct radeon_device *rdev);
  1743. int radeon_vce_resume(struct radeon_device *rdev);
  1744. int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
  1745.                               uint32_t handle, struct radeon_fence **fence);
  1746. int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
  1747.                                uint32_t handle, struct radeon_fence **fence);
  1748. void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
  1749. void radeon_vce_note_usage(struct radeon_device *rdev);
  1750. int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
  1751. int radeon_vce_cs_parse(struct radeon_cs_parser *p);
  1752. bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
  1753.                                struct radeon_ring *ring,
  1754.                                struct radeon_semaphore *semaphore,
  1755.                                bool emit_wait);
  1756. void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  1757. void radeon_vce_fence_emit(struct radeon_device *rdev,
  1758.                            struct radeon_fence *fence);
  1759. int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
  1760. int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
  1761.  
  1762. struct r600_audio_pin {
  1763.         int                     channels;
  1764.         int                     rate;
  1765.         int                     bits_per_sample;
  1766.         u8                      status_bits;
  1767.         u8                      category_code;
  1768.         u32                     offset;
  1769.         bool                    connected;
  1770.         u32                     id;
  1771. };
  1772.  
  1773. struct r600_audio {
  1774.         bool enabled;
  1775.         struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
  1776.         int num_pins;
  1777. };
  1778.  
  1779. /*
  1780.  * Benchmarking
  1781.  */
  1782. void radeon_benchmark(struct radeon_device *rdev, int test_number);
  1783.  
  1784.  
  1785. /*
  1786.  * Testing
  1787.  */
  1788. void radeon_test_moves(struct radeon_device *rdev);
  1789. void radeon_test_ring_sync(struct radeon_device *rdev,
  1790.                            struct radeon_ring *cpA,
  1791.                            struct radeon_ring *cpB);
  1792. void radeon_test_syncing(struct radeon_device *rdev);
  1793.  
  1794. /*
  1795.  * MMU Notifier
  1796.  */
  1797. int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
  1798. void radeon_mn_unregister(struct radeon_bo *bo);
  1799.  
  1800. /*
  1801.  * Debugfs
  1802.  */
  1803. struct radeon_debugfs {
  1804.         struct drm_info_list    *files;
  1805.         unsigned                num_files;
  1806. };
  1807.  
  1808. int radeon_debugfs_add_files(struct radeon_device *rdev,
  1809.                              struct drm_info_list *files,
  1810.                              unsigned nfiles);
  1811. int radeon_debugfs_fence_init(struct radeon_device *rdev);
  1812.  
  1813. /*
  1814.  * ASIC ring specific functions.
  1815.  */
  1816. struct radeon_asic_ring {
  1817.         /* ring read/write ptr handling */
  1818.         u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
  1819.         u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
  1820.         void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
  1821.  
  1822.         /* validating and patching of IBs */
  1823.         int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
  1824.         int (*cs_parse)(struct radeon_cs_parser *p);
  1825.  
  1826.         /* command emmit functions */
  1827.         void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  1828.         void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
  1829.         void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
  1830.         bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
  1831.                                struct radeon_semaphore *semaphore, bool emit_wait);
  1832.         void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
  1833.                          unsigned vm_id, uint64_t pd_addr);
  1834.  
  1835.         /* testing functions */
  1836.         int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
  1837.         int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
  1838.         bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
  1839.  
  1840.         /* deprecated */
  1841.         void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
  1842. };
  1843.  
  1844. /*
  1845.  * ASIC specific functions.
  1846.  */
  1847. struct radeon_asic {
  1848.         int (*init)(struct radeon_device *rdev);
  1849.         void (*fini)(struct radeon_device *rdev);
  1850.         int (*resume)(struct radeon_device *rdev);
  1851.         int (*suspend)(struct radeon_device *rdev);
  1852.         void (*vga_set_state)(struct radeon_device *rdev, bool state);
  1853.         int (*asic_reset)(struct radeon_device *rdev);
  1854.         /* Flush the HDP cache via MMIO */
  1855.         void (*mmio_hdp_flush)(struct radeon_device *rdev);
  1856.         /* check if 3D engine is idle */
  1857.         bool (*gui_idle)(struct radeon_device *rdev);
  1858.         /* wait for mc_idle */
  1859.         int (*mc_wait_for_idle)(struct radeon_device *rdev);
  1860.         /* get the reference clock */
  1861.         u32 (*get_xclk)(struct radeon_device *rdev);
  1862.         /* get the gpu clock counter */
  1863.         uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
  1864.         /* gart */
  1865.         struct {
  1866.                 void (*tlb_flush)(struct radeon_device *rdev);
  1867.                 void (*set_page)(struct radeon_device *rdev, unsigned i,
  1868.                                  uint64_t addr, uint32_t flags);
  1869.         } gart;
  1870.         struct {
  1871.                 int (*init)(struct radeon_device *rdev);
  1872.                 void (*fini)(struct radeon_device *rdev);
  1873.                 void (*copy_pages)(struct radeon_device *rdev,
  1874.                                    struct radeon_ib *ib,
  1875.                                    uint64_t pe, uint64_t src,
  1876.                                    unsigned count);
  1877.                 void (*write_pages)(struct radeon_device *rdev,
  1878.                                     struct radeon_ib *ib,
  1879.                                     uint64_t pe,
  1880.                                     uint64_t addr, unsigned count,
  1881.                                     uint32_t incr, uint32_t flags);
  1882.                 void (*set_pages)(struct radeon_device *rdev,
  1883.                                  struct radeon_ib *ib,
  1884.                                  uint64_t pe,
  1885.                                  uint64_t addr, unsigned count,
  1886.                                  uint32_t incr, uint32_t flags);
  1887.                 void (*pad_ib)(struct radeon_ib *ib);
  1888.         } vm;
  1889.         /* ring specific callbacks */
  1890.         struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
  1891.         /* irqs */
  1892.         struct {
  1893.                 int (*set)(struct radeon_device *rdev);
  1894.                 int (*process)(struct radeon_device *rdev);
  1895.         } irq;
  1896.         /* displays */
  1897.         struct {
  1898.                 /* display watermarks */
  1899.                 void (*bandwidth_update)(struct radeon_device *rdev);
  1900.                 /* get frame count */
  1901.         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  1902.                 /* wait for vblank */
  1903.                 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
  1904.                 /* set backlight level */
  1905.                 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
  1906.                 /* get backlight level */
  1907.                 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
  1908.                 /* audio callbacks */
  1909.                 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
  1910.                 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
  1911.         } display;
  1912.         /* copy functions for bo handling */
  1913.         struct {
  1914.                 struct radeon_fence *(*blit)(struct radeon_device *rdev,
  1915.                          uint64_t src_offset,
  1916.                          uint64_t dst_offset,
  1917.                          unsigned num_gpu_pages,
  1918.                                              struct reservation_object *resv);
  1919.                 u32 blit_ring_index;
  1920.                 struct radeon_fence *(*dma)(struct radeon_device *rdev,
  1921.                         uint64_t src_offset,
  1922.                         uint64_t dst_offset,
  1923.                         unsigned num_gpu_pages,
  1924.                                             struct reservation_object *resv);
  1925.                 u32 dma_ring_index;
  1926.                 /* method used for bo copy */
  1927.                 struct radeon_fence *(*copy)(struct radeon_device *rdev,
  1928.                     uint64_t src_offset,
  1929.                     uint64_t dst_offset,
  1930.                     unsigned num_gpu_pages,
  1931.                                              struct reservation_object *resv);
  1932.                 /* ring used for bo copies */
  1933.                 u32 copy_ring_index;
  1934.         } copy;
  1935.         /* surfaces */
  1936.         struct {
  1937.                 int (*set_reg)(struct radeon_device *rdev, int reg,
  1938.                                        uint32_t tiling_flags, uint32_t pitch,
  1939.                                        uint32_t offset, uint32_t obj_size);
  1940.                 void (*clear_reg)(struct radeon_device *rdev, int reg);
  1941.         } surface;
  1942.         /* hotplug detect */
  1943.         struct {
  1944.                 void (*init)(struct radeon_device *rdev);
  1945.                 void (*fini)(struct radeon_device *rdev);
  1946.                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  1947.                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  1948.         } hpd;
  1949.         /* static power management */
  1950.         struct {
  1951.                 void (*misc)(struct radeon_device *rdev);
  1952.                 void (*prepare)(struct radeon_device *rdev);
  1953.                 void (*finish)(struct radeon_device *rdev);
  1954.                 void (*init_profile)(struct radeon_device *rdev);
  1955.                 void (*get_dynpm_state)(struct radeon_device *rdev);
  1956.         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
  1957.         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  1958.         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
  1959.         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  1960.         int (*get_pcie_lanes)(struct radeon_device *rdev);
  1961.         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  1962.         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  1963.                 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
  1964.                 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
  1965.                 int (*get_temperature)(struct radeon_device *rdev);
  1966.         } pm;
  1967.         /* dynamic power management */
  1968.         struct {
  1969.                 int (*init)(struct radeon_device *rdev);
  1970.                 void (*setup_asic)(struct radeon_device *rdev);
  1971.                 int (*enable)(struct radeon_device *rdev);
  1972.                 int (*late_enable)(struct radeon_device *rdev);
  1973.                 void (*disable)(struct radeon_device *rdev);
  1974.                 int (*pre_set_power_state)(struct radeon_device *rdev);
  1975.                 int (*set_power_state)(struct radeon_device *rdev);
  1976.                 void (*post_set_power_state)(struct radeon_device *rdev);
  1977.                 void (*display_configuration_changed)(struct radeon_device *rdev);
  1978.                 void (*fini)(struct radeon_device *rdev);
  1979.                 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
  1980.                 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
  1981.                 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
  1982.                 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
  1983.                 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
  1984.                 bool (*vblank_too_short)(struct radeon_device *rdev);
  1985.                 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
  1986.                 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
  1987.         } dpm;
  1988.         /* pageflipping */
  1989.         struct {
  1990.                 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
  1991.                 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
  1992.         } pflip;
  1993. };
  1994.  
  1995. /*
  1996.  * Asic structures
  1997.  */
  1998. struct r100_asic {
  1999.         const unsigned  *reg_safe_bm;
  2000.         unsigned        reg_safe_bm_size;
  2001.         u32             hdp_cntl;
  2002. };
  2003.  
  2004. struct r300_asic {
  2005.         const unsigned  *reg_safe_bm;
  2006.         unsigned        reg_safe_bm_size;
  2007.         u32             resync_scratch;
  2008.         u32             hdp_cntl;
  2009. };
  2010.  
  2011. struct r600_asic {
  2012.         unsigned max_pipes;
  2013.         unsigned max_tile_pipes;
  2014.         unsigned max_simds;
  2015.         unsigned max_backends;
  2016.         unsigned max_gprs;
  2017.         unsigned max_threads;
  2018.         unsigned max_stack_entries;
  2019.         unsigned max_hw_contexts;
  2020.         unsigned max_gs_threads;
  2021.         unsigned sx_max_export_size;
  2022.         unsigned sx_max_export_pos_size;
  2023.         unsigned sx_max_export_smx_size;
  2024.         unsigned sq_num_cf_insts;
  2025.         unsigned tiling_nbanks;
  2026.         unsigned tiling_npipes;
  2027.         unsigned tiling_group_size;
  2028.         unsigned                tile_config;
  2029.         unsigned                backend_map;
  2030.         unsigned                active_simds;
  2031. };
  2032.  
  2033. struct rv770_asic {
  2034.         unsigned max_pipes;
  2035.         unsigned max_tile_pipes;
  2036.         unsigned max_simds;
  2037.         unsigned max_backends;
  2038.         unsigned max_gprs;
  2039.         unsigned max_threads;
  2040.         unsigned max_stack_entries;
  2041.         unsigned max_hw_contexts;
  2042.         unsigned max_gs_threads;
  2043.         unsigned sx_max_export_size;
  2044.         unsigned sx_max_export_pos_size;
  2045.         unsigned sx_max_export_smx_size;
  2046.         unsigned sq_num_cf_insts;
  2047.         unsigned sx_num_of_sets;
  2048.         unsigned sc_prim_fifo_size;
  2049.         unsigned sc_hiz_tile_fifo_size;
  2050.         unsigned sc_earlyz_tile_fifo_fize;
  2051.         unsigned tiling_nbanks;
  2052.         unsigned tiling_npipes;
  2053.         unsigned tiling_group_size;
  2054.         unsigned                tile_config;
  2055.         unsigned                backend_map;
  2056.         unsigned                active_simds;
  2057. };
  2058.  
  2059. struct evergreen_asic {
  2060.         unsigned num_ses;
  2061.         unsigned max_pipes;
  2062.         unsigned max_tile_pipes;
  2063.         unsigned max_simds;
  2064.         unsigned max_backends;
  2065.         unsigned max_gprs;
  2066.         unsigned max_threads;
  2067.         unsigned max_stack_entries;
  2068.         unsigned max_hw_contexts;
  2069.         unsigned max_gs_threads;
  2070.         unsigned sx_max_export_size;
  2071.         unsigned sx_max_export_pos_size;
  2072.         unsigned sx_max_export_smx_size;
  2073.         unsigned sq_num_cf_insts;
  2074.         unsigned sx_num_of_sets;
  2075.         unsigned sc_prim_fifo_size;
  2076.         unsigned sc_hiz_tile_fifo_size;
  2077.         unsigned sc_earlyz_tile_fifo_size;
  2078.         unsigned tiling_nbanks;
  2079.         unsigned tiling_npipes;
  2080.         unsigned tiling_group_size;
  2081.         unsigned tile_config;
  2082.         unsigned backend_map;
  2083.         unsigned active_simds;
  2084. };
  2085.  
  2086. struct cayman_asic {
  2087.         unsigned max_shader_engines;
  2088.         unsigned max_pipes_per_simd;
  2089.         unsigned max_tile_pipes;
  2090.         unsigned max_simds_per_se;
  2091.         unsigned max_backends_per_se;
  2092.         unsigned max_texture_channel_caches;
  2093.         unsigned max_gprs;
  2094.         unsigned max_threads;
  2095.         unsigned max_gs_threads;
  2096.         unsigned max_stack_entries;
  2097.         unsigned sx_num_of_sets;
  2098.         unsigned sx_max_export_size;
  2099.         unsigned sx_max_export_pos_size;
  2100.         unsigned sx_max_export_smx_size;
  2101.         unsigned max_hw_contexts;
  2102.         unsigned sq_num_cf_insts;
  2103.         unsigned sc_prim_fifo_size;
  2104.         unsigned sc_hiz_tile_fifo_size;
  2105.         unsigned sc_earlyz_tile_fifo_size;
  2106.  
  2107.         unsigned num_shader_engines;
  2108.         unsigned num_shader_pipes_per_simd;
  2109.         unsigned num_tile_pipes;
  2110.         unsigned num_simds_per_se;
  2111.         unsigned num_backends_per_se;
  2112.         unsigned backend_disable_mask_per_asic;
  2113.         unsigned backend_map;
  2114.         unsigned num_texture_channel_caches;
  2115.         unsigned mem_max_burst_length_bytes;
  2116.         unsigned mem_row_size_in_kb;
  2117.         unsigned shader_engine_tile_size;
  2118.         unsigned num_gpus;
  2119.         unsigned multi_gpu_tile_size;
  2120.  
  2121.         unsigned tile_config;
  2122.         unsigned active_simds;
  2123. };
  2124.  
  2125. struct si_asic {
  2126.         unsigned max_shader_engines;
  2127.         unsigned max_tile_pipes;
  2128.         unsigned max_cu_per_sh;
  2129.         unsigned max_sh_per_se;
  2130.         unsigned max_backends_per_se;
  2131.         unsigned max_texture_channel_caches;
  2132.         unsigned max_gprs;
  2133.         unsigned max_gs_threads;
  2134.         unsigned max_hw_contexts;
  2135.         unsigned sc_prim_fifo_size_frontend;
  2136.         unsigned sc_prim_fifo_size_backend;
  2137.         unsigned sc_hiz_tile_fifo_size;
  2138.         unsigned sc_earlyz_tile_fifo_size;
  2139.  
  2140.         unsigned num_tile_pipes;
  2141.         unsigned backend_enable_mask;
  2142.         unsigned backend_disable_mask_per_asic;
  2143.         unsigned backend_map;
  2144.         unsigned num_texture_channel_caches;
  2145.         unsigned mem_max_burst_length_bytes;
  2146.         unsigned mem_row_size_in_kb;
  2147.         unsigned shader_engine_tile_size;
  2148.         unsigned num_gpus;
  2149.         unsigned multi_gpu_tile_size;
  2150.  
  2151.         unsigned tile_config;
  2152.         uint32_t tile_mode_array[32];
  2153.         uint32_t active_cus;
  2154. };
  2155.  
  2156. struct cik_asic {
  2157.         unsigned max_shader_engines;
  2158.         unsigned max_tile_pipes;
  2159.         unsigned max_cu_per_sh;
  2160.         unsigned max_sh_per_se;
  2161.         unsigned max_backends_per_se;
  2162.         unsigned max_texture_channel_caches;
  2163.         unsigned max_gprs;
  2164.         unsigned max_gs_threads;
  2165.         unsigned max_hw_contexts;
  2166.         unsigned sc_prim_fifo_size_frontend;
  2167.         unsigned sc_prim_fifo_size_backend;
  2168.         unsigned sc_hiz_tile_fifo_size;
  2169.         unsigned sc_earlyz_tile_fifo_size;
  2170.  
  2171.         unsigned num_tile_pipes;
  2172.         unsigned backend_enable_mask;
  2173.         unsigned backend_disable_mask_per_asic;
  2174.         unsigned backend_map;
  2175.         unsigned num_texture_channel_caches;
  2176.         unsigned mem_max_burst_length_bytes;
  2177.         unsigned mem_row_size_in_kb;
  2178.         unsigned shader_engine_tile_size;
  2179.         unsigned num_gpus;
  2180.         unsigned multi_gpu_tile_size;
  2181.  
  2182.         unsigned tile_config;
  2183.         uint32_t tile_mode_array[32];
  2184.         uint32_t macrotile_mode_array[16];
  2185.         uint32_t active_cus;
  2186. };
  2187.  
  2188. union radeon_asic_config {
  2189.         struct r300_asic        r300;
  2190.         struct r100_asic        r100;
  2191.         struct r600_asic        r600;
  2192.         struct rv770_asic       rv770;
  2193.         struct evergreen_asic   evergreen;
  2194.         struct cayman_asic      cayman;
  2195.         struct si_asic          si;
  2196.         struct cik_asic         cik;
  2197. };
  2198.  
  2199. /*
  2200.  * asic initizalization from radeon_asic.c
  2201.  */
  2202. void radeon_agp_disable(struct radeon_device *rdev);
  2203. int radeon_asic_init(struct radeon_device *rdev);
  2204.  
  2205.  
  2206.  
  2207. /* VRAM scratch page for HDP bug, default vram page */
  2208. struct r600_vram_scratch {
  2209.         struct radeon_bo                *robj;
  2210.         volatile uint32_t               *ptr;
  2211.         u64                             gpu_addr;
  2212. };
  2213.  
  2214. /*
  2215.  * ACPI
  2216.  */
  2217. struct radeon_atif_notification_cfg {
  2218.         bool enabled;
  2219.         int command_code;
  2220. };
  2221.  
  2222. struct radeon_atif_notifications {
  2223.         bool display_switch;
  2224.         bool expansion_mode_change;
  2225.         bool thermal_state;
  2226.         bool forced_power_state;
  2227.         bool system_power_state;
  2228.         bool display_conf_change;
  2229.         bool px_gfx_switch;
  2230.         bool brightness_change;
  2231.         bool dgpu_display_event;
  2232. };
  2233.  
  2234. struct radeon_atif_functions {
  2235.         bool system_params;
  2236.         bool sbios_requests;
  2237.         bool select_active_disp;
  2238.         bool lid_state;
  2239.         bool get_tv_standard;
  2240.         bool set_tv_standard;
  2241.         bool get_panel_expansion_mode;
  2242.         bool set_panel_expansion_mode;
  2243.         bool temperature_change;
  2244.         bool graphics_device_types;
  2245. };
  2246.  
  2247. struct radeon_atif {
  2248.         struct radeon_atif_notifications notifications;
  2249.         struct radeon_atif_functions functions;
  2250.         struct radeon_atif_notification_cfg notification_cfg;
  2251.         struct radeon_encoder *encoder_for_bl;
  2252. };
  2253.  
  2254. struct radeon_atcs_functions {
  2255.         bool get_ext_state;
  2256.         bool pcie_perf_req;
  2257.         bool pcie_dev_rdy;
  2258.         bool pcie_bus_width;
  2259. };
  2260.  
  2261. struct radeon_atcs {
  2262.         struct radeon_atcs_functions functions;
  2263. };
  2264.  
  2265. /*
  2266.  * Core structure, functions and helpers.
  2267.  */
  2268. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  2269. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  2270.  
  2271. struct radeon_device {
  2272.     struct device              *dev;
  2273.     struct drm_device          *ddev;
  2274.     struct pci_dev             *pdev;
  2275.         struct rw_semaphore             exclusive_lock;
  2276.     /* ASIC */
  2277.     union radeon_asic_config    config;
  2278.     enum radeon_family          family;
  2279.     unsigned long               flags;
  2280.     int                         usec_timeout;
  2281.     enum radeon_pll_errata      pll_errata;
  2282.     int                         num_gb_pipes;
  2283.         int                                         num_z_pipes;
  2284.     int                         disp_priority;
  2285.     /* BIOS */
  2286.     uint8_t                     *bios;
  2287.     bool                        is_atom_bios;
  2288.     uint16_t                    bios_header_start;
  2289.         struct radeon_bo                    *stollen_vga_memory;
  2290.     /* Register mmio */
  2291.         resource_size_t                 rmmio_base;
  2292.         resource_size_t                 rmmio_size;
  2293.         /* protects concurrent MM_INDEX/DATA based register access */
  2294.         spinlock_t mmio_idx_lock;
  2295.         /* protects concurrent SMC based register access */
  2296.         spinlock_t smc_idx_lock;
  2297.         /* protects concurrent PLL register access */
  2298.         spinlock_t pll_idx_lock;
  2299.         /* protects concurrent MC register access */
  2300.         spinlock_t mc_idx_lock;
  2301.         /* protects concurrent PCIE register access */
  2302.         spinlock_t pcie_idx_lock;
  2303.         /* protects concurrent PCIE_PORT register access */
  2304.         spinlock_t pciep_idx_lock;
  2305.         /* protects concurrent PIF register access */
  2306.         spinlock_t pif_idx_lock;
  2307.         /* protects concurrent CG register access */
  2308.         spinlock_t cg_idx_lock;
  2309.         /* protects concurrent UVD register access */
  2310.         spinlock_t uvd_idx_lock;
  2311.         /* protects concurrent RCU register access */
  2312.         spinlock_t rcu_idx_lock;
  2313.         /* protects concurrent DIDT register access */
  2314.         spinlock_t didt_idx_lock;
  2315.         /* protects concurrent ENDPOINT (audio) register access */
  2316.         spinlock_t end_idx_lock;
  2317.         void __iomem                    *rmmio;
  2318.     radeon_rreg_t               mc_rreg;
  2319.     radeon_wreg_t               mc_wreg;
  2320.     radeon_rreg_t               pll_rreg;
  2321.     radeon_wreg_t               pll_wreg;
  2322.         uint32_t                        pcie_reg_mask;
  2323.     radeon_rreg_t               pciep_rreg;
  2324.     radeon_wreg_t               pciep_wreg;
  2325.         /* io port */
  2326.         void __iomem                    *rio_mem;
  2327.         resource_size_t                 rio_mem_size;
  2328.     struct radeon_clock         clock;
  2329.     struct radeon_mc            mc;
  2330.     struct radeon_gart          gart;
  2331.         struct radeon_mode_info         mode_info;
  2332.     struct radeon_scratch       scratch;
  2333.         struct radeon_doorbell          doorbell;
  2334.     struct radeon_mman          mman;
  2335.         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
  2336.         wait_queue_head_t               fence_queue;
  2337.         unsigned                        fence_context;
  2338.         struct mutex                    ring_lock;
  2339.         struct radeon_ring              ring[RADEON_NUM_RINGS];
  2340.         bool                            ib_pool_ready;
  2341.         struct radeon_sa_manager        ring_tmp_bo;
  2342.     struct radeon_irq       irq;
  2343.     struct radeon_asic         *asic;
  2344.     struct radeon_gem       gem;
  2345.         struct radeon_pm                pm;
  2346.         struct radeon_uvd               uvd;
  2347.         struct radeon_vce               vce;
  2348.         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  2349.     struct radeon_wb        wb;
  2350.         struct radeon_dummy_page        dummy_page;
  2351.     bool                shutdown;
  2352.     bool                suspend;
  2353.         bool                            need_dma32;
  2354.         bool                            accel_working;
  2355.         bool                            fastfb_working; /* IGP feature*/
  2356.         bool                            needs_reset, in_reset;
  2357.         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  2358.         const struct firmware *me_fw;   /* all family ME firmware */
  2359.         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
  2360.         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
  2361.         const struct firmware *mc_fw;   /* NI MC firmware */
  2362.         const struct firmware *ce_fw;   /* SI CE firmware */
  2363.         const struct firmware *mec_fw;  /* CIK MEC firmware */
  2364.         const struct firmware *mec2_fw; /* KV MEC2 firmware */
  2365.         const struct firmware *sdma_fw; /* CIK SDMA firmware */
  2366.         const struct firmware *smc_fw;  /* SMC firmware */
  2367.         const struct firmware *uvd_fw;  /* UVD firmware */
  2368.         const struct firmware *vce_fw;  /* VCE firmware */
  2369.         bool new_fw;
  2370.         struct r600_vram_scratch vram_scratch;
  2371.         int msi_enabled; /* msi enabled */
  2372.         struct r600_ih ih; /* r6/700 interrupt ring */
  2373.         struct radeon_rlc rlc;
  2374.         struct radeon_mec mec;
  2375.         struct work_struct hotplug_work;
  2376.         struct work_struct audio_work;
  2377.         int num_crtc; /* number of crtcs */
  2378.         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
  2379.         bool has_uvd;
  2380.         struct r600_audio audio; /* audio stuff */
  2381.         /* only one userspace can use Hyperz features or CMASK at a time */
  2382.         struct drm_file *hyperz_filp;
  2383.         struct drm_file *cmask_filp;
  2384.         /* i2c buses */
  2385.         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
  2386.         /* debugfs */
  2387.         struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
  2388.         unsigned                debugfs_count;
  2389.         /* virtual memory */
  2390.         struct radeon_vm_manager        vm_manager;
  2391.         struct mutex                    gpu_clock_mutex;
  2392.         /* memory stats */
  2393.         atomic64_t                      vram_usage;
  2394.         atomic64_t                      gtt_usage;
  2395.         atomic64_t                      num_bytes_moved;
  2396.         /* ACPI interface */
  2397.         struct radeon_atif              atif;
  2398.         struct radeon_atcs              atcs;
  2399.         /* srbm instance registers */
  2400.         struct mutex                    srbm_mutex;
  2401.         /* GRBM index mutex. Protects concurrents access to GRBM index */
  2402.         struct mutex                    grbm_idx_mutex;
  2403.         /* clock, powergating flags */
  2404.         u32 cg_flags;
  2405.         u32 pg_flags;
  2406.  
  2407. //      struct dev_pm_domain vga_pm_domain;
  2408.         bool have_disp_power_ref;
  2409.         u32 px_quirk_flags;
  2410.  
  2411.         /* tracking pinned memory */
  2412.         u64 vram_pin_size;
  2413.         u64 gart_pin_size;
  2414.         struct mutex    mn_lock;
  2415. };
  2416.  
  2417. bool radeon_is_px(struct drm_device *dev);
  2418. int radeon_device_init(struct radeon_device *rdev,
  2419.                        struct drm_device *ddev,
  2420.                        struct pci_dev *pdev,
  2421.                        uint32_t flags);
  2422. void radeon_device_fini(struct radeon_device *rdev);
  2423. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  2424.  
  2425. #define RADEON_MIN_MMIO_SIZE 0x10000
  2426.  
  2427. static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
  2428.                                     bool always_indirect)
  2429. {
  2430.         /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
  2431.         if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
  2432.                 return readl(((void __iomem *)rdev->rmmio) + reg);
  2433.         else {
  2434.                 unsigned long flags;
  2435.                 uint32_t ret;
  2436.  
  2437.                 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
  2438.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  2439.                 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  2440.                 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
  2441.  
  2442.                 return ret;
  2443.         }
  2444. }
  2445.  
  2446. static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
  2447.                                 bool always_indirect)
  2448. {
  2449.         if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
  2450.                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
  2451.         else {
  2452.                 unsigned long flags;
  2453.  
  2454.                 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
  2455.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  2456.                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  2457.                 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
  2458.         }
  2459. }
  2460.  
  2461. u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
  2462. void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  2463.  
  2464. u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
  2465. void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
  2466.  
  2467. /*
  2468.  * Cast helper
  2469.  */
  2470. extern const struct fence_ops radeon_fence_ops;
  2471.  
  2472. static inline struct radeon_fence *to_radeon_fence(struct fence *f)
  2473. {
  2474.         struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
  2475.  
  2476.         if (__f->base.ops == &radeon_fence_ops)
  2477.                 return __f;
  2478.  
  2479.         return NULL;
  2480. }
  2481.  
  2482. /*
  2483.  * Registers read & write functions.
  2484.  */
  2485. #define RREG8(reg) readb((rdev->rmmio) + (reg))
  2486. #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
  2487. #define RREG16(reg) readw((rdev->rmmio) + (reg))
  2488. #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
  2489. #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
  2490. #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
  2491. #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
  2492. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
  2493. #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
  2494. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  2495. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  2496. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  2497. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  2498. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  2499. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  2500. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  2501. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  2502. #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
  2503. #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
  2504. #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
  2505. #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
  2506. #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
  2507. #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
  2508. #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
  2509. #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
  2510. #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
  2511. #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
  2512. #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
  2513. #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
  2514. #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
  2515. #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
  2516. #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
  2517. #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
  2518. #define WREG32_P(reg, val, mask)                                \
  2519.         do {                                                    \
  2520.                 uint32_t tmp_ = RREG32(reg);                    \
  2521.                 tmp_ &= (mask);                                 \
  2522.                 tmp_ |= ((val) & ~(mask));                      \
  2523.                 WREG32(reg, tmp_);                              \
  2524.         } while (0)
  2525. #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
  2526. #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
  2527. #define WREG32_PLL_P(reg, val, mask)                            \
  2528.         do {                                                    \
  2529.                 uint32_t tmp_ = RREG32_PLL(reg);                \
  2530.                 tmp_ &= (mask);                                 \
  2531.                 tmp_ |= ((val) & ~(mask));                      \
  2532.                 WREG32_PLL(reg, tmp_);                          \
  2533.         } while (0)
  2534. #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
  2535. #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
  2536. #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
  2537.  
  2538. #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
  2539. #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
  2540.  
  2541. /*
  2542.  * Indirect registers accessor
  2543.  */
  2544. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  2545. {
  2546.         unsigned long flags;
  2547.         uint32_t r;
  2548.  
  2549.         spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
  2550.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  2551.         r = RREG32(RADEON_PCIE_DATA);
  2552.         spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
  2553.         return r;
  2554. }
  2555.  
  2556. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  2557. {
  2558.         unsigned long flags;
  2559.  
  2560.         spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
  2561.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  2562.         WREG32(RADEON_PCIE_DATA, (v));
  2563.         spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
  2564. }
  2565.  
  2566. static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
  2567. {
  2568.         unsigned long flags;
  2569.         u32 r;
  2570.  
  2571.         spin_lock_irqsave(&rdev->smc_idx_lock, flags);
  2572.         WREG32(TN_SMC_IND_INDEX_0, (reg));
  2573.         r = RREG32(TN_SMC_IND_DATA_0);
  2574.         spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
  2575.         return r;
  2576. }
  2577.  
  2578. static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  2579. {
  2580.         unsigned long flags;
  2581.  
  2582.         spin_lock_irqsave(&rdev->smc_idx_lock, flags);
  2583.         WREG32(TN_SMC_IND_INDEX_0, (reg));
  2584.         WREG32(TN_SMC_IND_DATA_0, (v));
  2585.         spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
  2586. }
  2587.  
  2588. static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
  2589. {
  2590.         unsigned long flags;
  2591.         u32 r;
  2592.  
  2593.         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
  2594.         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
  2595.         r = RREG32(R600_RCU_DATA);
  2596.         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
  2597.         return r;
  2598. }
  2599.  
  2600. static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  2601. {
  2602.         unsigned long flags;
  2603.  
  2604.         spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
  2605.         WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
  2606.         WREG32(R600_RCU_DATA, (v));
  2607.         spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
  2608. }
  2609.  
  2610. static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
  2611. {
  2612.         unsigned long flags;
  2613.         u32 r;
  2614.  
  2615.         spin_lock_irqsave(&rdev->cg_idx_lock, flags);
  2616.         WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
  2617.         r = RREG32(EVERGREEN_CG_IND_DATA);
  2618.         spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
  2619.         return r;
  2620. }
  2621.  
  2622. static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  2623. {
  2624.         unsigned long flags;
  2625.  
  2626.         spin_lock_irqsave(&rdev->cg_idx_lock, flags);
  2627.         WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
  2628.         WREG32(EVERGREEN_CG_IND_DATA, (v));
  2629.         spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
  2630. }
  2631.  
  2632. static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
  2633. {
  2634.         unsigned long flags;
  2635.         u32 r;
  2636.  
  2637.         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
  2638.         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
  2639.         r = RREG32(EVERGREEN_PIF_PHY0_DATA);
  2640.         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
  2641.         return r;
  2642. }
  2643.  
  2644. static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  2645. {
  2646.         unsigned long flags;
  2647.  
  2648.         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
  2649.         WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
  2650.         WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
  2651.         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
  2652. }
  2653.  
  2654. static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
  2655. {
  2656.         unsigned long flags;
  2657.         u32 r;
  2658.  
  2659.         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
  2660.         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
  2661.         r = RREG32(EVERGREEN_PIF_PHY1_DATA);
  2662.         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
  2663.         return r;
  2664. }
  2665.  
  2666. static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  2667. {
  2668.         unsigned long flags;
  2669.  
  2670.         spin_lock_irqsave(&rdev->pif_idx_lock, flags);
  2671.         WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
  2672.         WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
  2673.         spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
  2674. }
  2675.  
  2676. static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
  2677. {
  2678.         unsigned long flags;
  2679.         u32 r;
  2680.  
  2681.         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
  2682.         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
  2683.         r = RREG32(R600_UVD_CTX_DATA);
  2684.         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
  2685.         return r;
  2686. }
  2687.  
  2688. static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  2689. {
  2690.         unsigned long flags;
  2691.  
  2692.         spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
  2693.         WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
  2694.         WREG32(R600_UVD_CTX_DATA, (v));
  2695.         spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
  2696. }
  2697.  
  2698.  
  2699. static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
  2700. {
  2701.         unsigned long flags;
  2702.         u32 r;
  2703.  
  2704.         spin_lock_irqsave(&rdev->didt_idx_lock, flags);
  2705.         WREG32(CIK_DIDT_IND_INDEX, (reg));
  2706.         r = RREG32(CIK_DIDT_IND_DATA);
  2707.         spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
  2708.         return r;
  2709. }
  2710.  
  2711. static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  2712. {
  2713.         unsigned long flags;
  2714.  
  2715.         spin_lock_irqsave(&rdev->didt_idx_lock, flags);
  2716.         WREG32(CIK_DIDT_IND_INDEX, (reg));
  2717.         WREG32(CIK_DIDT_IND_DATA, (v));
  2718.         spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
  2719. }
  2720.  
  2721. void r100_pll_errata_after_index(struct radeon_device *rdev);
  2722.  
  2723.  
  2724. /*
  2725.  * ASICs helpers.
  2726.  */
  2727. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  2728.                             (rdev->pdev->device == 0x5969))
  2729. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  2730.         (rdev->family == CHIP_RV200) || \
  2731.         (rdev->family == CHIP_RS100) || \
  2732.         (rdev->family == CHIP_RS200) || \
  2733.         (rdev->family == CHIP_RV250) || \
  2734.         (rdev->family == CHIP_RV280) || \
  2735.         (rdev->family == CHIP_RS300))
  2736. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
  2737.         (rdev->family == CHIP_RV350) ||         \
  2738.         (rdev->family == CHIP_R350)  ||         \
  2739.         (rdev->family == CHIP_RV380) ||         \
  2740.         (rdev->family == CHIP_R420)  ||         \
  2741.         (rdev->family == CHIP_R423)  ||         \
  2742.         (rdev->family == CHIP_RV410) ||         \
  2743.         (rdev->family == CHIP_RS400) ||         \
  2744.         (rdev->family == CHIP_RS480))
  2745. #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
  2746.                 (rdev->ddev->pdev->device == 0x9443) || \
  2747.                 (rdev->ddev->pdev->device == 0x944B) || \
  2748.                 (rdev->ddev->pdev->device == 0x9506) || \
  2749.                 (rdev->ddev->pdev->device == 0x9509) || \
  2750.                 (rdev->ddev->pdev->device == 0x950F) || \
  2751.                 (rdev->ddev->pdev->device == 0x689C) || \
  2752.                 (rdev->ddev->pdev->device == 0x689D))
  2753. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  2754. #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
  2755.                             (rdev->family == CHIP_RS690)  ||    \
  2756.                             (rdev->family == CHIP_RS740)  ||    \
  2757.                             (rdev->family >= CHIP_R600))
  2758. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  2759. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  2760. #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
  2761. #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
  2762.                              (rdev->flags & RADEON_IS_IGP))
  2763. #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
  2764. #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
  2765. #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
  2766.                              (rdev->flags & RADEON_IS_IGP))
  2767. #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
  2768. #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
  2769. #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
  2770. #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
  2771. #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
  2772. #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
  2773.                              (rdev->family == CHIP_MULLINS))
  2774.  
  2775. #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
  2776.                               (rdev->ddev->pdev->device == 0x6850) || \
  2777.                               (rdev->ddev->pdev->device == 0x6858) || \
  2778.                               (rdev->ddev->pdev->device == 0x6859) || \
  2779.                               (rdev->ddev->pdev->device == 0x6840) || \
  2780.                               (rdev->ddev->pdev->device == 0x6841) || \
  2781.                               (rdev->ddev->pdev->device == 0x6842) || \
  2782.                               (rdev->ddev->pdev->device == 0x6843))
  2783.  
  2784. /*
  2785.  * BIOS helpers.
  2786.  */
  2787. #define RBIOS8(i) (rdev->bios[i])
  2788. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  2789. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  2790.  
  2791. int radeon_combios_init(struct radeon_device *rdev);
  2792. void radeon_combios_fini(struct radeon_device *rdev);
  2793. int radeon_atombios_init(struct radeon_device *rdev);
  2794. void radeon_atombios_fini(struct radeon_device *rdev);
  2795.  
  2796.  
  2797. /*
  2798.  * RING helpers.
  2799.  */
  2800.  
  2801. /**
  2802.  * radeon_ring_write - write a value to the ring
  2803.  *
  2804.  * @ring: radeon_ring structure holding ring information
  2805.  * @v: dword (dw) value to write
  2806.  *
  2807.  * Write a value to the requested ring buffer (all asics).
  2808.  */
  2809. static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
  2810. {
  2811.         if (ring->count_dw <= 0)
  2812.                 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
  2813.  
  2814.         ring->ring[ring->wptr++] = v;
  2815.         ring->wptr &= ring->ptr_mask;
  2816.         ring->count_dw--;
  2817.         ring->ring_free_dw--;
  2818. }
  2819.  
  2820. /*
  2821.  * ASICs macro.
  2822.  */
  2823. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  2824. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  2825. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  2826. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  2827. #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
  2828. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  2829. #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
  2830. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
  2831. #define radeon_gart_set_page(rdev, i, p, f) (rdev)->asic->gart.set_page((rdev), (i), (p), (f))
  2832. #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
  2833. #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
  2834. #define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
  2835. #define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
  2836. #define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
  2837. #define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
  2838. #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
  2839. #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
  2840. #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
  2841. #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
  2842. #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
  2843. #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
  2844. #define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
  2845. #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
  2846. #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
  2847. #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
  2848. #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
  2849. #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
  2850. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
  2851. #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
  2852. #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
  2853. #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
  2854. #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
  2855. #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
  2856. #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
  2857. #define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
  2858. #define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
  2859. #define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
  2860. #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
  2861. #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
  2862. #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
  2863. #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
  2864. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
  2865. #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
  2866. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
  2867. #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
  2868. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
  2869. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
  2870. #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
  2871. #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
  2872. #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
  2873. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
  2874. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
  2875. #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
  2876. #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
  2877. #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
  2878. #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
  2879. #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
  2880. #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
  2881. #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
  2882. #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
  2883. #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
  2884. #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
  2885. #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
  2886. #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
  2887. #define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
  2888. #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
  2889. #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
  2890. #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
  2891. #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
  2892. #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
  2893. #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
  2894. #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
  2895. #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
  2896. #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
  2897. #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
  2898. #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
  2899. #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
  2900. #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
  2901. #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
  2902. #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
  2903. #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
  2904. #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
  2905. #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
  2906. #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
  2907. #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
  2908. #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
  2909. #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
  2910.  
  2911. /* Common functions */
  2912. /* AGP */
  2913. extern int radeon_gpu_reset(struct radeon_device *rdev);
  2914. extern void radeon_pci_config_reset(struct radeon_device *rdev);
  2915. extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
  2916. extern void radeon_agp_disable(struct radeon_device *rdev);
  2917. extern int radeon_modeset_init(struct radeon_device *rdev);
  2918. extern void radeon_modeset_fini(struct radeon_device *rdev);
  2919. extern bool radeon_card_posted(struct radeon_device *rdev);
  2920. extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
  2921. extern void radeon_update_display_priority(struct radeon_device *rdev);
  2922. extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
  2923. extern void radeon_scratch_init(struct radeon_device *rdev);
  2924. extern void radeon_wb_fini(struct radeon_device *rdev);
  2925. extern int radeon_wb_init(struct radeon_device *rdev);
  2926. extern void radeon_wb_disable(struct radeon_device *rdev);
  2927. extern void radeon_surface_init(struct radeon_device *rdev);
  2928. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  2929. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  2930. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  2931. extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
  2932. extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
  2933. extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
  2934.                                      uint32_t flags);
  2935. extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
  2936. extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
  2937. extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
  2938. extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
  2939. extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
  2940. extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
  2941. extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
  2942. extern void radeon_program_register_sequence(struct radeon_device *rdev,
  2943.                                              const u32 *registers,
  2944.                                              const u32 array_size);
  2945.  
  2946. /*
  2947.  * vm
  2948.  */
  2949. int radeon_vm_manager_init(struct radeon_device *rdev);
  2950. void radeon_vm_manager_fini(struct radeon_device *rdev);
  2951. int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
  2952. void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
  2953. struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
  2954.                                           struct radeon_vm *vm,
  2955.                                           struct list_head *head);
  2956. struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
  2957.                                        struct radeon_vm *vm, int ring);
  2958. void radeon_vm_flush(struct radeon_device *rdev,
  2959.                      struct radeon_vm *vm,
  2960.                      int ring, struct radeon_fence *fence);
  2961. void radeon_vm_fence(struct radeon_device *rdev,
  2962.                      struct radeon_vm *vm,
  2963.                      struct radeon_fence *fence);
  2964. uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
  2965. int radeon_vm_update_page_directory(struct radeon_device *rdev,
  2966.                                     struct radeon_vm *vm);
  2967. int radeon_vm_clear_freed(struct radeon_device *rdev,
  2968.                           struct radeon_vm *vm);
  2969. int radeon_vm_clear_invalids(struct radeon_device *rdev,
  2970.                              struct radeon_vm *vm);
  2971. int radeon_vm_bo_update(struct radeon_device *rdev,
  2972.                         struct radeon_bo_va *bo_va,
  2973.                         struct ttm_mem_reg *mem);
  2974. void radeon_vm_bo_invalidate(struct radeon_device *rdev,
  2975.                              struct radeon_bo *bo);
  2976. struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
  2977.                                        struct radeon_bo *bo);
  2978. struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
  2979.                                       struct radeon_vm *vm,
  2980.                                       struct radeon_bo *bo);
  2981. int radeon_vm_bo_set_addr(struct radeon_device *rdev,
  2982.                           struct radeon_bo_va *bo_va,
  2983.                           uint64_t offset,
  2984.                           uint32_t flags);
  2985. void radeon_vm_bo_rmv(struct radeon_device *rdev,
  2986.                      struct radeon_bo_va *bo_va);
  2987.  
  2988. /* audio */
  2989. void r600_audio_update_hdmi(struct work_struct *work);
  2990. struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
  2991. struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
  2992. void r600_audio_enable(struct radeon_device *rdev,
  2993.                        struct r600_audio_pin *pin,
  2994.                        u8 enable_mask);
  2995. void dce6_audio_enable(struct radeon_device *rdev,
  2996.                        struct r600_audio_pin *pin,
  2997.                        u8 enable_mask);
  2998.  
  2999. /*
  3000.  * R600 vram scratch functions
  3001.  */
  3002. int r600_vram_scratch_init(struct radeon_device *rdev);
  3003. void r600_vram_scratch_fini(struct radeon_device *rdev);
  3004.  
  3005. /*
  3006.  * r600 cs checking helper
  3007.  */
  3008. unsigned r600_mip_minify(unsigned size, unsigned level);
  3009. bool r600_fmt_is_valid_color(u32 format);
  3010. bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
  3011. int r600_fmt_get_blocksize(u32 format);
  3012. int r600_fmt_get_nblocksx(u32 format, u32 w);
  3013. int r600_fmt_get_nblocksy(u32 format, u32 h);
  3014.  
  3015. /*
  3016.  * r600 functions used by radeon_encoder.c
  3017.  */
  3018. struct radeon_hdmi_acr {
  3019.         u32 clock;
  3020.  
  3021.         int n_32khz;
  3022.         int cts_32khz;
  3023.  
  3024.         int n_44_1khz;
  3025.         int cts_44_1khz;
  3026.  
  3027.         int n_48khz;
  3028.         int cts_48khz;
  3029.  
  3030. };
  3031.  
  3032. extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
  3033.  
  3034. extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
  3035.                                      u32 tiling_pipe_num,
  3036.                                      u32 max_rb_num,
  3037.                                      u32 total_max_rb_num,
  3038.                                      u32 enabled_rb_mask);
  3039.  
  3040. /*
  3041.  * evergreen functions used by radeon_encoder.c
  3042.  */
  3043.  
  3044. extern int ni_init_microcode(struct radeon_device *rdev);
  3045. extern int ni_mc_load_microcode(struct radeon_device *rdev);
  3046.  
  3047. /* radeon_acpi.c */
  3048. #if defined(CONFIG_ACPI)
  3049. extern int radeon_acpi_init(struct radeon_device *rdev);
  3050. extern void radeon_acpi_fini(struct radeon_device *rdev);
  3051. extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
  3052. extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
  3053.                                                 u8 perf_req, bool advertise);
  3054. extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
  3055. #else
  3056. static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
  3057. static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
  3058. #endif
  3059.  
  3060. int radeon_cs_packet_parse(struct radeon_cs_parser *p,
  3061.                            struct radeon_cs_packet *pkt,
  3062.                            unsigned idx);
  3063. bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
  3064. void radeon_cs_dump_packet(struct radeon_cs_parser *p,
  3065.                            struct radeon_cs_packet *pkt);
  3066. int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
  3067.                                 struct radeon_bo_list **cs_reloc,
  3068.                                 int nomm);
  3069. int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
  3070.                                uint32_t *vline_start_end,
  3071.                                uint32_t *vline_status);
  3072.  
  3073. #include "radeon_object.h"
  3074.  
  3075. #define PCI_DEVICE_ID_ATI_RADEON_QY     0x5159
  3076.  
  3077. resource_size_t
  3078. drm_get_resource_start(struct drm_device *dev, unsigned int resource);
  3079. resource_size_t
  3080. drm_get_resource_len(struct drm_device *dev, unsigned int resource);
  3081.  
  3082.  
  3083. #endif
  3084.