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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30.  
  31. /* TODO: Here are things that needs to be done :
  32.  *      - surface allocator & initializer : (bit like scratch reg) should
  33.  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34.  *        related to surface
  35.  *      - WB : write back stuff (do it bit like scratch reg things)
  36.  *      - Vblank : look at Jesse's rework and what we should do
  37.  *      - r600/r700: gart & cp
  38.  *      - cs : clean cs ioctl use bitmap & things like that.
  39.  *      - power management stuff
  40.  *      - Barrier in gart code
  41.  *      - Unmappabled vram ?
  42.  *      - TESTING, TESTING, TESTING
  43.  */
  44.  
  45. /* Initialization path:
  46.  *  We expect that acceleration initialization might fail for various
  47.  *  reasons even thought we work hard to make it works on most
  48.  *  configurations. In order to still have a working userspace in such
  49.  *  situation the init path must succeed up to the memory controller
  50.  *  initialization point. Failure before this point are considered as
  51.  *  fatal error. Here is the init callchain :
  52.  *      radeon_device_init  perform common structure, mutex initialization
  53.  *      asic_init           setup the GPU memory layout and perform all
  54.  *                          one time initialization (failure in this
  55.  *                          function are considered fatal)
  56.  *      asic_startup        setup the GPU acceleration, in order to
  57.  *                          follow guideline the first thing this
  58.  *                          function should do is setting the GPU
  59.  *                          memory controller (only MC setup failure
  60.  *                          are considered as fatal)
  61.  */
  62.  
  63. #include <asm/atomic.h>
  64. #include <linux/wait.h>
  65. #include <linux/list.h>
  66. #include <linux/kref.h>
  67. #include <asm/div64.h>
  68.  
  69. #include <ttm/ttm_bo_api.h>
  70. #include <ttm/ttm_bo_driver.h>
  71. #include <ttm/ttm_placement.h>
  72. #include <ttm/ttm_module.h>
  73.  
  74. #include <linux/irqreturn.h>
  75. #include <pci.h>
  76.  
  77. #include <errno-base.h>
  78.  
  79. #include "radeon_family.h"
  80. #include "radeon_mode.h"
  81. #include "radeon_reg.h"
  82.  
  83. #include <syscall.h>
  84.  
  85. /*
  86.  * Modules parameters.
  87.  */
  88. extern int radeon_no_wb;
  89. extern int radeon_modeset;
  90. extern int radeon_dynclks;
  91. extern int radeon_r4xx_atom;
  92. extern int radeon_agpmode;
  93. extern int radeon_vram_limit;
  94. extern int radeon_gart_size;
  95. extern int radeon_benchmarking;
  96. extern int radeon_testing;
  97. extern int radeon_connector_table;
  98. extern int radeon_tv;
  99. extern int radeon_audio;
  100. extern int radeon_disp_priority;
  101. extern int radeon_hw_i2c;
  102. extern int radeon_pcie_gen2;
  103. extern int radeon_msi;
  104. extern int radeon_lockup_timeout;
  105.  
  106.  
  107.  
  108. typedef struct pm_message {
  109.     int event;
  110. } pm_message_t;
  111.  
  112. typedef struct
  113. {
  114.   int width;
  115.   int height;
  116.   int bpp;
  117.   int freq;
  118. }videomode_t;
  119.  
  120.  
  121.  
  122. static inline u32 ioread32(const volatile void __iomem *addr)
  123. {
  124.     return in32((u32)addr);
  125. }
  126.  
  127. static inline void iowrite32(uint32_t b, volatile void __iomem *addr)
  128. {
  129.     out32((u32)addr, b);
  130. }
  131.  
  132. //struct __wait_queue_head {
  133. //        spinlock_t lock;
  134. //        struct list_head task_list;
  135. //};
  136. //typedef struct __wait_queue_head wait_queue_head_t;
  137.  
  138.  
  139. /*
  140.  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  141.  * symbol;
  142.  */
  143. #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  144. #define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
  145. /* RADEON_IB_POOL_SIZE must be a power of 2 */
  146. #define RADEON_IB_POOL_SIZE             16
  147. #define RADEON_DEBUGFS_MAX_COMPONENTS   32
  148. #define RADEONFB_CONN_LIMIT             4
  149. #define RADEON_BIOS_NUM_SCRATCH         8
  150.  
  151. /* max number of rings */
  152. #define RADEON_NUM_RINGS 3
  153.  
  154. /* fence seq are set to this number when signaled */
  155. #define RADEON_FENCE_SIGNALED_SEQ               0LL
  156.  
  157. /* internal ring indices */
  158. /* r1xx+ has gfx CP ring */
  159. #define RADEON_RING_TYPE_GFX_INDEX  0
  160.  
  161. /* cayman has 2 compute CP rings */
  162. #define CAYMAN_RING_TYPE_CP1_INDEX 1
  163. #define CAYMAN_RING_TYPE_CP2_INDEX 2
  164.  
  165. /* hardcode those limit for now */
  166. #define RADEON_VA_IB_OFFSET                     (1 << 20)
  167. #define RADEON_VA_RESERVED_SIZE         (8 << 20)
  168. #define RADEON_IB_VM_MAX_SIZE           (64 << 10)
  169.  
  170. /*
  171.  * Errata workarounds.
  172.  */
  173. enum radeon_pll_errata {
  174.     CHIP_ERRATA_R300_CG             = 0x00000001,
  175.     CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  176.     CHIP_ERRATA_PLL_DELAY           = 0x00000004
  177. };
  178.  
  179.  
  180. struct radeon_device;
  181.  
  182.  
  183. /*
  184.  * BIOS.
  185.  */
  186. bool radeon_get_bios(struct radeon_device *rdev);
  187.  
  188. /*
  189.  * Dummy page
  190.  */
  191. struct radeon_dummy_page {
  192.         struct page     *page;
  193.         dma_addr_t      addr;
  194. };
  195. int radeon_dummy_page_init(struct radeon_device *rdev);
  196. void radeon_dummy_page_fini(struct radeon_device *rdev);
  197.  
  198.  
  199. /*
  200.  * Clocks
  201.  */
  202. struct radeon_clock {
  203.         struct radeon_pll p1pll;
  204.         struct radeon_pll p2pll;
  205.         struct radeon_pll dcpll;
  206.         struct radeon_pll spll;
  207.         struct radeon_pll mpll;
  208.         /* 10 Khz units */
  209.         uint32_t default_mclk;
  210.         uint32_t default_sclk;
  211.         uint32_t default_dispclk;
  212.         uint32_t dp_extclk;
  213.         uint32_t max_pixel_clock;
  214. };
  215.  
  216. /*
  217.  * Power management
  218.  */
  219. int radeon_pm_init(struct radeon_device *rdev);
  220. void radeon_pm_fini(struct radeon_device *rdev);
  221. void radeon_pm_compute_clocks(struct radeon_device *rdev);
  222. void radeon_pm_suspend(struct radeon_device *rdev);
  223. void radeon_pm_resume(struct radeon_device *rdev);
  224. void radeon_combios_get_power_modes(struct radeon_device *rdev);
  225. void radeon_atombios_get_power_modes(struct radeon_device *rdev);
  226. void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
  227. void rs690_pm_info(struct radeon_device *rdev);
  228. extern int rv6xx_get_temp(struct radeon_device *rdev);
  229. extern int rv770_get_temp(struct radeon_device *rdev);
  230. extern int evergreen_get_temp(struct radeon_device *rdev);
  231. extern int sumo_get_temp(struct radeon_device *rdev);
  232. extern int si_get_temp(struct radeon_device *rdev);
  233. extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
  234.                                     unsigned *bankh, unsigned *mtaspect,
  235.                                     unsigned *tile_split);
  236.  
  237. /*
  238.  * Fences.
  239.  */
  240. struct radeon_fence_driver {
  241.         uint32_t                        scratch_reg;
  242.         uint64_t                        gpu_addr;
  243.         volatile uint32_t               *cpu_addr;
  244.         /* sync_seq is protected by ring emission lock */
  245.         uint64_t                        sync_seq[RADEON_NUM_RINGS];
  246.         atomic64_t                      last_seq;
  247.         unsigned long                   last_activity;
  248.         bool                            initialized;
  249. };
  250.  
  251. struct radeon_fence {
  252.     struct radeon_device   *rdev;
  253.     struct kref             kref;
  254.         /* protected by radeon_fence.lock */
  255.         uint64_t                        seq;
  256.         /* RB, DMA, etc. */
  257.         unsigned                        ring;
  258. };
  259.  
  260. int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
  261. int radeon_fence_driver_init(struct radeon_device *rdev);
  262. void radeon_fence_driver_fini(struct radeon_device *rdev);
  263. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
  264. void radeon_fence_process(struct radeon_device *rdev, int ring);
  265. bool radeon_fence_signaled(struct radeon_fence *fence);
  266. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  267. int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring);
  268. void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring);
  269. int radeon_fence_wait_any(struct radeon_device *rdev,
  270.                           struct radeon_fence **fences,
  271.                           bool intr);
  272. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  273. void radeon_fence_unref(struct radeon_fence **fence);
  274. unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
  275. bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
  276. void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
  277. static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
  278.                                                       struct radeon_fence *b)
  279. {
  280.         if (!a) {
  281.                 return b;
  282.         }
  283.  
  284.         if (!b) {
  285.                 return a;
  286.         }
  287.  
  288.         BUG_ON(a->ring != b->ring);
  289.  
  290.         if (a->seq > b->seq) {
  291.                 return a;
  292.         } else {
  293.                 return b;
  294.         }
  295. }
  296.  
  297. static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
  298.                                            struct radeon_fence *b)
  299. {
  300.         if (!a) {
  301.                 return false;
  302.         }
  303.  
  304.         if (!b) {
  305.                 return true;
  306.         }
  307.  
  308.         BUG_ON(a->ring != b->ring);
  309.  
  310.         return a->seq < b->seq;
  311. }
  312.  
  313. /*
  314.  * Tiling registers
  315.  */
  316. struct radeon_surface_reg {
  317.         struct radeon_bo *bo;
  318. };
  319.  
  320. #define RADEON_GEM_MAX_SURFACES 8
  321.  
  322. /*
  323.  * TTM.
  324.  */
  325. struct radeon_mman {
  326.         struct ttm_bo_global_ref        bo_global_ref;
  327. //      struct drm_global_reference     mem_global_ref;
  328.         struct ttm_bo_device            bdev;
  329.         bool                            mem_global_referenced;
  330.         bool                            initialized;
  331. };
  332.  
  333. /* bo virtual address in a specific vm */
  334. struct radeon_bo_va {
  335.         /* protected by bo being reserved */
  336.         struct list_head                bo_list;
  337.         uint64_t                        soffset;
  338.         uint64_t                        eoffset;
  339.         uint32_t                        flags;
  340.         bool                            valid;
  341.         unsigned                        ref_count;
  342.  
  343.         /* protected by vm mutex */
  344.         struct list_head                vm_list;
  345.  
  346.         /* constant after initialization */
  347.         struct radeon_vm                *vm;
  348.         struct radeon_bo                *bo;
  349. };
  350.  
  351. struct radeon_bo {
  352.         /* Protected by gem.mutex */
  353.         struct list_head                list;
  354.         /* Protected by tbo.reserved */
  355.         u32                             placements[3];
  356.         struct ttm_placement            placement;
  357.         struct ttm_buffer_object        tbo;
  358.         struct ttm_bo_kmap_obj          kmap;
  359.     unsigned                    pin_count;
  360.     void                       *kptr;
  361.     void                       *uptr;
  362.     u32                         cpu_addr;
  363.     u32                         tiling_flags;
  364.     u32                         pitch;
  365.     int                         surface_reg;
  366.         /* list of all virtual address to which this bo
  367.          * is associated to
  368.          */
  369.         struct list_head                va;
  370.         /* Constant after initialization */
  371.         struct radeon_device            *rdev;
  372.         struct drm_gem_object           gem_base;
  373.     u32                          domain;
  374.         int vmapping_count;
  375. };
  376. #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
  377.  
  378. struct radeon_bo_list {
  379.         struct radeon_bo        *bo;
  380.         uint64_t                gpu_offset;
  381.         unsigned                rdomain;
  382.         unsigned                wdomain;
  383.         u32                     tiling_flags;
  384. };
  385.  
  386. /* sub-allocation manager, it has to be protected by another lock.
  387.  * By conception this is an helper for other part of the driver
  388.  * like the indirect buffer or semaphore, which both have their
  389.  * locking.
  390.  *
  391.  * Principe is simple, we keep a list of sub allocation in offset
  392.  * order (first entry has offset == 0, last entry has the highest
  393.  * offset).
  394.  *
  395.  * When allocating new object we first check if there is room at
  396.  * the end total_size - (last_object_offset + last_object_size) >=
  397.  * alloc_size. If so we allocate new object there.
  398.  *
  399.  * When there is not enough room at the end, we start waiting for
  400.  * each sub object until we reach object_offset+object_size >=
  401.  * alloc_size, this object then become the sub object we return.
  402.  *
  403.  * Alignment can't be bigger than page size.
  404.  *
  405.  * Hole are not considered for allocation to keep things simple.
  406.  * Assumption is that there won't be hole (all object on same
  407.  * alignment).
  408.  */
  409. struct radeon_sa_manager {
  410.         wait_queue_head_t       wq;
  411.         struct radeon_bo        *bo;
  412.         struct list_head        *hole;
  413.         struct list_head        flist[RADEON_NUM_RINGS];
  414.         struct list_head        olist;
  415.         unsigned                size;
  416.         uint64_t                gpu_addr;
  417.         void                    *cpu_ptr;
  418.         uint32_t                domain;
  419. };
  420.  
  421. struct radeon_sa_bo;
  422.  
  423. /* sub-allocation buffer */
  424. struct radeon_sa_bo {
  425.         struct list_head                olist;
  426.         struct list_head                flist;
  427.         struct radeon_sa_manager        *manager;
  428.         unsigned                        soffset;
  429.         unsigned                        eoffset;
  430.         struct radeon_fence             *fence;
  431. };
  432.  
  433. /*
  434.  * GEM objects.
  435.  */
  436. struct radeon_gem {
  437.         struct mutex            mutex;
  438.         struct list_head        objects;
  439. };
  440.  
  441. int radeon_gem_init(struct radeon_device *rdev);
  442. void radeon_gem_fini(struct radeon_device *rdev);
  443. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  444.                              int alignment, int initial_domain,
  445.                              bool discardable, bool kernel,
  446.                              struct drm_gem_object **obj);
  447.  
  448. int radeon_mode_dumb_create(struct drm_file *file_priv,
  449.                             struct drm_device *dev,
  450.                             struct drm_mode_create_dumb *args);
  451. int radeon_mode_dumb_mmap(struct drm_file *filp,
  452.                           struct drm_device *dev,
  453.                           uint32_t handle, uint64_t *offset_p);
  454. int radeon_mode_dumb_destroy(struct drm_file *file_priv,
  455.                              struct drm_device *dev,
  456.                              uint32_t handle);
  457.  
  458. /*
  459.  * Semaphores.
  460.  */
  461. /* everything here is constant */
  462. struct radeon_semaphore {
  463.         struct radeon_sa_bo             *sa_bo;
  464.         signed                          waiters;
  465.         uint64_t                        gpu_addr;
  466. };
  467.  
  468. int radeon_semaphore_create(struct radeon_device *rdev,
  469.                             struct radeon_semaphore **semaphore);
  470. void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
  471.                                   struct radeon_semaphore *semaphore);
  472. void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
  473.                                 struct radeon_semaphore *semaphore);
  474. int radeon_semaphore_sync_rings(struct radeon_device *rdev,
  475.                                 struct radeon_semaphore *semaphore,
  476.                                 int signaler, int waiter);
  477. void radeon_semaphore_free(struct radeon_device *rdev,
  478.                            struct radeon_semaphore **semaphore,
  479.                            struct radeon_fence *fence);
  480.  
  481. /*
  482.  * GART structures, functions & helpers
  483.  */
  484. struct radeon_mc;
  485.  
  486. #define RADEON_GPU_PAGE_SIZE 4096
  487. #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
  488. #define RADEON_GPU_PAGE_SHIFT 12
  489. #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
  490.  
  491. struct radeon_gart {
  492.     dma_addr_t          table_addr;
  493.         struct radeon_bo                *robj;
  494.         void                            *ptr;
  495.     unsigned            num_gpu_pages;
  496.     unsigned            num_cpu_pages;
  497.     unsigned            table_size;
  498.     struct page         **pages;
  499.     dma_addr_t          *pages_addr;
  500.     bool                ready;
  501. };
  502.  
  503. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  504. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  505. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  506. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  507. int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  508. void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
  509. int radeon_gart_init(struct radeon_device *rdev);
  510. void radeon_gart_fini(struct radeon_device *rdev);
  511. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  512.                         int pages);
  513. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  514.              int pages, u32 *pagelist,
  515.                      dma_addr_t *dma_addr);
  516. void radeon_gart_restore(struct radeon_device *rdev);
  517.  
  518.  
  519. /*
  520.  * GPU MC structures, functions & helpers
  521.  */
  522. struct radeon_mc {
  523.     resource_size_t     aper_size;
  524.     resource_size_t     aper_base;
  525.     resource_size_t     agp_base;
  526.         /* for some chips with <= 32MB we need to lie
  527.          * about vram size near mc fb location */
  528.         u64                     mc_vram_size;
  529.         u64                     visible_vram_size;
  530.         u64                     gtt_size;
  531.         u64                     gtt_start;
  532.         u64                     gtt_end;
  533.         u64                     vram_start;
  534.         u64                     vram_end;
  535.     unsigned            vram_width;
  536.         u64                     real_vram_size;
  537.     int                 vram_mtrr;
  538.     bool                vram_is_ddr;
  539.         bool                    igp_sideport_enabled;
  540.         u64                     gtt_base_align;
  541. };
  542.  
  543. bool radeon_combios_sideport_present(struct radeon_device *rdev);
  544. bool radeon_atombios_sideport_present(struct radeon_device *rdev);
  545.  
  546. /*
  547.  * GPU scratch registers structures, functions & helpers
  548.  */
  549. struct radeon_scratch {
  550.     unsigned        num_reg;
  551.         uint32_t                reg_base;
  552.     bool            free[32];
  553.     uint32_t        reg[32];
  554. };
  555.  
  556. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  557. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  558.  
  559.  
  560. /*
  561.  * IRQS.
  562.  */
  563. struct r500_irq_stat_regs {
  564.         u32 disp_int;
  565.         u32 hdmi0_status;
  566. };
  567.  
  568. struct r600_irq_stat_regs {
  569.         u32 disp_int;
  570.         u32 disp_int_cont;
  571.         u32 disp_int_cont2;
  572.         u32 d1grph_int;
  573.         u32 d2grph_int;
  574.         u32 hdmi0_status;
  575.         u32 hdmi1_status;
  576. };
  577.  
  578. struct evergreen_irq_stat_regs {
  579.         u32 disp_int;
  580.         u32 disp_int_cont;
  581.         u32 disp_int_cont2;
  582.         u32 disp_int_cont3;
  583.         u32 disp_int_cont4;
  584.         u32 disp_int_cont5;
  585.         u32 d1grph_int;
  586.         u32 d2grph_int;
  587.         u32 d3grph_int;
  588.         u32 d4grph_int;
  589.         u32 d5grph_int;
  590.         u32 d6grph_int;
  591.         u32 afmt_status1;
  592.         u32 afmt_status2;
  593.         u32 afmt_status3;
  594.         u32 afmt_status4;
  595.         u32 afmt_status5;
  596.         u32 afmt_status6;
  597. };
  598.  
  599. union radeon_irq_stat_regs {
  600.         struct r500_irq_stat_regs r500;
  601.         struct r600_irq_stat_regs r600;
  602.         struct evergreen_irq_stat_regs evergreen;
  603. };
  604.  
  605. #define RADEON_MAX_HPD_PINS 6
  606. #define RADEON_MAX_CRTCS 6
  607. #define RADEON_MAX_AFMT_BLOCKS 6
  608.  
  609. struct radeon_irq {
  610.         bool            installed;
  611.         spinlock_t                      lock;
  612.         atomic_t                        ring_int[RADEON_NUM_RINGS];
  613.         bool                            crtc_vblank_int[RADEON_MAX_CRTCS];
  614.         atomic_t                        pflip[RADEON_MAX_CRTCS];
  615.     wait_queue_head_t   vblank_queue;
  616.         bool                            hpd[RADEON_MAX_HPD_PINS];
  617.         bool                            afmt[RADEON_MAX_AFMT_BLOCKS];
  618.         union radeon_irq_stat_regs stat_regs;
  619. };
  620.  
  621. int radeon_irq_kms_init(struct radeon_device *rdev);
  622. void radeon_irq_kms_fini(struct radeon_device *rdev);
  623. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
  624. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
  625. void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
  626. void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
  627. void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
  628. void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
  629. void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
  630. void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
  631.  
  632. /*
  633.  * CP & rings.
  634.  */
  635.  
  636. struct radeon_ib {
  637.         struct radeon_sa_bo             *sa_bo;
  638.         uint32_t                length_dw;
  639.     uint64_t            gpu_addr;
  640.         uint32_t                *ptr;
  641.         int                             ring;
  642.         struct radeon_fence     *fence;
  643.         struct radeon_vm                *vm;
  644.         bool                    is_const_ib;
  645.         struct radeon_fence             *sync_to[RADEON_NUM_RINGS];
  646.         struct radeon_semaphore         *semaphore;
  647. };
  648.  
  649. struct radeon_ring {
  650.         struct radeon_bo        *ring_obj;
  651.         volatile uint32_t       *ring;
  652.     unsigned            rptr;
  653.         unsigned                rptr_offs;
  654.         unsigned                rptr_reg;
  655.         unsigned                rptr_save_reg;
  656.         u64                     next_rptr_gpu_addr;
  657.         volatile u32            *next_rptr_cpu_addr;
  658.     unsigned            wptr;
  659.     unsigned            wptr_old;
  660.         unsigned                wptr_reg;
  661.     unsigned            ring_size;
  662.     unsigned            ring_free_dw;
  663.     int                 count_dw;
  664.         unsigned long           last_activity;
  665.         unsigned                last_rptr;
  666.     uint64_t            gpu_addr;
  667.     uint32_t            align_mask;
  668.     uint32_t            ptr_mask;
  669.     bool                ready;
  670.         u32                     ptr_reg_shift;
  671.         u32                     ptr_reg_mask;
  672.         u32                     nop;
  673.         u32                     idx;
  674. };
  675.  
  676. /*
  677.  * VM
  678.  */
  679.  
  680. /* maximum number of VMIDs */
  681. #define RADEON_NUM_VM   16
  682.  
  683. /* defines number of bits in page table versus page directory,
  684.  * a page is 4KB so we have 12 bits offset, 9 bits in the page
  685.  * table and the remaining 19 bits are in the page directory */
  686. #define RADEON_VM_BLOCK_SIZE   9
  687.  
  688. /* number of entries in page table */
  689. #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
  690.  
  691. struct radeon_vm {
  692.         struct list_head                list;
  693.         struct list_head                va;
  694.         unsigned                        id;
  695.  
  696.         /* contains the page directory */
  697.         struct radeon_sa_bo             *page_directory;
  698.         uint64_t                        pd_gpu_addr;
  699.  
  700.         /* array of page tables, one for each page directory entry */
  701.         struct radeon_sa_bo             **page_tables;
  702.  
  703.         struct mutex                    mutex;
  704.         /* last fence for cs using this vm */
  705.         struct radeon_fence             *fence;
  706.         /* last flush or NULL if we still need to flush */
  707.         struct radeon_fence             *last_flush;
  708. };
  709.  
  710. struct radeon_vm_manager {
  711.         struct mutex                    lock;
  712.         struct list_head                lru_vm;
  713.         struct radeon_fence             *active[RADEON_NUM_VM];
  714.         struct radeon_sa_manager        sa_manager;
  715.         uint32_t                        max_pfn;
  716.         /* number of VMIDs */
  717.         unsigned                        nvm;
  718.         /* vram base address for page table entry  */
  719.         u64                             vram_base_offset;
  720.         /* is vm enabled? */
  721.         bool                            enabled;
  722. };
  723.  
  724. /*
  725.  * file private structure
  726.  */
  727. struct radeon_fpriv {
  728.         struct radeon_vm                vm;
  729. };
  730.  
  731. /*
  732.  * R6xx+ IH ring
  733.  */
  734. struct r600_ih {
  735.         struct radeon_bo        *ring_obj;
  736.         volatile uint32_t       *ring;
  737.     unsigned            rptr;
  738.     unsigned            ring_size;
  739.     uint64_t            gpu_addr;
  740.     uint32_t            ptr_mask;
  741.         atomic_t                lock;
  742.     bool                enabled;
  743. };
  744.  
  745. struct r600_blit_cp_primitives {
  746.         void (*set_render_target)(struct radeon_device *rdev, int format,
  747.                                   int w, int h, u64 gpu_addr);
  748.         void (*cp_set_surface_sync)(struct radeon_device *rdev,
  749.                                     u32 sync_type, u32 size,
  750.                                     u64 mc_addr);
  751.         void (*set_shaders)(struct radeon_device *rdev);
  752.         void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
  753.         void (*set_tex_resource)(struct radeon_device *rdev,
  754.                                  int format, int w, int h, int pitch,
  755.                                  u64 gpu_addr, u32 size);
  756.         void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
  757.                              int x2, int y2);
  758.         void (*draw_auto)(struct radeon_device *rdev);
  759.         void (*set_default_state)(struct radeon_device *rdev);
  760. };
  761.  
  762. struct r600_blit {
  763.         struct radeon_bo        *shader_obj;
  764.         struct r600_blit_cp_primitives primitives;
  765.         int max_dim;
  766.         int ring_size_common;
  767.         int ring_size_per_loop;
  768.         u64 shader_gpu_addr;
  769.         u32 vs_offset, ps_offset;
  770.         u32 state_offset;
  771.         u32 state_len;
  772. };
  773.  
  774. /*
  775.  * SI RLC stuff
  776.  */
  777. struct si_rlc {
  778.         /* for power gating */
  779.         struct radeon_bo        *save_restore_obj;
  780.         uint64_t                save_restore_gpu_addr;
  781.         /* for clear state */
  782.         struct radeon_bo        *clear_state_obj;
  783.         uint64_t                clear_state_gpu_addr;
  784. };
  785.  
  786. int radeon_ib_get(struct radeon_device *rdev, int ring,
  787.                   struct radeon_ib *ib, struct radeon_vm *vm,
  788.                   unsigned size);
  789. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
  790. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
  791.                        struct radeon_ib *const_ib);
  792. int radeon_ib_pool_init(struct radeon_device *rdev);
  793. void radeon_ib_pool_fini(struct radeon_device *rdev);
  794. int radeon_ib_ring_tests(struct radeon_device *rdev);
  795. /* Ring access between begin & end cannot sleep */
  796. bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
  797.                                       struct radeon_ring *ring);
  798. void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
  799. int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
  800. int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
  801. void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
  802. void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
  803. void radeon_ring_undo(struct radeon_ring *ring);
  804. void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
  805. int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  806. void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring);
  807. void radeon_ring_lockup_update(struct radeon_ring *ring);
  808. bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
  809. unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
  810.                             uint32_t **data);
  811. int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
  812.                         unsigned size, uint32_t *data);
  813. int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
  814.                      unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
  815.                      u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop);
  816. void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
  817.  
  818.  
  819. /*
  820.  * CS.
  821.  */
  822. struct radeon_cs_reloc {
  823. //      struct drm_gem_object           *gobj;
  824.         struct radeon_bo                *robj;
  825.         struct radeon_bo_list           lobj;
  826.     uint32_t                handle;
  827.     uint32_t                flags;
  828. };
  829.  
  830. struct radeon_cs_chunk {
  831.         uint32_t                chunk_id;
  832.         uint32_t                length_dw;
  833.         int kpage_idx[2];
  834.         uint32_t                *kpage[2];
  835.         uint32_t                *kdata;
  836.         void __user *user_ptr;
  837.         int last_copied_page;
  838.         int last_page_index;
  839. };
  840.  
  841. struct radeon_cs_parser {
  842.         struct device           *dev;
  843.         struct radeon_device    *rdev;
  844.         struct drm_file         *filp;
  845.         /* chunks */
  846.         unsigned                nchunks;
  847.         struct radeon_cs_chunk  *chunks;
  848.         uint64_t                *chunks_array;
  849.         /* IB */
  850.         unsigned                idx;
  851.         /* relocations */
  852.         unsigned                nrelocs;
  853.         struct radeon_cs_reloc  *relocs;
  854.         struct radeon_cs_reloc  **relocs_ptr;
  855.         struct list_head        validated;
  856.         /* indices of various chunks */
  857.         int                     chunk_ib_idx;
  858.         int                     chunk_relocs_idx;
  859.         int                     chunk_flags_idx;
  860.         int                     chunk_const_ib_idx;
  861.         struct radeon_ib        ib;
  862.         struct radeon_ib        const_ib;
  863.         void                    *track;
  864.         unsigned                family;
  865.         int parser_error;
  866.         u32                     cs_flags;
  867.         u32                     ring;
  868.         s32                     priority;
  869. };
  870.  
  871. extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
  872. extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
  873.  
  874. struct radeon_cs_packet {
  875.         unsigned        idx;
  876.         unsigned        type;
  877.         unsigned        reg;
  878.         unsigned        opcode;
  879.         int             count;
  880.         unsigned        one_reg_wr;
  881. };
  882.  
  883. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  884.                                       struct radeon_cs_packet *pkt,
  885.                                       unsigned idx, unsigned reg);
  886. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  887.                                       struct radeon_cs_packet *pkt);
  888.  
  889.  
  890. /*
  891.  * AGP
  892.  */
  893. int radeon_agp_init(struct radeon_device *rdev);
  894. void radeon_agp_resume(struct radeon_device *rdev);
  895. void radeon_agp_suspend(struct radeon_device *rdev);
  896. void radeon_agp_fini(struct radeon_device *rdev);
  897.  
  898.  
  899. /*
  900.  * Writeback
  901.  */
  902. struct radeon_wb {
  903.         struct radeon_bo        *wb_obj;
  904.         volatile uint32_t       *wb;
  905.         uint64_t                gpu_addr;
  906.         bool                    enabled;
  907.         bool                    use_event;
  908. };
  909.  
  910. #define RADEON_WB_SCRATCH_OFFSET 0
  911. #define RADEON_WB_RING0_NEXT_RPTR 256
  912. #define RADEON_WB_CP_RPTR_OFFSET 1024
  913. #define RADEON_WB_CP1_RPTR_OFFSET 1280
  914. #define RADEON_WB_CP2_RPTR_OFFSET 1536
  915. #define R600_WB_IH_WPTR_OFFSET   2048
  916. #define R600_WB_EVENT_OFFSET     3072
  917.  
  918. /**
  919.  * struct radeon_pm - power management datas
  920.  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
  921.  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  922.  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
  923.  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
  924.  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
  925.  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
  926.  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  927.  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
  928.  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
  929.  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
  930.  * @needed_bandwidth:   current bandwidth needs
  931.  *
  932.  * It keeps track of various data needed to take powermanagement decision.
  933.  * Bandwidth need is used to determine minimun clock of the GPU and memory.
  934.  * Equation between gpu/memory clock and available bandwidth is hw dependent
  935.  * (type of memory, bus size, efficiency, ...)
  936.  */
  937.  
  938. enum radeon_pm_method {
  939.         PM_METHOD_PROFILE,
  940.         PM_METHOD_DYNPM,
  941. };
  942.  
  943. enum radeon_dynpm_state {
  944.         DYNPM_STATE_DISABLED,
  945.         DYNPM_STATE_MINIMUM,
  946.         DYNPM_STATE_PAUSED,
  947.         DYNPM_STATE_ACTIVE,
  948.         DYNPM_STATE_SUSPENDED,
  949. };
  950. enum radeon_dynpm_action {
  951.         DYNPM_ACTION_NONE,
  952.         DYNPM_ACTION_MINIMUM,
  953.         DYNPM_ACTION_DOWNCLOCK,
  954.         DYNPM_ACTION_UPCLOCK,
  955.         DYNPM_ACTION_DEFAULT
  956. };
  957.  
  958. enum radeon_voltage_type {
  959.         VOLTAGE_NONE = 0,
  960.         VOLTAGE_GPIO,
  961.         VOLTAGE_VDDC,
  962.         VOLTAGE_SW
  963. };
  964.  
  965. enum radeon_pm_state_type {
  966.         POWER_STATE_TYPE_DEFAULT,
  967.         POWER_STATE_TYPE_POWERSAVE,
  968.         POWER_STATE_TYPE_BATTERY,
  969.         POWER_STATE_TYPE_BALANCED,
  970.         POWER_STATE_TYPE_PERFORMANCE,
  971. };
  972.  
  973. enum radeon_pm_profile_type {
  974.         PM_PROFILE_DEFAULT,
  975.         PM_PROFILE_AUTO,
  976.         PM_PROFILE_LOW,
  977.         PM_PROFILE_MID,
  978.         PM_PROFILE_HIGH,
  979. };
  980.  
  981. #define PM_PROFILE_DEFAULT_IDX 0
  982. #define PM_PROFILE_LOW_SH_IDX  1
  983. #define PM_PROFILE_MID_SH_IDX  2
  984. #define PM_PROFILE_HIGH_SH_IDX 3
  985. #define PM_PROFILE_LOW_MH_IDX  4
  986. #define PM_PROFILE_MID_MH_IDX  5
  987. #define PM_PROFILE_HIGH_MH_IDX 6
  988. #define PM_PROFILE_MAX         7
  989.  
  990. struct radeon_pm_profile {
  991.         int dpms_off_ps_idx;
  992.         int dpms_on_ps_idx;
  993.         int dpms_off_cm_idx;
  994.         int dpms_on_cm_idx;
  995. };
  996.  
  997. enum radeon_int_thermal_type {
  998.         THERMAL_TYPE_NONE,
  999.         THERMAL_TYPE_RV6XX,
  1000.         THERMAL_TYPE_RV770,
  1001.         THERMAL_TYPE_EVERGREEN,
  1002.         THERMAL_TYPE_SUMO,
  1003.         THERMAL_TYPE_NI,
  1004.         THERMAL_TYPE_SI,
  1005. };
  1006.  
  1007. struct radeon_voltage {
  1008.         enum radeon_voltage_type type;
  1009.         /* gpio voltage */
  1010.         struct radeon_gpio_rec gpio;
  1011.         u32 delay; /* delay in usec from voltage drop to sclk change */
  1012.         bool active_high; /* voltage drop is active when bit is high */
  1013.         /* VDDC voltage */
  1014.         u8 vddc_id; /* index into vddc voltage table */
  1015.         u8 vddci_id; /* index into vddci voltage table */
  1016.         bool vddci_enabled;
  1017.         /* r6xx+ sw */
  1018.         u16 voltage;
  1019.         /* evergreen+ vddci */
  1020.         u16 vddci;
  1021. };
  1022.  
  1023. /* clock mode flags */
  1024. #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
  1025.  
  1026. struct radeon_pm_clock_info {
  1027.         /* memory clock */
  1028.         u32 mclk;
  1029.         /* engine clock */
  1030.         u32 sclk;
  1031.         /* voltage info */
  1032.         struct radeon_voltage voltage;
  1033.         /* standardized clock flags */
  1034.         u32 flags;
  1035. };
  1036.  
  1037. /* state flags */
  1038. #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
  1039.  
  1040. struct radeon_power_state {
  1041.         enum radeon_pm_state_type type;
  1042.         struct radeon_pm_clock_info *clock_info;
  1043.         /* number of valid clock modes in this power state */
  1044.         int num_clock_modes;
  1045.         struct radeon_pm_clock_info *default_clock_mode;
  1046.         /* standardized state flags */
  1047.         u32 flags;
  1048.         u32 misc; /* vbios specific flags */
  1049.         u32 misc2; /* vbios specific flags */
  1050.         int pcie_lanes; /* pcie lanes */
  1051. };
  1052.  
  1053. /*
  1054.  * Some modes are overclocked by very low value, accept them
  1055.  */
  1056. #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
  1057.  
  1058. struct radeon_pm {
  1059.         struct mutex            mutex;
  1060.         /* write locked while reprogramming mclk */
  1061.         struct rw_semaphore     mclk_lock;
  1062.         u32                     active_crtcs;
  1063.         int                     active_crtc_count;
  1064.         int                     req_vblank;
  1065.         bool                    vblank_sync;
  1066.         fixed20_12              max_bandwidth;
  1067.         fixed20_12              igp_sideport_mclk;
  1068.         fixed20_12              igp_system_mclk;
  1069.         fixed20_12              igp_ht_link_clk;
  1070.         fixed20_12              igp_ht_link_width;
  1071.         fixed20_12              k8_bandwidth;
  1072.         fixed20_12              sideport_bandwidth;
  1073.         fixed20_12              ht_bandwidth;
  1074.         fixed20_12              core_bandwidth;
  1075.         fixed20_12              sclk;
  1076.         fixed20_12              mclk;
  1077.         fixed20_12              needed_bandwidth;
  1078.         struct radeon_power_state *power_state;
  1079.         /* number of valid power states */
  1080.         int                     num_power_states;
  1081.         int                     current_power_state_index;
  1082.         int                     current_clock_mode_index;
  1083.         int                     requested_power_state_index;
  1084.         int                     requested_clock_mode_index;
  1085.         int                     default_power_state_index;
  1086.         u32                     current_sclk;
  1087.         u32                     current_mclk;
  1088.         u16                     current_vddc;
  1089.         u16                     current_vddci;
  1090.         u32                     default_sclk;
  1091.         u32                     default_mclk;
  1092.         u16                     default_vddc;
  1093.         u16                     default_vddci;
  1094.         struct radeon_i2c_chan *i2c_bus;
  1095.         /* selected pm method */
  1096.         enum radeon_pm_method     pm_method;
  1097.         /* dynpm power management */
  1098. //   struct delayed_work dynpm_idle_work;
  1099.         enum radeon_dynpm_state dynpm_state;
  1100.         enum radeon_dynpm_action        dynpm_planned_action;
  1101.         unsigned long           dynpm_action_timeout;
  1102.         bool                    dynpm_can_upclock;
  1103.         bool                    dynpm_can_downclock;
  1104.         /* profile-based power management */
  1105.         enum radeon_pm_profile_type profile;
  1106.         int                     profile_index;
  1107.         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
  1108.         /* internal thermal controller on rv6xx+ */
  1109.         enum radeon_int_thermal_type int_thermal_type;
  1110.         struct device           *int_hwmon_dev;
  1111. };
  1112.  
  1113. int radeon_pm_get_type_index(struct radeon_device *rdev,
  1114.                              enum radeon_pm_state_type ps_type,
  1115.                              int instance);
  1116.  
  1117. struct r600_audio {
  1118.         int                     channels;
  1119.         int                     rate;
  1120.         int                     bits_per_sample;
  1121.         u8                      status_bits;
  1122.         u8                      category_code;
  1123. };
  1124. /*
  1125.  * ASIC specific functions.
  1126.  */
  1127. struct radeon_asic {
  1128.         int (*init)(struct radeon_device *rdev);
  1129.         void (*fini)(struct radeon_device *rdev);
  1130.         int (*resume)(struct radeon_device *rdev);
  1131.         int (*suspend)(struct radeon_device *rdev);
  1132.         void (*vga_set_state)(struct radeon_device *rdev, bool state);
  1133.         int (*asic_reset)(struct radeon_device *rdev);
  1134.         /* ioctl hw specific callback. Some hw might want to perform special
  1135.          * operation on specific ioctl. For instance on wait idle some hw
  1136.          * might want to perform and HDP flush through MMIO as it seems that
  1137.          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
  1138.          * through ring.
  1139.          */
  1140.         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
  1141.         /* check if 3D engine is idle */
  1142.         bool (*gui_idle)(struct radeon_device *rdev);
  1143.         /* wait for mc_idle */
  1144.         int (*mc_wait_for_idle)(struct radeon_device *rdev);
  1145.         /* gart */
  1146.         struct {
  1147.                 void (*tlb_flush)(struct radeon_device *rdev);
  1148.                 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  1149.         } gart;
  1150.         struct {
  1151.                 int (*init)(struct radeon_device *rdev);
  1152.                 void (*fini)(struct radeon_device *rdev);
  1153.  
  1154.                 u32 pt_ring_index;
  1155.                 void (*set_page)(struct radeon_device *rdev, uint64_t pe,
  1156.                                  uint64_t addr, unsigned count,
  1157.                                  uint32_t incr, uint32_t flags);
  1158.         } vm;
  1159.         /* ring specific callbacks */
  1160.         struct {
  1161.                 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  1162.                 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
  1163.                 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
  1164.                 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
  1165.                                        struct radeon_semaphore *semaphore, bool emit_wait);
  1166.                 int (*cs_parse)(struct radeon_cs_parser *p);
  1167.                 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
  1168.                 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
  1169.                 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
  1170.                 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
  1171.                 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
  1172.         } ring[RADEON_NUM_RINGS];
  1173.         /* irqs */
  1174.         struct {
  1175.                 int (*set)(struct radeon_device *rdev);
  1176.                 int (*process)(struct radeon_device *rdev);
  1177.         } irq;
  1178.         /* displays */
  1179.         struct {
  1180.                 /* display watermarks */
  1181.                 void (*bandwidth_update)(struct radeon_device *rdev);
  1182.                 /* get frame count */
  1183.         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  1184.                 /* wait for vblank */
  1185.                 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
  1186.                 /* set backlight level */
  1187.                 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
  1188.                 /* get backlight level */
  1189.                 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
  1190.         } display;
  1191.         /* copy functions for bo handling */
  1192.         struct {
  1193.                 int (*blit)(struct radeon_device *rdev,
  1194.                          uint64_t src_offset,
  1195.                          uint64_t dst_offset,
  1196.                          unsigned num_gpu_pages,
  1197.                             struct radeon_fence **fence);
  1198.                 u32 blit_ring_index;
  1199.                 int (*dma)(struct radeon_device *rdev,
  1200.                         uint64_t src_offset,
  1201.                         uint64_t dst_offset,
  1202.                         unsigned num_gpu_pages,
  1203.                            struct radeon_fence **fence);
  1204.                 u32 dma_ring_index;
  1205.                 /* method used for bo copy */
  1206.         int (*copy)(struct radeon_device *rdev,
  1207.                     uint64_t src_offset,
  1208.                     uint64_t dst_offset,
  1209.                     unsigned num_gpu_pages,
  1210.                             struct radeon_fence **fence);
  1211.                 /* ring used for bo copies */
  1212.                 u32 copy_ring_index;
  1213.         } copy;
  1214.         /* surfaces */
  1215.         struct {
  1216.                 int (*set_reg)(struct radeon_device *rdev, int reg,
  1217.                                        uint32_t tiling_flags, uint32_t pitch,
  1218.                                        uint32_t offset, uint32_t obj_size);
  1219.                 void (*clear_reg)(struct radeon_device *rdev, int reg);
  1220.         } surface;
  1221.         /* hotplug detect */
  1222.         struct {
  1223.                 void (*init)(struct radeon_device *rdev);
  1224.                 void (*fini)(struct radeon_device *rdev);
  1225.                 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  1226.                 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  1227.         } hpd;
  1228.         /* power management */
  1229.         struct {
  1230.                 void (*misc)(struct radeon_device *rdev);
  1231.                 void (*prepare)(struct radeon_device *rdev);
  1232.                 void (*finish)(struct radeon_device *rdev);
  1233.                 void (*init_profile)(struct radeon_device *rdev);
  1234.                 void (*get_dynpm_state)(struct radeon_device *rdev);
  1235.         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
  1236.         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  1237.         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
  1238.         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  1239.         int (*get_pcie_lanes)(struct radeon_device *rdev);
  1240.         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  1241.         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  1242.         } pm;
  1243.         /* pageflipping */
  1244.         struct {
  1245.         void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
  1246.         u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
  1247.         void (*post_page_flip)(struct radeon_device *rdev, int crtc);
  1248.         } pflip;
  1249. };
  1250.  
  1251. /*
  1252.  * Asic structures
  1253.  */
  1254. struct r100_asic {
  1255.         const unsigned  *reg_safe_bm;
  1256.         unsigned        reg_safe_bm_size;
  1257.         u32             hdp_cntl;
  1258. };
  1259.  
  1260. struct r300_asic {
  1261.         const unsigned  *reg_safe_bm;
  1262.         unsigned        reg_safe_bm_size;
  1263.         u32             resync_scratch;
  1264.         u32             hdp_cntl;
  1265. };
  1266.  
  1267. struct r600_asic {
  1268.         unsigned max_pipes;
  1269.         unsigned max_tile_pipes;
  1270.         unsigned max_simds;
  1271.         unsigned max_backends;
  1272.         unsigned max_gprs;
  1273.         unsigned max_threads;
  1274.         unsigned max_stack_entries;
  1275.         unsigned max_hw_contexts;
  1276.         unsigned max_gs_threads;
  1277.         unsigned sx_max_export_size;
  1278.         unsigned sx_max_export_pos_size;
  1279.         unsigned sx_max_export_smx_size;
  1280.         unsigned sq_num_cf_insts;
  1281.         unsigned tiling_nbanks;
  1282.         unsigned tiling_npipes;
  1283.         unsigned tiling_group_size;
  1284.         unsigned                tile_config;
  1285.         unsigned                backend_map;
  1286. };
  1287.  
  1288. struct rv770_asic {
  1289.         unsigned max_pipes;
  1290.         unsigned max_tile_pipes;
  1291.         unsigned max_simds;
  1292.         unsigned max_backends;
  1293.         unsigned max_gprs;
  1294.         unsigned max_threads;
  1295.         unsigned max_stack_entries;
  1296.         unsigned max_hw_contexts;
  1297.         unsigned max_gs_threads;
  1298.         unsigned sx_max_export_size;
  1299.         unsigned sx_max_export_pos_size;
  1300.         unsigned sx_max_export_smx_size;
  1301.         unsigned sq_num_cf_insts;
  1302.         unsigned sx_num_of_sets;
  1303.         unsigned sc_prim_fifo_size;
  1304.         unsigned sc_hiz_tile_fifo_size;
  1305.         unsigned sc_earlyz_tile_fifo_fize;
  1306.         unsigned tiling_nbanks;
  1307.         unsigned tiling_npipes;
  1308.         unsigned tiling_group_size;
  1309.         unsigned                tile_config;
  1310.         unsigned                backend_map;
  1311. };
  1312.  
  1313. struct evergreen_asic {
  1314.         unsigned num_ses;
  1315.         unsigned max_pipes;
  1316.         unsigned max_tile_pipes;
  1317.         unsigned max_simds;
  1318.         unsigned max_backends;
  1319.         unsigned max_gprs;
  1320.         unsigned max_threads;
  1321.         unsigned max_stack_entries;
  1322.         unsigned max_hw_contexts;
  1323.         unsigned max_gs_threads;
  1324.         unsigned sx_max_export_size;
  1325.         unsigned sx_max_export_pos_size;
  1326.         unsigned sx_max_export_smx_size;
  1327.         unsigned sq_num_cf_insts;
  1328.         unsigned sx_num_of_sets;
  1329.         unsigned sc_prim_fifo_size;
  1330.         unsigned sc_hiz_tile_fifo_size;
  1331.         unsigned sc_earlyz_tile_fifo_size;
  1332.         unsigned tiling_nbanks;
  1333.         unsigned tiling_npipes;
  1334.         unsigned tiling_group_size;
  1335.         unsigned tile_config;
  1336.         unsigned backend_map;
  1337. };
  1338.  
  1339. struct cayman_asic {
  1340.         unsigned max_shader_engines;
  1341.         unsigned max_pipes_per_simd;
  1342.         unsigned max_tile_pipes;
  1343.         unsigned max_simds_per_se;
  1344.         unsigned max_backends_per_se;
  1345.         unsigned max_texture_channel_caches;
  1346.         unsigned max_gprs;
  1347.         unsigned max_threads;
  1348.         unsigned max_gs_threads;
  1349.         unsigned max_stack_entries;
  1350.         unsigned sx_num_of_sets;
  1351.         unsigned sx_max_export_size;
  1352.         unsigned sx_max_export_pos_size;
  1353.         unsigned sx_max_export_smx_size;
  1354.         unsigned max_hw_contexts;
  1355.         unsigned sq_num_cf_insts;
  1356.         unsigned sc_prim_fifo_size;
  1357.         unsigned sc_hiz_tile_fifo_size;
  1358.         unsigned sc_earlyz_tile_fifo_size;
  1359.  
  1360.         unsigned num_shader_engines;
  1361.         unsigned num_shader_pipes_per_simd;
  1362.         unsigned num_tile_pipes;
  1363.         unsigned num_simds_per_se;
  1364.         unsigned num_backends_per_se;
  1365.         unsigned backend_disable_mask_per_asic;
  1366.         unsigned backend_map;
  1367.         unsigned num_texture_channel_caches;
  1368.         unsigned mem_max_burst_length_bytes;
  1369.         unsigned mem_row_size_in_kb;
  1370.         unsigned shader_engine_tile_size;
  1371.         unsigned num_gpus;
  1372.         unsigned multi_gpu_tile_size;
  1373.  
  1374.         unsigned tile_config;
  1375. };
  1376.  
  1377. struct si_asic {
  1378.         unsigned max_shader_engines;
  1379.         unsigned max_tile_pipes;
  1380.         unsigned max_cu_per_sh;
  1381.         unsigned max_sh_per_se;
  1382.         unsigned max_backends_per_se;
  1383.         unsigned max_texture_channel_caches;
  1384.         unsigned max_gprs;
  1385.         unsigned max_gs_threads;
  1386.         unsigned max_hw_contexts;
  1387.         unsigned sc_prim_fifo_size_frontend;
  1388.         unsigned sc_prim_fifo_size_backend;
  1389.         unsigned sc_hiz_tile_fifo_size;
  1390.         unsigned sc_earlyz_tile_fifo_size;
  1391.  
  1392.         unsigned num_tile_pipes;
  1393.         unsigned num_backends_per_se;
  1394.         unsigned backend_disable_mask_per_asic;
  1395.         unsigned backend_map;
  1396.         unsigned num_texture_channel_caches;
  1397.         unsigned mem_max_burst_length_bytes;
  1398.         unsigned mem_row_size_in_kb;
  1399.         unsigned shader_engine_tile_size;
  1400.         unsigned num_gpus;
  1401.         unsigned multi_gpu_tile_size;
  1402.  
  1403.         unsigned tile_config;
  1404. };
  1405.  
  1406. union radeon_asic_config {
  1407.         struct r300_asic        r300;
  1408.         struct r100_asic        r100;
  1409.         struct r600_asic        r600;
  1410.         struct rv770_asic       rv770;
  1411.         struct evergreen_asic   evergreen;
  1412.         struct cayman_asic      cayman;
  1413.         struct si_asic          si;
  1414. };
  1415.  
  1416. /*
  1417.  * asic initizalization from radeon_asic.c
  1418.  */
  1419. void radeon_agp_disable(struct radeon_device *rdev);
  1420. int radeon_asic_init(struct radeon_device *rdev);
  1421.  
  1422.  
  1423.  
  1424. /* VRAM scratch page for HDP bug, default vram page */
  1425. struct r600_vram_scratch {
  1426.         struct radeon_bo                *robj;
  1427.         volatile uint32_t               *ptr;
  1428.         u64                             gpu_addr;
  1429. };
  1430.  
  1431.  
  1432. /*
  1433.  * Core structure, functions and helpers.
  1434.  */
  1435. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  1436. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  1437.  
  1438. struct radeon_device {
  1439.     struct device              *dev;
  1440.     struct drm_device          *ddev;
  1441.     struct pci_dev             *pdev;
  1442.         struct rw_semaphore             exclusive_lock;
  1443.     /* ASIC */
  1444.     union radeon_asic_config    config;
  1445.     enum radeon_family          family;
  1446.     unsigned long               flags;
  1447.     int                         usec_timeout;
  1448.     enum radeon_pll_errata      pll_errata;
  1449.     int                         num_gb_pipes;
  1450.         int                                         num_z_pipes;
  1451.     int                         disp_priority;
  1452.     /* BIOS */
  1453.     uint8_t                     *bios;
  1454.     bool                        is_atom_bios;
  1455.     uint16_t                    bios_header_start;
  1456.         struct radeon_bo                    *stollen_vga_memory;
  1457.     /* Register mmio */
  1458.         resource_size_t                 rmmio_base;
  1459.         resource_size_t                 rmmio_size;
  1460.         void __iomem                    *rmmio;
  1461.     radeon_rreg_t               mc_rreg;
  1462.     radeon_wreg_t               mc_wreg;
  1463.     radeon_rreg_t               pll_rreg;
  1464.     radeon_wreg_t               pll_wreg;
  1465.         uint32_t                        pcie_reg_mask;
  1466.     radeon_rreg_t               pciep_rreg;
  1467.     radeon_wreg_t               pciep_wreg;
  1468.         /* io port */
  1469.         void __iomem                    *rio_mem;
  1470.         resource_size_t                 rio_mem_size;
  1471.     struct radeon_clock         clock;
  1472.     struct radeon_mc            mc;
  1473.     struct radeon_gart          gart;
  1474.         struct radeon_mode_info         mode_info;
  1475.     struct radeon_scratch       scratch;
  1476.     struct radeon_mman          mman;
  1477.         struct radeon_fence_driver      fence_drv[RADEON_NUM_RINGS];
  1478.         wait_queue_head_t               fence_queue;
  1479.         struct mutex                    ring_lock;
  1480.         struct radeon_ring              ring[RADEON_NUM_RINGS];
  1481.         bool                            ib_pool_ready;
  1482.         struct radeon_sa_manager        ring_tmp_bo;
  1483.     struct radeon_irq       irq;
  1484.     struct radeon_asic         *asic;
  1485.     struct radeon_gem       gem;
  1486.         struct radeon_pm                pm;
  1487.         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  1488.     struct radeon_wb        wb;
  1489.         struct radeon_dummy_page        dummy_page;
  1490.     bool                shutdown;
  1491.     bool                suspend;
  1492.         bool                            need_dma32;
  1493.         bool                            accel_working;
  1494.         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  1495.         const struct firmware *me_fw;   /* all family ME firmware */
  1496.         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
  1497.         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
  1498.         const struct firmware *mc_fw;   /* NI MC firmware */
  1499.         const struct firmware *ce_fw;   /* SI CE firmware */
  1500.         struct r600_blit r600_blit;
  1501.         struct r600_vram_scratch vram_scratch;
  1502.         int msi_enabled; /* msi enabled */
  1503.         struct r600_ih ih; /* r6/700 interrupt ring */
  1504.         struct si_rlc rlc;
  1505. //      struct work_struct hotplug_work;
  1506. //      struct work_struct audio_work;
  1507.         int num_crtc; /* number of crtcs */
  1508.         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
  1509.         bool                    audio_enabled;
  1510. //   struct r600_audio audio_status; /* audio stuff */
  1511. //   struct notifier_block acpi_nb;
  1512.         /* only one userspace can use Hyperz features or CMASK at a time */
  1513. //      struct drm_file *hyperz_filp;
  1514. //      struct drm_file *cmask_filp;
  1515.         /* i2c buses */
  1516.         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
  1517.         /* debugfs */
  1518. //      struct radeon_debugfs   debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
  1519.         unsigned                debugfs_count;
  1520.         /* virtual memory */
  1521.         struct radeon_vm_manager        vm_manager;
  1522.         struct mutex                    gpu_clock_mutex;
  1523.         /* ACPI interface */
  1524. //      struct radeon_atif              atif;
  1525. //      struct radeon_atcs              atcs;
  1526. };
  1527.  
  1528. int radeon_device_init(struct radeon_device *rdev,
  1529.                        struct drm_device *ddev,
  1530.                        struct pci_dev *pdev,
  1531.                        uint32_t flags);
  1532. void radeon_device_fini(struct radeon_device *rdev);
  1533. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  1534.  
  1535. uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
  1536. void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  1537. u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
  1538. void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  1539.  
  1540. /*
  1541.  * Cast helper
  1542.  */
  1543. #define to_radeon_fence(p) ((struct radeon_fence *)(p))
  1544.  
  1545. /*
  1546.  * Registers read & write functions.
  1547.  */
  1548. #define RREG8(reg) readb((rdev->rmmio) + (reg))
  1549. #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
  1550. #define RREG16(reg) readw((rdev->rmmio) + (reg))
  1551. #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
  1552. #define RREG32(reg) r100_mm_rreg(rdev, (reg))
  1553. #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
  1554. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
  1555. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  1556. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  1557. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  1558. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  1559. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  1560. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  1561. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  1562. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  1563. #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
  1564. #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
  1565. #define WREG32_P(reg, val, mask)                                \
  1566.         do {                                                    \
  1567.                 uint32_t tmp_ = RREG32(reg);                    \
  1568.                 tmp_ &= (mask);                                 \
  1569.                 tmp_ |= ((val) & ~(mask));                      \
  1570.                 WREG32(reg, tmp_);                              \
  1571.         } while (0)
  1572. #define WREG32_PLL_P(reg, val, mask)                            \
  1573.         do {                                                    \
  1574.                 uint32_t tmp_ = RREG32_PLL(reg);                \
  1575.                 tmp_ &= (mask);                                 \
  1576.                 tmp_ |= ((val) & ~(mask));                      \
  1577.                 WREG32_PLL(reg, tmp_);                          \
  1578.         } while (0)
  1579. #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
  1580. #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
  1581.  
  1582. /*
  1583.  * Indirect registers accessor
  1584.  */
  1585. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  1586. {
  1587.         uint32_t r;
  1588.  
  1589.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  1590.         r = RREG32(RADEON_PCIE_DATA);
  1591.         return r;
  1592. }
  1593.  
  1594. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  1595. {
  1596.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  1597.         WREG32(RADEON_PCIE_DATA, (v));
  1598. }
  1599.  
  1600. void r100_pll_errata_after_index(struct radeon_device *rdev);
  1601.  
  1602.  
  1603. /*
  1604.  * ASICs helpers.
  1605.  */
  1606. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  1607.                             (rdev->pdev->device == 0x5969))
  1608. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  1609.         (rdev->family == CHIP_RV200) || \
  1610.         (rdev->family == CHIP_RS100) || \
  1611.         (rdev->family == CHIP_RS200) || \
  1612.         (rdev->family == CHIP_RV250) || \
  1613.         (rdev->family == CHIP_RV280) || \
  1614.         (rdev->family == CHIP_RS300))
  1615. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
  1616.         (rdev->family == CHIP_RV350) ||         \
  1617.         (rdev->family == CHIP_R350)  ||         \
  1618.         (rdev->family == CHIP_RV380) ||         \
  1619.         (rdev->family == CHIP_R420)  ||         \
  1620.         (rdev->family == CHIP_R423)  ||         \
  1621.         (rdev->family == CHIP_RV410) ||         \
  1622.         (rdev->family == CHIP_RS400) ||         \
  1623.         (rdev->family == CHIP_RS480))
  1624. #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
  1625.                 (rdev->ddev->pdev->device == 0x9443) || \
  1626.                 (rdev->ddev->pdev->device == 0x944B) || \
  1627.                 (rdev->ddev->pdev->device == 0x9506) || \
  1628.                 (rdev->ddev->pdev->device == 0x9509) || \
  1629.                 (rdev->ddev->pdev->device == 0x950F) || \
  1630.                 (rdev->ddev->pdev->device == 0x689C) || \
  1631.                 (rdev->ddev->pdev->device == 0x689D))
  1632. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  1633. #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
  1634.                             (rdev->family == CHIP_RS690)  ||    \
  1635.                             (rdev->family == CHIP_RS740)  ||    \
  1636.                             (rdev->family >= CHIP_R600))
  1637. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  1638. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  1639. #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
  1640. #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
  1641.                              (rdev->flags & RADEON_IS_IGP))
  1642. #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
  1643. #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
  1644. #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
  1645.                              (rdev->flags & RADEON_IS_IGP))
  1646.  
  1647. /*
  1648.  * BIOS helpers.
  1649.  */
  1650. #define RBIOS8(i) (rdev->bios[i])
  1651. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  1652. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  1653.  
  1654. int radeon_combios_init(struct radeon_device *rdev);
  1655. void radeon_combios_fini(struct radeon_device *rdev);
  1656. int radeon_atombios_init(struct radeon_device *rdev);
  1657. void radeon_atombios_fini(struct radeon_device *rdev);
  1658.  
  1659.  
  1660. /*
  1661.  * RING helpers.
  1662.  */
  1663. #if DRM_DEBUG_CODE == 0
  1664. static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
  1665. {
  1666.         ring->ring[ring->wptr++] = v;
  1667.         ring->wptr &= ring->ptr_mask;
  1668.         ring->count_dw--;
  1669.         ring->ring_free_dw--;
  1670. }
  1671. #else
  1672. /* With debugging this is just too big to inline */
  1673. void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
  1674. #endif
  1675.  
  1676. /*
  1677.  * ASICs macro.
  1678.  */
  1679. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  1680. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  1681. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  1682. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  1683. #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p))
  1684. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  1685. #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
  1686. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
  1687. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
  1688. #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
  1689. #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
  1690. #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags)))
  1691. #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
  1692. #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
  1693. #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
  1694. #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
  1695. #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib))
  1696. #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp))
  1697. #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm))
  1698. #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
  1699. #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
  1700. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
  1701. #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
  1702. #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
  1703. #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
  1704. #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
  1705. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
  1706. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
  1707. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
  1708. #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
  1709. #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
  1710. #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
  1711. #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
  1712. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
  1713. #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
  1714. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
  1715. #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
  1716. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
  1717. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
  1718. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
  1719. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
  1720. #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
  1721. #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
  1722. #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
  1723. #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
  1724. #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
  1725. #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
  1726. #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
  1727. #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
  1728. #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
  1729. #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
  1730. #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
  1731. #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
  1732. #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
  1733. #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
  1734. #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
  1735. #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
  1736.  
  1737. /* Common functions */
  1738. /* AGP */
  1739. extern int radeon_gpu_reset(struct radeon_device *rdev);
  1740. extern void radeon_agp_disable(struct radeon_device *rdev);
  1741. extern int radeon_modeset_init(struct radeon_device *rdev);
  1742. extern void radeon_modeset_fini(struct radeon_device *rdev);
  1743. extern bool radeon_card_posted(struct radeon_device *rdev);
  1744. extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
  1745. extern void radeon_update_display_priority(struct radeon_device *rdev);
  1746. extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
  1747. extern void radeon_scratch_init(struct radeon_device *rdev);
  1748. extern void radeon_wb_fini(struct radeon_device *rdev);
  1749. extern int radeon_wb_init(struct radeon_device *rdev);
  1750. extern void radeon_wb_disable(struct radeon_device *rdev);
  1751. extern void radeon_surface_init(struct radeon_device *rdev);
  1752. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  1753. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  1754. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  1755. extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
  1756. extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
  1757. extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
  1758. extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
  1759. extern int radeon_resume_kms(struct drm_device *dev);
  1760. extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
  1761. extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
  1762.  
  1763. /*
  1764.  * vm
  1765.  */
  1766. int radeon_vm_manager_init(struct radeon_device *rdev);
  1767. void radeon_vm_manager_fini(struct radeon_device *rdev);
  1768. void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
  1769. void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
  1770. int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm);
  1771. void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm);
  1772. struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
  1773.                                        struct radeon_vm *vm, int ring);
  1774. void radeon_vm_fence(struct radeon_device *rdev,
  1775.                      struct radeon_vm *vm,
  1776.                      struct radeon_fence *fence);
  1777. uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
  1778. int radeon_vm_bo_update_pte(struct radeon_device *rdev,
  1779.                             struct radeon_vm *vm,
  1780.                             struct radeon_bo *bo,
  1781.                             struct ttm_mem_reg *mem);
  1782. void radeon_vm_bo_invalidate(struct radeon_device *rdev,
  1783.                              struct radeon_bo *bo);
  1784. struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
  1785.                                        struct radeon_bo *bo);
  1786. struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
  1787.                                       struct radeon_vm *vm,
  1788.                                       struct radeon_bo *bo);
  1789. int radeon_vm_bo_set_addr(struct radeon_device *rdev,
  1790.                           struct radeon_bo_va *bo_va,
  1791.                           uint64_t offset,
  1792.                           uint32_t flags);
  1793. int radeon_vm_bo_rmv(struct radeon_device *rdev,
  1794.                      struct radeon_bo_va *bo_va);
  1795.  
  1796. /* audio */
  1797. void r600_audio_update_hdmi(struct work_struct *work);
  1798.  
  1799. /*
  1800.  * R600 vram scratch functions
  1801.  */
  1802. int r600_vram_scratch_init(struct radeon_device *rdev);
  1803. void r600_vram_scratch_fini(struct radeon_device *rdev);
  1804.  
  1805. /*
  1806.  * r600 cs checking helper
  1807.  */
  1808. unsigned r600_mip_minify(unsigned size, unsigned level);
  1809. bool r600_fmt_is_valid_color(u32 format);
  1810. bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
  1811. int r600_fmt_get_blocksize(u32 format);
  1812. int r600_fmt_get_nblocksx(u32 format, u32 w);
  1813. int r600_fmt_get_nblocksy(u32 format, u32 h);
  1814.  
  1815. /*
  1816.  * r600 functions used by radeon_encoder.c
  1817.  */
  1818. struct radeon_hdmi_acr {
  1819.         u32 clock;
  1820.  
  1821.         int n_32khz;
  1822.         int cts_32khz;
  1823.  
  1824.         int n_44_1khz;
  1825.         int cts_44_1khz;
  1826.  
  1827.         int n_48khz;
  1828.         int cts_48khz;
  1829.  
  1830. };
  1831.  
  1832. extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
  1833.  
  1834. extern void r600_hdmi_enable(struct drm_encoder *encoder);
  1835. extern void r600_hdmi_disable(struct drm_encoder *encoder);
  1836. extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  1837. extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
  1838.                                      u32 tiling_pipe_num,
  1839.                                      u32 max_rb_num,
  1840.                                      u32 total_max_rb_num,
  1841.                                      u32 enabled_rb_mask);
  1842.  
  1843. /*
  1844.  * evergreen functions used by radeon_encoder.c
  1845.  */
  1846.  
  1847. extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  1848.  
  1849. extern int ni_init_microcode(struct radeon_device *rdev);
  1850. extern int ni_mc_load_microcode(struct radeon_device *rdev);
  1851.  
  1852. /* radeon_acpi.c */
  1853. #if defined(CONFIG_ACPI)
  1854. extern int radeon_acpi_init(struct radeon_device *rdev);
  1855. extern void radeon_acpi_fini(struct radeon_device *rdev);
  1856. #else
  1857. static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
  1858. static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
  1859. #endif
  1860.  
  1861. #include "radeon_object.h"
  1862.  
  1863. #define DRM_UDELAY(d)           udelay(d)
  1864.  
  1865. resource_size_t
  1866. drm_get_resource_start(struct drm_device *dev, unsigned int resource);
  1867. resource_size_t
  1868. drm_get_resource_len(struct drm_device *dev, unsigned int resource);
  1869.  
  1870. bool set_mode(struct drm_device *dev, struct drm_connector *connector,
  1871.               videomode_t *mode, bool strict);
  1872.  
  1873.  
  1874.  
  1875. #endif
  1876.