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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30.  
  31. /* TODO: Here are things that needs to be done :
  32.  *      - surface allocator & initializer : (bit like scratch reg) should
  33.  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34.  *        related to surface
  35.  *      - WB : write back stuff (do it bit like scratch reg things)
  36.  *      - Vblank : look at Jesse's rework and what we should do
  37.  *      - r600/r700: gart & cp
  38.  *      - cs : clean cs ioctl use bitmap & things like that.
  39.  *      - power management stuff
  40.  *      - Barrier in gart code
  41.  *      - Unmappabled vram ?
  42.  *      - TESTING, TESTING, TESTING
  43.  */
  44.  
  45. /* Initialization path:
  46.  *  We expect that acceleration initialization might fail for various
  47.  *  reasons even thought we work hard to make it works on most
  48.  *  configurations. In order to still have a working userspace in such
  49.  *  situation the init path must succeed up to the memory controller
  50.  *  initialization point. Failure before this point are considered as
  51.  *  fatal error. Here is the init callchain :
  52.  *      radeon_device_init  perform common structure, mutex initialization
  53.  *      asic_init           setup the GPU memory layout and perform all
  54.  *                          one time initialization (failure in this
  55.  *                          function are considered fatal)
  56.  *      asic_startup        setup the GPU acceleration, in order to
  57.  *                          follow guideline the first thing this
  58.  *                          function should do is setting the GPU
  59.  *                          memory controller (only MC setup failure
  60.  *                          are considered as fatal)
  61.  */
  62.  
  63. #include <ddk.h>
  64. #include <asm/atomic.h>
  65.  
  66. #include <linux/list.h>
  67. #include <linux/kref.h>
  68.  
  69. #include <ttm/ttm_bo_api.h>
  70. #include <ttm/ttm_bo_driver.h>
  71. #include <ttm/ttm_placement.h>
  72. #include <ttm/ttm_module.h>
  73.  
  74.  
  75. #include <pci.h>
  76.  
  77. #include <errno-base.h>
  78. #include "drm_edid.h"
  79.  
  80. #include "radeon_family.h"
  81. #include "radeon_mode.h"
  82. #include "radeon_reg.h"
  83.  
  84. #include <syscall.h>
  85.  
  86. /*
  87.  * Modules parameters.
  88.  */
  89. extern int radeon_no_wb;
  90. extern int radeon_modeset;
  91. extern int radeon_dynclks;
  92. extern int radeon_r4xx_atom;
  93. extern int radeon_agpmode;
  94. extern int radeon_vram_limit;
  95. extern int radeon_gart_size;
  96. extern int radeon_benchmarking;
  97. extern int radeon_testing;
  98. extern int radeon_connector_table;
  99. extern int radeon_tv;
  100. extern int radeon_new_pll;
  101. extern int radeon_dynpm;
  102. extern int radeon_audio;
  103.  
  104. typedef struct pm_message {
  105.     int event;
  106. } pm_message_t;
  107.  
  108. typedef struct
  109. {
  110.   int width;
  111.   int height;
  112.   int bpp;
  113.   int freq;
  114. }videomode_t;
  115.  
  116. static inline uint8_t __raw_readb(const volatile void __iomem *addr)
  117. {
  118.     return *(const volatile uint8_t __force *) addr;
  119. }
  120.  
  121. static inline uint16_t __raw_readw(const volatile void __iomem *addr)
  122. {
  123.     return *(const volatile uint16_t __force *) addr;
  124. }
  125.  
  126. static inline uint32_t __raw_readl(const volatile void __iomem *addr)
  127. {
  128.     return *(const volatile uint32_t __force *) addr;
  129. }
  130.  
  131. #define readb __raw_readb
  132. #define readw __raw_readw
  133. #define readl __raw_readl
  134.  
  135.  
  136.  
  137. static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
  138. {
  139.     *(volatile uint8_t __force *) addr = b;
  140. }
  141.  
  142. static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
  143. {
  144.     *(volatile uint16_t __force *) addr = b;
  145. }
  146.  
  147. static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
  148. {
  149.     *(volatile uint32_t __force *) addr = b;
  150. }
  151.  
  152. static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
  153. {
  154.         *(volatile __u64 *)addr = b;
  155. }
  156.  
  157. #define writeb __raw_writeb
  158. #define writew __raw_writew
  159. #define writel __raw_writel
  160. #define writeq __raw_writeq
  161.  
  162.  
  163. /*
  164.  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  165.  * symbol;
  166.  */
  167. #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  168. /* RADEON_IB_POOL_SIZE must be a power of 2 */
  169. #define RADEON_IB_POOL_SIZE             16
  170. #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  171. #define RADEONFB_CONN_LIMIT             4
  172. #define RADEON_BIOS_NUM_SCRATCH         8
  173.  
  174. /*
  175.  * Errata workarounds.
  176.  */
  177. enum radeon_pll_errata {
  178.     CHIP_ERRATA_R300_CG             = 0x00000001,
  179.     CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  180.     CHIP_ERRATA_PLL_DELAY           = 0x00000004
  181. };
  182.  
  183.  
  184. struct radeon_device;
  185.  
  186.  
  187. /*
  188.  * BIOS.
  189.  */
  190. #define ATRM_BIOS_PAGE 4096
  191.  
  192. #if defined(CONFIG_VGA_SWITCHEROO)
  193. bool radeon_atrm_supported(struct pci_dev *pdev);
  194. int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
  195. #else
  196. static inline bool radeon_atrm_supported(struct pci_dev *pdev)
  197. {
  198.         return false;
  199. }
  200.  
  201. static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
  202.         return -EINVAL;
  203. }
  204. #endif
  205. bool radeon_get_bios(struct radeon_device *rdev);
  206.  
  207.  
  208. /*
  209.  * Dummy page
  210.  */
  211. struct radeon_dummy_page {
  212.         struct page     *page;
  213.         dma_addr_t      addr;
  214. };
  215. int radeon_dummy_page_init(struct radeon_device *rdev);
  216. void radeon_dummy_page_fini(struct radeon_device *rdev);
  217.  
  218.  
  219. /*
  220.  * Clocks
  221.  */
  222. struct radeon_clock {
  223.         struct radeon_pll p1pll;
  224.         struct radeon_pll p2pll;
  225.         struct radeon_pll dcpll;
  226.         struct radeon_pll spll;
  227.         struct radeon_pll mpll;
  228.         /* 10 Khz units */
  229.         uint32_t default_mclk;
  230.         uint32_t default_sclk;
  231.         uint32_t default_dispclk;
  232.         uint32_t dp_extclk;
  233. };
  234.  
  235. /*
  236.  * Power management
  237.  */
  238. int radeon_pm_init(struct radeon_device *rdev);
  239. void radeon_pm_compute_clocks(struct radeon_device *rdev);
  240. void radeon_combios_get_power_modes(struct radeon_device *rdev);
  241. void radeon_atombios_get_power_modes(struct radeon_device *rdev);
  242.  
  243. /*
  244.  * Fences.
  245.  */
  246. struct radeon_fence_driver {
  247.         uint32_t                        scratch_reg;
  248.         atomic_t                        seq;
  249.         uint32_t                        last_seq;
  250.         unsigned long                   count_timeout;
  251. //      wait_queue_head_t               queue;
  252.         rwlock_t                        lock;
  253.         struct list_head                created;
  254.         struct list_head                emited;
  255.         struct list_head                signaled;
  256.         bool                            initialized;
  257. };
  258.  
  259. struct radeon_fence {
  260.         struct radeon_device            *rdev;
  261.         struct kref                     kref;
  262.         struct list_head                list;
  263.         /* protected by radeon_fence.lock */
  264.         uint32_t                        seq;
  265.         unsigned long                   timeout;
  266.         bool                            emited;
  267.         bool                            signaled;
  268. };
  269.  
  270. int radeon_fence_driver_init(struct radeon_device *rdev);
  271. void radeon_fence_driver_fini(struct radeon_device *rdev);
  272. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
  273. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
  274. void radeon_fence_process(struct radeon_device *rdev);
  275. bool radeon_fence_signaled(struct radeon_fence *fence);
  276. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  277. int radeon_fence_wait_next(struct radeon_device *rdev);
  278. int radeon_fence_wait_last(struct radeon_device *rdev);
  279. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  280. void radeon_fence_unref(struct radeon_fence **fence);
  281.  
  282. /*
  283.  * Tiling registers
  284.  */
  285. struct radeon_surface_reg {
  286.         struct radeon_bo *bo;
  287. };
  288.  
  289. #define RADEON_GEM_MAX_SURFACES 8
  290.  
  291. /*
  292.  * TTM.
  293.  */
  294. struct radeon_mman {
  295.         struct ttm_bo_global_ref        bo_global_ref;
  296.         struct ttm_global_reference     mem_global_ref;
  297.         struct ttm_bo_device            bdev;
  298.         bool                            mem_global_referenced;
  299.         bool                            initialized;
  300. };
  301.  
  302. struct radeon_bo {
  303.         /* Protected by gem.mutex */
  304.         struct list_head                list;
  305.         /* Protected by tbo.reserved */
  306.         u32                             placements[3];
  307.         struct ttm_placement            placement;
  308.         struct ttm_buffer_object        tbo;
  309.         struct ttm_bo_kmap_obj          kmap;
  310.     unsigned                    pin_count;
  311.     void                       *kptr;
  312.     u32                         cpu_addr;
  313.     u32                         tiling_flags;
  314.     u32                         pitch;
  315.     int                         surface_reg;
  316.         /* Constant after initialization */
  317.         struct radeon_device            *rdev;
  318.         struct drm_gem_object           *gobj;
  319.     u32                          domain;
  320. };
  321.  
  322. struct radeon_bo_list {
  323.         struct list_head        list;
  324.         struct radeon_bo        *bo;
  325.         uint64_t                gpu_offset;
  326.         unsigned                rdomain;
  327.         unsigned                wdomain;
  328.         u32                     tiling_flags;
  329. };
  330.  
  331. /*
  332.  * GEM objects.
  333.  */
  334. struct radeon_gem {
  335.         struct mutex            mutex;
  336.         struct list_head        objects;
  337. };
  338.  
  339. int radeon_gem_init(struct radeon_device *rdev);
  340. void radeon_gem_fini(struct radeon_device *rdev);
  341. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  342.                              int alignment, int initial_domain,
  343.                              bool discardable, bool kernel,
  344.                              struct drm_gem_object **obj);
  345. int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
  346.                           uint64_t *gpu_addr);
  347. void radeon_gem_object_unpin(struct drm_gem_object *obj);
  348.  
  349.  
  350. /*
  351.  * GART structures, functions & helpers
  352.  */
  353. struct radeon_mc;
  354.  
  355. struct radeon_gart_table_ram {
  356.     volatile uint32_t       *ptr;
  357. };
  358.  
  359. struct radeon_gart_table_vram {
  360.         struct radeon_bo                *robj;
  361.     volatile uint32_t       *ptr;
  362. };
  363.  
  364. union radeon_gart_table {
  365.     struct radeon_gart_table_ram    ram;
  366.     struct radeon_gart_table_vram   vram;
  367. };
  368.  
  369. #define RADEON_GPU_PAGE_SIZE 4096
  370. #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
  371.  
  372. struct radeon_gart {
  373.     dma_addr_t          table_addr;
  374.     unsigned            num_gpu_pages;
  375.     unsigned            num_cpu_pages;
  376.     unsigned            table_size;
  377.     union radeon_gart_table     table;
  378.     struct page         **pages;
  379.     dma_addr_t          *pages_addr;
  380.     bool                ready;
  381. };
  382.  
  383. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  384. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  385. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  386. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  387. int radeon_gart_init(struct radeon_device *rdev);
  388. void radeon_gart_fini(struct radeon_device *rdev);
  389. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  390.                         int pages);
  391. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  392.             int pages, u32_t *pagelist);
  393.  
  394.  
  395. /*
  396.  * GPU MC structures, functions & helpers
  397.  */
  398. struct radeon_mc {
  399.     resource_size_t     aper_size;
  400.     resource_size_t     aper_base;
  401.     resource_size_t     agp_base;
  402.         /* for some chips with <= 32MB we need to lie
  403.          * about vram size near mc fb location */
  404.         u64                     mc_vram_size;
  405.         u64                     visible_vram_size;
  406.         u64                     gtt_size;
  407.         u64                     gtt_start;
  408.         u64                     gtt_end;
  409.         u64                     vram_start;
  410.         u64                     vram_end;
  411.     unsigned            vram_width;
  412.         u64                     real_vram_size;
  413.     int                 vram_mtrr;
  414.     bool                vram_is_ddr;
  415.         bool                    igp_sideport_enabled;
  416. };
  417.  
  418. bool radeon_combios_sideport_present(struct radeon_device *rdev);
  419. bool radeon_atombios_sideport_present(struct radeon_device *rdev);
  420.  
  421. /*
  422.  * GPU scratch registers structures, functions & helpers
  423.  */
  424. struct radeon_scratch {
  425.     unsigned        num_reg;
  426.     bool            free[32];
  427.     uint32_t        reg[32];
  428. };
  429.  
  430. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  431. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  432.  
  433.  
  434. /*
  435.  * IRQS.
  436.  */
  437. struct radeon_irq {
  438.         bool            installed;
  439.         bool            sw_int;
  440.         /* FIXME: use a define max crtc rather than hardcode it */
  441.         bool            crtc_vblank_int[2];
  442.         /* FIXME: use defines for max hpd/dacs */
  443.         bool            hpd[6];
  444.     spinlock_t  sw_lock;
  445.         int sw_refcount;
  446. };
  447.  
  448. int radeon_irq_kms_init(struct radeon_device *rdev);
  449. void radeon_irq_kms_fini(struct radeon_device *rdev);
  450. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
  451. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
  452.  
  453. /*
  454.  * CP & ring.
  455.  */
  456. struct radeon_ib {
  457.     struct list_head    list;
  458.         unsigned                idx;
  459.     uint64_t            gpu_addr;
  460.         struct radeon_fence     *fence;
  461.     uint32_t            *ptr;
  462.     uint32_t            length_dw;
  463.         bool                    free;
  464. };
  465.  
  466. /*
  467.  * locking -
  468.  * mutex protects scheduled_ibs, ready, alloc_bm
  469.  */
  470. struct radeon_ib_pool {
  471.         struct mutex            mutex;
  472.         struct radeon_bo        *robj;
  473.         struct list_head        bogus_ib;
  474.         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
  475.     bool                ready;
  476.         unsigned                head_id;
  477. };
  478.  
  479. struct radeon_cp {
  480.         struct radeon_bo        *ring_obj;
  481.         volatile uint32_t       *ring;
  482.     unsigned            rptr;
  483.     unsigned            wptr;
  484.     unsigned            wptr_old;
  485.     unsigned            ring_size;
  486.     unsigned            ring_free_dw;
  487.     int                 count_dw;
  488.     uint64_t            gpu_addr;
  489.     uint32_t            align_mask;
  490.     uint32_t            ptr_mask;
  491.         struct mutex            mutex;
  492.     bool                ready;
  493. };
  494.  
  495. /*
  496.  * R6xx+ IH ring
  497.  */
  498. struct r600_ih {
  499.         struct radeon_bo        *ring_obj;
  500.         volatile uint32_t       *ring;
  501.     unsigned            rptr;
  502.     unsigned            wptr;
  503.     unsigned            wptr_old;
  504.     unsigned            ring_size;
  505.     uint64_t            gpu_addr;
  506.     uint32_t            ptr_mask;
  507.     spinlock_t              lock;
  508.     bool                enabled;
  509. };
  510.  
  511. struct r600_blit {
  512.         struct mutex            mutex;
  513.         struct radeon_bo        *shader_obj;
  514.         u64 shader_gpu_addr;
  515.         u32 vs_offset, ps_offset;
  516.         u32 state_offset;
  517.         u32 state_len;
  518.         u32 vb_used, vb_total;
  519.         struct radeon_ib *vb_ib;
  520. };
  521.  
  522. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
  523. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
  524. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
  525. int radeon_ib_pool_init(struct radeon_device *rdev);
  526. void radeon_ib_pool_fini(struct radeon_device *rdev);
  527. int radeon_ib_test(struct radeon_device *rdev);
  528. extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
  529. /* Ring access between begin & end cannot sleep */
  530. void radeon_ring_free_size(struct radeon_device *rdev);
  531. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
  532. void radeon_ring_unlock_commit(struct radeon_device *rdev);
  533. void radeon_ring_unlock_undo(struct radeon_device *rdev);
  534. int radeon_ring_test(struct radeon_device *rdev);
  535. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
  536. void radeon_ring_fini(struct radeon_device *rdev);
  537.  
  538.  
  539. /*
  540.  * CS.
  541.  */
  542. struct radeon_cs_reloc {
  543. //      struct drm_gem_object           *gobj;
  544.         struct radeon_bo                *robj;
  545.         struct radeon_bo_list           lobj;
  546.     uint32_t                handle;
  547.     uint32_t                flags;
  548. };
  549.  
  550. struct radeon_cs_chunk {
  551.         uint32_t                chunk_id;
  552.         uint32_t                length_dw;
  553.         int kpage_idx[2];
  554.         uint32_t                *kpage[2];
  555.         uint32_t                *kdata;
  556.         void __user *user_ptr;
  557.         int last_copied_page;
  558.         int last_page_index;
  559. };
  560.  
  561. struct radeon_cs_parser {
  562.         struct device           *dev;
  563.         struct radeon_device    *rdev;
  564. //      struct drm_file         *filp;
  565.         /* chunks */
  566.         unsigned                nchunks;
  567.         struct radeon_cs_chunk  *chunks;
  568.         uint64_t                *chunks_array;
  569.         /* IB */
  570.         unsigned                idx;
  571.         /* relocations */
  572.         unsigned                nrelocs;
  573.         struct radeon_cs_reloc  *relocs;
  574.         struct radeon_cs_reloc  **relocs_ptr;
  575.         struct list_head        validated;
  576.         /* indices of various chunks */
  577.         int                     chunk_ib_idx;
  578.         int                     chunk_relocs_idx;
  579.         struct radeon_ib        *ib;
  580.         void                    *track;
  581.         unsigned                family;
  582.         int parser_error;
  583. };
  584.  
  585. extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
  586. extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
  587.  
  588.  
  589. static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  590. {
  591.         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  592.         u32 pg_idx, pg_offset;
  593.         u32 idx_value = 0;
  594.         int new_page;
  595.  
  596.         pg_idx = (idx * 4) / PAGE_SIZE;
  597.         pg_offset = (idx * 4) % PAGE_SIZE;
  598.  
  599.         if (ibc->kpage_idx[0] == pg_idx)
  600.                 return ibc->kpage[0][pg_offset/4];
  601.         if (ibc->kpage_idx[1] == pg_idx)
  602.                 return ibc->kpage[1][pg_offset/4];
  603.  
  604.         new_page = radeon_cs_update_pages(p, pg_idx);
  605.         if (new_page < 0) {
  606.                 p->parser_error = new_page;
  607.                 return 0;
  608.         }
  609.  
  610.         idx_value = ibc->kpage[new_page][pg_offset/4];
  611.         return idx_value;
  612. }
  613.  
  614. struct radeon_cs_packet {
  615.         unsigned        idx;
  616.         unsigned        type;
  617.         unsigned        reg;
  618.         unsigned        opcode;
  619.         int             count;
  620.         unsigned        one_reg_wr;
  621. };
  622.  
  623. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  624.                                       struct radeon_cs_packet *pkt,
  625.                                       unsigned idx, unsigned reg);
  626. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  627.                                       struct radeon_cs_packet *pkt);
  628.  
  629.  
  630. /*
  631.  * AGP
  632.  */
  633. int radeon_agp_init(struct radeon_device *rdev);
  634. void radeon_agp_resume(struct radeon_device *rdev);
  635. void radeon_agp_fini(struct radeon_device *rdev);
  636.  
  637.  
  638. /*
  639.  * Writeback
  640.  */
  641. struct radeon_wb {
  642.         struct radeon_bo        *wb_obj;
  643.         volatile uint32_t       *wb;
  644.         uint64_t                gpu_addr;
  645. };
  646.  
  647. /**
  648.  * struct radeon_pm - power management datas
  649.  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
  650.  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  651.  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
  652.  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
  653.  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
  654.  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
  655.  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  656.  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
  657.  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
  658.  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
  659.  * @needed_bandwidth:   current bandwidth needs
  660.  *
  661.  * It keeps track of various data needed to take powermanagement decision.
  662.  * Bandwith need is used to determine minimun clock of the GPU and memory.
  663.  * Equation between gpu/memory clock and available bandwidth is hw dependent
  664.  * (type of memory, bus size, efficiency, ...)
  665.  */
  666. enum radeon_pm_state {
  667.         PM_STATE_DISABLED,
  668.         PM_STATE_MINIMUM,
  669.         PM_STATE_PAUSED,
  670.         PM_STATE_ACTIVE
  671. };
  672. enum radeon_pm_action {
  673.         PM_ACTION_NONE,
  674.         PM_ACTION_MINIMUM,
  675.         PM_ACTION_DOWNCLOCK,
  676.         PM_ACTION_UPCLOCK
  677. };
  678.  
  679. enum radeon_voltage_type {
  680.         VOLTAGE_NONE = 0,
  681.         VOLTAGE_GPIO,
  682.         VOLTAGE_VDDC,
  683.         VOLTAGE_SW
  684. };
  685.  
  686. enum radeon_pm_state_type {
  687.         POWER_STATE_TYPE_DEFAULT,
  688.         POWER_STATE_TYPE_POWERSAVE,
  689.         POWER_STATE_TYPE_BATTERY,
  690.         POWER_STATE_TYPE_BALANCED,
  691.         POWER_STATE_TYPE_PERFORMANCE,
  692. };
  693.  
  694. enum radeon_pm_clock_mode_type {
  695.         POWER_MODE_TYPE_DEFAULT,
  696.         POWER_MODE_TYPE_LOW,
  697.         POWER_MODE_TYPE_MID,
  698.         POWER_MODE_TYPE_HIGH,
  699. };
  700.  
  701. struct radeon_voltage {
  702.         enum radeon_voltage_type type;
  703.         /* gpio voltage */
  704.         struct radeon_gpio_rec gpio;
  705.         u32 delay; /* delay in usec from voltage drop to sclk change */
  706.         bool active_high; /* voltage drop is active when bit is high */
  707.         /* VDDC voltage */
  708.         u8 vddc_id; /* index into vddc voltage table */
  709.         u8 vddci_id; /* index into vddci voltage table */
  710.         bool vddci_enabled;
  711.         /* r6xx+ sw */
  712.         u32 voltage;
  713. };
  714.  
  715. struct radeon_pm_non_clock_info {
  716.         /* pcie lanes */
  717.         int pcie_lanes;
  718.         /* standardized non-clock flags */
  719.         u32 flags;
  720. };
  721.  
  722. struct radeon_pm_clock_info {
  723.         /* memory clock */
  724.         u32 mclk;
  725.         /* engine clock */
  726.         u32 sclk;
  727.         /* voltage info */
  728.         struct radeon_voltage voltage;
  729.         /* standardized clock flags - not sure we'll need these */
  730.         u32 flags;
  731. };
  732.  
  733. struct radeon_power_state {
  734.         enum radeon_pm_state_type type;
  735.         /* XXX: use a define for num clock modes */
  736.         struct radeon_pm_clock_info clock_info[8];
  737.         /* number of valid clock modes in this power state */
  738.         int num_clock_modes;
  739.         struct radeon_pm_clock_info *default_clock_mode;
  740.         /* non clock info about this state */
  741.         struct radeon_pm_non_clock_info non_clock_info;
  742.         bool voltage_drop_active;
  743. };
  744.  
  745. /*
  746.  * Some modes are overclocked by very low value, accept them
  747.  */
  748. #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
  749.  
  750. struct radeon_pm {
  751.         struct mutex            mutex;
  752. //      struct delayed_work     idle_work;
  753.         enum radeon_pm_state    state;
  754.         enum radeon_pm_action   planned_action;
  755.         unsigned long           action_timeout;
  756.         bool                    downclocked;
  757.         int                     active_crtcs;
  758.         int                     req_vblank;
  759.         fixed20_12              max_bandwidth;
  760.         fixed20_12              igp_sideport_mclk;
  761.         fixed20_12              igp_system_mclk;
  762.         fixed20_12              igp_ht_link_clk;
  763.         fixed20_12              igp_ht_link_width;
  764.         fixed20_12              k8_bandwidth;
  765.         fixed20_12              sideport_bandwidth;
  766.         fixed20_12              ht_bandwidth;
  767.         fixed20_12              core_bandwidth;
  768.         fixed20_12              sclk;
  769.         fixed20_12              needed_bandwidth;
  770.         /* XXX: use a define for num power modes */
  771.         struct radeon_power_state power_state[8];
  772.         /* number of valid power states */
  773.         int                     num_power_states;
  774.         struct radeon_power_state *current_power_state;
  775.         struct radeon_pm_clock_info *current_clock_mode;
  776.         struct radeon_power_state *requested_power_state;
  777.         struct radeon_pm_clock_info *requested_clock_mode;
  778.         struct radeon_power_state *default_power_state;
  779. };
  780.  
  781. /*
  782.  * ASIC specific functions.
  783.  */
  784. struct radeon_asic {
  785.         int (*init)(struct radeon_device *rdev);
  786.         void (*fini)(struct radeon_device *rdev);
  787.         int (*resume)(struct radeon_device *rdev);
  788.         int (*suspend)(struct radeon_device *rdev);
  789.         void (*vga_set_state)(struct radeon_device *rdev, bool state);
  790.         int (*gpu_reset)(struct radeon_device *rdev);
  791.         void (*gart_tlb_flush)(struct radeon_device *rdev);
  792.         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  793.         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
  794.         void (*cp_fini)(struct radeon_device *rdev);
  795.         void (*cp_disable)(struct radeon_device *rdev);
  796.         void (*cp_commit)(struct radeon_device *rdev);
  797.         void (*ring_start)(struct radeon_device *rdev);
  798.         int (*ring_test)(struct radeon_device *rdev);
  799.         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  800.         int (*irq_set)(struct radeon_device *rdev);
  801.         int (*irq_process)(struct radeon_device *rdev);
  802.         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  803.         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
  804.         int (*cs_parse)(struct radeon_cs_parser *p);
  805.         int (*copy_blit)(struct radeon_device *rdev,
  806.                          uint64_t src_offset,
  807.                          uint64_t dst_offset,
  808.                          unsigned num_pages,
  809.                          struct radeon_fence *fence);
  810.         int (*copy_dma)(struct radeon_device *rdev,
  811.                         uint64_t src_offset,
  812.                         uint64_t dst_offset,
  813.                         unsigned num_pages,
  814.                         struct radeon_fence *fence);
  815.         int (*copy)(struct radeon_device *rdev,
  816.                     uint64_t src_offset,
  817.                     uint64_t dst_offset,
  818.                     unsigned num_pages,
  819.                     struct radeon_fence *fence);
  820.         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
  821.         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  822.         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
  823.         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  824.         int (*get_pcie_lanes)(struct radeon_device *rdev);
  825.         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  826.         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  827.         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
  828.                                uint32_t tiling_flags, uint32_t pitch,
  829.                                uint32_t offset, uint32_t obj_size);
  830.         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
  831.         void (*bandwidth_update)(struct radeon_device *rdev);
  832.         void (*hpd_init)(struct radeon_device *rdev);
  833.         void (*hpd_fini)(struct radeon_device *rdev);
  834.         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  835.         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  836.         /* ioctl hw specific callback. Some hw might want to perform special
  837.          * operation on specific ioctl. For instance on wait idle some hw
  838.          * might want to perform and HDP flush through MMIO as it seems that
  839.          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
  840.          * through ring.
  841.          */
  842.         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
  843. };
  844.  
  845. /*
  846.  * Asic structures
  847.  */
  848. struct r100_asic {
  849.         const unsigned  *reg_safe_bm;
  850.         unsigned        reg_safe_bm_size;
  851.         u32             hdp_cntl;
  852. };
  853.  
  854. struct r300_asic {
  855.         const unsigned  *reg_safe_bm;
  856.         unsigned        reg_safe_bm_size;
  857.         u32             resync_scratch;
  858.         u32             hdp_cntl;
  859. };
  860.  
  861. struct r600_asic {
  862.         unsigned max_pipes;
  863.         unsigned max_tile_pipes;
  864.         unsigned max_simds;
  865.         unsigned max_backends;
  866.         unsigned max_gprs;
  867.         unsigned max_threads;
  868.         unsigned max_stack_entries;
  869.         unsigned max_hw_contexts;
  870.         unsigned max_gs_threads;
  871.         unsigned sx_max_export_size;
  872.         unsigned sx_max_export_pos_size;
  873.         unsigned sx_max_export_smx_size;
  874.         unsigned sq_num_cf_insts;
  875.         unsigned tiling_nbanks;
  876.         unsigned tiling_npipes;
  877.         unsigned tiling_group_size;
  878. };
  879.  
  880. struct rv770_asic {
  881.         unsigned max_pipes;
  882.         unsigned max_tile_pipes;
  883.         unsigned max_simds;
  884.         unsigned max_backends;
  885.         unsigned max_gprs;
  886.         unsigned max_threads;
  887.         unsigned max_stack_entries;
  888.         unsigned max_hw_contexts;
  889.         unsigned max_gs_threads;
  890.         unsigned sx_max_export_size;
  891.         unsigned sx_max_export_pos_size;
  892.         unsigned sx_max_export_smx_size;
  893.         unsigned sq_num_cf_insts;
  894.         unsigned sx_num_of_sets;
  895.         unsigned sc_prim_fifo_size;
  896.         unsigned sc_hiz_tile_fifo_size;
  897.         unsigned sc_earlyz_tile_fifo_fize;
  898.         unsigned tiling_nbanks;
  899.         unsigned tiling_npipes;
  900.         unsigned tiling_group_size;
  901. };
  902.  
  903. union radeon_asic_config {
  904.         struct r300_asic        r300;
  905.         struct r100_asic        r100;
  906.         struct r600_asic        r600;
  907.         struct rv770_asic       rv770;
  908. };
  909.  
  910.  
  911. /*
  912.  
  913.  
  914.  
  915.  
  916. /*
  917.  * Core structure, functions and helpers.
  918.  */
  919. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  920. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  921.  
  922. struct radeon_device {
  923.         struct device                   *dev;
  924.     struct drm_device          *ddev;
  925.     struct pci_dev             *pdev;
  926.     /* ASIC */
  927.     union radeon_asic_config    config;
  928.     enum radeon_family          family;
  929.     unsigned long               flags;
  930.     int                         usec_timeout;
  931.     enum radeon_pll_errata      pll_errata;
  932.     int                         num_gb_pipes;
  933.         int                                         num_z_pipes;
  934.     int                         disp_priority;
  935.     /* BIOS */
  936.     uint8_t                     *bios;
  937.     bool                        is_atom_bios;
  938.     uint16_t                    bios_header_start;
  939.         struct radeon_bo                    *stollen_vga_memory;
  940.     struct fb_info              *fbdev_info;
  941.         struct radeon_bo                    *fbdev_rbo;
  942.     struct radeon_framebuffer   *fbdev_rfb;
  943.     /* Register mmio */
  944.     unsigned long               rmmio_base;
  945.     unsigned long               rmmio_size;
  946.     void                       *rmmio;
  947.     radeon_rreg_t               mc_rreg;
  948.     radeon_wreg_t               mc_wreg;
  949.     radeon_rreg_t               pll_rreg;
  950.     radeon_wreg_t               pll_wreg;
  951.         uint32_t                        pcie_reg_mask;
  952.     radeon_rreg_t               pciep_rreg;
  953.     radeon_wreg_t               pciep_wreg;
  954.     struct radeon_clock         clock;
  955.     struct radeon_mc            mc;
  956.     struct radeon_gart          gart;
  957.         struct radeon_mode_info         mode_info;
  958.     struct radeon_scratch       scratch;
  959.     struct radeon_mman          mman;
  960.         struct radeon_fence_driver      fence_drv;
  961.     struct radeon_cp            cp;
  962.     struct radeon_ib_pool       ib_pool;
  963. //    struct radeon_irq       irq;
  964.     struct radeon_asic         *asic;
  965.     struct radeon_gem       gem;
  966.         struct radeon_pm                pm;
  967.         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  968.         struct mutex                    cs_mutex;
  969.     struct radeon_wb        wb;
  970.         struct radeon_dummy_page        dummy_page;
  971.     bool                gpu_lockup;
  972.     bool                shutdown;
  973.     bool                suspend;
  974.         bool                            need_dma32;
  975.         bool                            accel_working;
  976.         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  977.         const struct firmware *me_fw;   /* all family ME firmware */
  978.         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
  979.         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
  980.         struct r600_blit r600_blit;
  981.         int msi_enabled; /* msi enabled */
  982.         int num_crtc; /* number of crtcs */
  983.         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
  984.  
  985.         /* audio stuff */
  986. //   struct timer_list   audio_timer;
  987.         int                     audio_channels;
  988.         int                     audio_rate;
  989.         int                     audio_bits_per_sample;
  990.         uint8_t                 audio_status_bits;
  991.         uint8_t                 audio_category_code;
  992.  
  993.         bool powered_down;
  994. };
  995.  
  996. int radeon_device_init(struct radeon_device *rdev,
  997.                        struct drm_device *ddev,
  998.                        struct pci_dev *pdev,
  999.                        uint32_t flags);
  1000. void radeon_device_fini(struct radeon_device *rdev);
  1001. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  1002.  
  1003. /* r600 blit */
  1004. int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
  1005. void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
  1006. void r600_kms_blit_copy(struct radeon_device *rdev,
  1007.                         u64 src_gpu_addr, u64 dst_gpu_addr,
  1008.                         int size_bytes);
  1009.  
  1010. static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
  1011. {
  1012.         if (reg < rdev->rmmio_size)
  1013.                 return readl(((void __iomem *)rdev->rmmio) + reg);
  1014.         else {
  1015.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  1016.                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  1017.         }
  1018. }
  1019.  
  1020. static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  1021. {
  1022.         if (reg < rdev->rmmio_size)
  1023.                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
  1024.         else {
  1025.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  1026.                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  1027.         }
  1028. }
  1029.  
  1030. /*
  1031.  * Cast helper
  1032.  */
  1033. #define to_radeon_fence(p) ((struct radeon_fence *)(p))
  1034.  
  1035. /*
  1036.  * Registers read & write functions.
  1037.  */
  1038. #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
  1039. #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
  1040. #define RREG32(reg) r100_mm_rreg(rdev, (reg))
  1041. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
  1042. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  1043. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  1044. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  1045. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  1046. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  1047. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  1048. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  1049. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  1050. #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
  1051. #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
  1052. #define WREG32_P(reg, val, mask)                                \
  1053.         do {                                                    \
  1054.                 uint32_t tmp_ = RREG32(reg);                    \
  1055.                 tmp_ &= (mask);                                 \
  1056.                 tmp_ |= ((val) & ~(mask));                      \
  1057.                 WREG32(reg, tmp_);                              \
  1058.         } while (0)
  1059. #define WREG32_PLL_P(reg, val, mask)                            \
  1060.         do {                                                    \
  1061.                 uint32_t tmp_ = RREG32_PLL(reg);                \
  1062.                 tmp_ &= (mask);                                 \
  1063.                 tmp_ |= ((val) & ~(mask));                      \
  1064.                 WREG32_PLL(reg, tmp_);                          \
  1065.         } while (0)
  1066.  
  1067. /*
  1068.  * Indirect registers accessor
  1069.  */
  1070. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  1071. {
  1072.         uint32_t r;
  1073.  
  1074.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  1075.         r = RREG32(RADEON_PCIE_DATA);
  1076.         return r;
  1077. }
  1078.  
  1079. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  1080. {
  1081.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  1082.         WREG32(RADEON_PCIE_DATA, (v));
  1083. }
  1084.  
  1085. void r100_pll_errata_after_index(struct radeon_device *rdev);
  1086.  
  1087.  
  1088. /*
  1089.  * ASICs helpers.
  1090.  */
  1091. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  1092.                             (rdev->pdev->device == 0x5969))
  1093. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  1094.         (rdev->family == CHIP_RV200) || \
  1095.         (rdev->family == CHIP_RS100) || \
  1096.         (rdev->family == CHIP_RS200) || \
  1097.         (rdev->family == CHIP_RV250) || \
  1098.         (rdev->family == CHIP_RV280) || \
  1099.         (rdev->family == CHIP_RS300))
  1100. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
  1101.         (rdev->family == CHIP_RV350) ||         \
  1102.         (rdev->family == CHIP_R350)  ||         \
  1103.         (rdev->family == CHIP_RV380) ||         \
  1104.         (rdev->family == CHIP_R420)  ||         \
  1105.         (rdev->family == CHIP_R423)  ||         \
  1106.         (rdev->family == CHIP_RV410) ||         \
  1107.         (rdev->family == CHIP_RS400) ||         \
  1108.         (rdev->family == CHIP_RS480))
  1109. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  1110. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  1111. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  1112. #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
  1113.  
  1114. /*
  1115.  * BIOS helpers.
  1116.  */
  1117. #define RBIOS8(i) (rdev->bios[i])
  1118. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  1119. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  1120.  
  1121. int radeon_combios_init(struct radeon_device *rdev);
  1122. void radeon_combios_fini(struct radeon_device *rdev);
  1123. int radeon_atombios_init(struct radeon_device *rdev);
  1124. void radeon_atombios_fini(struct radeon_device *rdev);
  1125.  
  1126.  
  1127. /*
  1128.  * RING helpers.
  1129.  */
  1130. static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  1131. {
  1132. #if DRM_DEBUG_CODE
  1133.         if (rdev->cp.count_dw <= 0) {
  1134.                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  1135.         }
  1136. #endif
  1137.         rdev->cp.ring[rdev->cp.wptr++] = v;
  1138.         rdev->cp.wptr &= rdev->cp.ptr_mask;
  1139.         rdev->cp.count_dw--;
  1140.         rdev->cp.ring_free_dw--;
  1141. }
  1142.  
  1143.  
  1144. /*
  1145.  * ASICs macro.
  1146.  */
  1147. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  1148. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  1149. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  1150. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  1151. #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
  1152. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  1153. #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
  1154. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
  1155. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
  1156. #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
  1157. #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
  1158. #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
  1159. #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
  1160. #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
  1161. #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
  1162. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
  1163. #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
  1164. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
  1165. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
  1166. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
  1167. #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
  1168. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  1169. #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
  1170. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
  1171. #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
  1172. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
  1173. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
  1174. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
  1175. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
  1176. #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
  1177. #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
  1178. #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
  1179. #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
  1180. #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
  1181.  
  1182. /* Common functions */
  1183. /* AGP */
  1184. extern void radeon_agp_disable(struct radeon_device *rdev);
  1185. extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  1186. extern void radeon_gart_restore(struct radeon_device *rdev);
  1187. extern int radeon_modeset_init(struct radeon_device *rdev);
  1188. extern void radeon_modeset_fini(struct radeon_device *rdev);
  1189. extern bool radeon_card_posted(struct radeon_device *rdev);
  1190. extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
  1191. extern int radeon_clocks_init(struct radeon_device *rdev);
  1192. extern void radeon_clocks_fini(struct radeon_device *rdev);
  1193. extern void radeon_scratch_init(struct radeon_device *rdev);
  1194. extern void radeon_surface_init(struct radeon_device *rdev);
  1195. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  1196. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  1197. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  1198. extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
  1199. extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
  1200. extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
  1201. extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
  1202. extern int radeon_resume_kms(struct drm_device *dev);
  1203. extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
  1204.  
  1205. /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
  1206. struct r100_mc_save {
  1207.         u32     GENMO_WT;
  1208.         u32     CRTC_EXT_CNTL;
  1209.         u32     CRTC_GEN_CNTL;
  1210.         u32     CRTC2_GEN_CNTL;
  1211.         u32     CUR_OFFSET;
  1212.         u32     CUR2_OFFSET;
  1213. };
  1214. extern void r100_cp_disable(struct radeon_device *rdev);
  1215. extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  1216. extern void r100_cp_fini(struct radeon_device *rdev);
  1217. extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  1218. extern int r100_pci_gart_init(struct radeon_device *rdev);
  1219. extern void r100_pci_gart_fini(struct radeon_device *rdev);
  1220. extern int r100_pci_gart_enable(struct radeon_device *rdev);
  1221. extern void r100_pci_gart_disable(struct radeon_device *rdev);
  1222. extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  1223. extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  1224. extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
  1225. extern void r100_ib_fini(struct radeon_device *rdev);
  1226. extern int r100_ib_init(struct radeon_device *rdev);
  1227. extern void r100_irq_disable(struct radeon_device *rdev);
  1228. extern int r100_irq_set(struct radeon_device *rdev);
  1229. extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
  1230. extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
  1231. extern void r100_vram_init_sizes(struct radeon_device *rdev);
  1232. extern void r100_wb_disable(struct radeon_device *rdev);
  1233. extern void r100_wb_fini(struct radeon_device *rdev);
  1234. extern int r100_wb_init(struct radeon_device *rdev);
  1235. extern void r100_hdp_reset(struct radeon_device *rdev);
  1236. extern int r100_rb2d_reset(struct radeon_device *rdev);
  1237. extern int r100_cp_reset(struct radeon_device *rdev);
  1238. extern void r100_vga_render_disable(struct radeon_device *rdev);
  1239. extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  1240.                                                 struct radeon_cs_packet *pkt,
  1241.                                                 struct radeon_bo *robj);
  1242. extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  1243.                                 struct radeon_cs_packet *pkt,
  1244.                                 const unsigned *auth, unsigned n,
  1245.                                 radeon_packet0_check_t check);
  1246. extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
  1247.                                 struct radeon_cs_packet *pkt,
  1248.                                 unsigned idx);
  1249. extern void r100_enable_bm(struct radeon_device *rdev);
  1250. extern void r100_set_common_regs(struct radeon_device *rdev);
  1251.  
  1252. /* rv200,rv250,rv280 */
  1253. extern void r200_set_safe_registers(struct radeon_device *rdev);
  1254.  
  1255. /* r300,r350,rv350,rv370,rv380 */
  1256. extern void r300_set_reg_safe(struct radeon_device *rdev);
  1257. extern void r300_mc_program(struct radeon_device *rdev);
  1258. extern void r300_mc_init(struct radeon_device *rdev);
  1259. extern void r300_clock_startup(struct radeon_device *rdev);
  1260. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  1261. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
  1262. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
  1263. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
  1264. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
  1265.  
  1266. /* r420,r423,rv410 */
  1267. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
  1268. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  1269. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  1270. extern void r420_pipes_init(struct radeon_device *rdev);
  1271.  
  1272. /* rv515 */
  1273. struct rv515_mc_save {
  1274.         u32 d1vga_control;
  1275.         u32 d2vga_control;
  1276.         u32 vga_render_control;
  1277.         u32 vga_hdp_control;
  1278.         u32 d1crtc_control;
  1279.         u32 d2crtc_control;
  1280. };
  1281. extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  1282. extern void rv515_vga_render_disable(struct radeon_device *rdev);
  1283. extern void rv515_set_safe_registers(struct radeon_device *rdev);
  1284. extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
  1285. extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
  1286. extern void rv515_clock_startup(struct radeon_device *rdev);
  1287. extern void rv515_debugfs(struct radeon_device *rdev);
  1288. extern int rv515_suspend(struct radeon_device *rdev);
  1289.  
  1290. /* rs400 */
  1291. extern int rs400_gart_init(struct radeon_device *rdev);
  1292. extern int rs400_gart_enable(struct radeon_device *rdev);
  1293. extern void rs400_gart_adjust_size(struct radeon_device *rdev);
  1294. extern void rs400_gart_disable(struct radeon_device *rdev);
  1295. extern void rs400_gart_fini(struct radeon_device *rdev);
  1296.  
  1297. /* rs600 */
  1298. extern void rs600_set_safe_registers(struct radeon_device *rdev);
  1299. extern int rs600_irq_set(struct radeon_device *rdev);
  1300. extern void rs600_irq_disable(struct radeon_device *rdev);
  1301.  
  1302. /* rs690, rs740 */
  1303. extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
  1304.                                         struct drm_display_mode *mode1,
  1305.                                         struct drm_display_mode *mode2);
  1306.  
  1307. /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
  1308. extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
  1309. extern bool r600_card_posted(struct radeon_device *rdev);
  1310. extern void r600_cp_stop(struct radeon_device *rdev);
  1311. extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1312. extern int r600_cp_resume(struct radeon_device *rdev);
  1313. extern void r600_cp_fini(struct radeon_device *rdev);
  1314. extern int r600_count_pipe_bits(uint32_t val);
  1315. extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
  1316. extern int r600_pcie_gart_init(struct radeon_device *rdev);
  1317. extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  1318. extern int r600_ib_test(struct radeon_device *rdev);
  1319. extern int r600_ring_test(struct radeon_device *rdev);
  1320. extern void r600_wb_fini(struct radeon_device *rdev);
  1321. extern int r600_wb_enable(struct radeon_device *rdev);
  1322. extern void r600_wb_disable(struct radeon_device *rdev);
  1323. extern void r600_scratch_init(struct radeon_device *rdev);
  1324. extern int r600_blit_init(struct radeon_device *rdev);
  1325. extern void r600_blit_fini(struct radeon_device *rdev);
  1326. extern int r600_init_microcode(struct radeon_device *rdev);
  1327. extern int r600_gpu_reset(struct radeon_device *rdev);
  1328. /* r600 irq */
  1329. extern int r600_irq_init(struct radeon_device *rdev);
  1330. extern void r600_irq_fini(struct radeon_device *rdev);
  1331. extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1332. extern int r600_irq_set(struct radeon_device *rdev);
  1333. extern void r600_irq_suspend(struct radeon_device *rdev);
  1334. /* r600 audio */
  1335. extern int r600_audio_init(struct radeon_device *rdev);
  1336. extern int r600_audio_tmds_index(struct drm_encoder *encoder);
  1337. extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
  1338. extern void r600_audio_fini(struct radeon_device *rdev);
  1339. extern void r600_hdmi_init(struct drm_encoder *encoder);
  1340. extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
  1341. extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  1342. extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
  1343. extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
  1344.                                             int channels,
  1345.                                             int rate,
  1346.                                             int bps,
  1347.                                             uint8_t status_bits,
  1348.                                             uint8_t category_code);
  1349.  
  1350. /* evergreen */
  1351. struct evergreen_mc_save {
  1352.         u32 vga_control[6];
  1353.         u32 vga_render_control;
  1354.         u32 vga_hdp_control;
  1355.         u32 crtc_control[6];
  1356. };
  1357.  
  1358. #include "radeon_object.h"
  1359.  
  1360. #define DRM_UDELAY(d)           udelay(d)
  1361.  
  1362. resource_size_t
  1363. drm_get_resource_start(struct drm_device *dev, unsigned int resource);
  1364. resource_size_t
  1365. drm_get_resource_len(struct drm_device *dev, unsigned int resource);
  1366.  
  1367. bool set_mode(struct drm_device *dev, struct drm_connector *connector,
  1368.               videomode_t *mode, bool strict);
  1369.  
  1370.  
  1371. #endif
  1372.