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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30.  
  31. /* TODO: Here are things that needs to be done :
  32.  *      - surface allocator & initializer : (bit like scratch reg) should
  33.  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34.  *        related to surface
  35.  *      - WB : write back stuff (do it bit like scratch reg things)
  36.  *      - Vblank : look at Jesse's rework and what we should do
  37.  *      - r600/r700: gart & cp
  38.  *      - cs : clean cs ioctl use bitmap & things like that.
  39.  *      - power management stuff
  40.  *      - Barrier in gart code
  41.  *      - Unmappabled vram ?
  42.  *      - TESTING, TESTING, TESTING
  43.  */
  44.  
  45. /* Initialization path:
  46.  *  We expect that acceleration initialization might fail for various
  47.  *  reasons even thought we work hard to make it works on most
  48.  *  configurations. In order to still have a working userspace in such
  49.  *  situation the init path must succeed up to the memory controller
  50.  *  initialization point. Failure before this point are considered as
  51.  *  fatal error. Here is the init callchain :
  52.  *      radeon_device_init  perform common structure, mutex initialization
  53.  *      asic_init           setup the GPU memory layout and perform all
  54.  *                          one time initialization (failure in this
  55.  *                          function are considered fatal)
  56.  *      asic_startup        setup the GPU acceleration, in order to
  57.  *                          follow guideline the first thing this
  58.  *                          function should do is setting the GPU
  59.  *                          memory controller (only MC setup failure
  60.  *                          are considered as fatal)
  61.  */
  62.  
  63. #include <asm/atomic.h>
  64.  
  65. #include <linux/list.h>
  66. #include <linux/kref.h>
  67.  
  68. #include <ttm/ttm_bo_api.h>
  69. #include <ttm/ttm_bo_driver.h>
  70. #include <ttm/ttm_placement.h>
  71. #include <ttm/ttm_module.h>
  72.  
  73.  
  74. #include <pci.h>
  75.  
  76. #include <errno-base.h>
  77. #include "drm_edid.h"
  78.  
  79. #include "radeon_family.h"
  80. #include "radeon_mode.h"
  81. #include "radeon_reg.h"
  82.  
  83. #include <syscall.h>
  84.  
  85. /*
  86.  * Modules parameters.
  87.  */
  88. extern int radeon_no_wb;
  89. extern int radeon_modeset;
  90. extern int radeon_dynclks;
  91. extern int radeon_r4xx_atom;
  92. extern int radeon_agpmode;
  93. extern int radeon_vram_limit;
  94. extern int radeon_gart_size;
  95. extern int radeon_benchmarking;
  96. extern int radeon_testing;
  97. extern int radeon_connector_table;
  98. extern int radeon_tv;
  99. extern int radeon_new_pll;
  100. extern int radeon_audio;
  101.  
  102. typedef struct
  103. {
  104.   int width;
  105.   int height;
  106.   int bpp;
  107.   int freq;
  108. }videomode_t;
  109.  
  110. static inline uint8_t __raw_readb(const volatile void __iomem *addr)
  111. {
  112.     return *(const volatile uint8_t __force *) addr;
  113. }
  114.  
  115. static inline uint16_t __raw_readw(const volatile void __iomem *addr)
  116. {
  117.     return *(const volatile uint16_t __force *) addr;
  118. }
  119.  
  120. static inline uint32_t __raw_readl(const volatile void __iomem *addr)
  121. {
  122.     return *(const volatile uint32_t __force *) addr;
  123. }
  124.  
  125. #define readb __raw_readb
  126. #define readw __raw_readw
  127. #define readl __raw_readl
  128.  
  129.  
  130.  
  131. static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
  132. {
  133.     *(volatile uint8_t __force *) addr = b;
  134. }
  135.  
  136. static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
  137. {
  138.     *(volatile uint16_t __force *) addr = b;
  139. }
  140.  
  141. static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
  142. {
  143.     *(volatile uint32_t __force *) addr = b;
  144. }
  145.  
  146. static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
  147. {
  148.         *(volatile __u64 *)addr = b;
  149. }
  150.  
  151. #define writeb __raw_writeb
  152. #define writew __raw_writew
  153. #define writel __raw_writel
  154. #define writeq __raw_writeq
  155.  
  156.  
  157. /*
  158.  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  159.  * symbol;
  160.  */
  161. #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  162. #define RADEON_IB_POOL_SIZE             16
  163. #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  164. #define RADEONFB_CONN_LIMIT             4
  165. #define RADEON_BIOS_NUM_SCRATCH         8
  166.  
  167. /*
  168.  * Errata workarounds.
  169.  */
  170. enum radeon_pll_errata {
  171.     CHIP_ERRATA_R300_CG             = 0x00000001,
  172.     CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  173.     CHIP_ERRATA_PLL_DELAY           = 0x00000004
  174. };
  175.  
  176.  
  177. struct radeon_device;
  178.  
  179.  
  180. /*
  181.  * BIOS.
  182.  */
  183. bool radeon_get_bios(struct radeon_device *rdev);
  184.  
  185.  
  186. /*
  187.  * Dummy page
  188.  */
  189. struct radeon_dummy_page {
  190.         struct page     *page;
  191.         dma_addr_t      addr;
  192. };
  193. int radeon_dummy_page_init(struct radeon_device *rdev);
  194. void radeon_dummy_page_fini(struct radeon_device *rdev);
  195.  
  196.  
  197. /*
  198.  * Clocks
  199.  */
  200. struct radeon_clock {
  201.         struct radeon_pll p1pll;
  202.         struct radeon_pll p2pll;
  203.         struct radeon_pll spll;
  204.         struct radeon_pll mpll;
  205.         /* 10 Khz units */
  206.         uint32_t default_mclk;
  207.         uint32_t default_sclk;
  208. };
  209.  
  210. /*
  211.  * Power management
  212.  */
  213. int radeon_pm_init(struct radeon_device *rdev);
  214.  
  215. /*
  216.  * Fences.
  217.  */
  218. struct radeon_fence_driver {
  219.         uint32_t                        scratch_reg;
  220.         atomic_t                        seq;
  221.         uint32_t                        last_seq;
  222.         unsigned long                   count_timeout;
  223. //      wait_queue_head_t               queue;
  224.         rwlock_t                        lock;
  225.         struct list_head                created;
  226.         struct list_head                emited;
  227.         struct list_head                signaled;
  228.         bool                            initialized;
  229. };
  230.  
  231. struct radeon_fence {
  232.         struct radeon_device            *rdev;
  233.         struct kref                     kref;
  234.         struct list_head                list;
  235.         /* protected by radeon_fence.lock */
  236.         uint32_t                        seq;
  237.         unsigned long                   timeout;
  238.         bool                            emited;
  239.         bool                            signaled;
  240. };
  241.  
  242. int radeon_fence_driver_init(struct radeon_device *rdev);
  243. void radeon_fence_driver_fini(struct radeon_device *rdev);
  244. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
  245. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
  246. void radeon_fence_process(struct radeon_device *rdev);
  247. bool radeon_fence_signaled(struct radeon_fence *fence);
  248. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  249. int radeon_fence_wait_next(struct radeon_device *rdev);
  250. int radeon_fence_wait_last(struct radeon_device *rdev);
  251. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  252. void radeon_fence_unref(struct radeon_fence **fence);
  253.  
  254. /*
  255.  * Tiling registers
  256.  */
  257. struct radeon_surface_reg {
  258.         struct radeon_bo *bo;
  259. };
  260.  
  261. #define RADEON_GEM_MAX_SURFACES 8
  262.  
  263. /*
  264.  * TTM.
  265.  */
  266. struct radeon_mman {
  267.         struct ttm_bo_global_ref        bo_global_ref;
  268.         struct ttm_global_reference     mem_global_ref;
  269.         struct ttm_bo_device            bdev;
  270.         bool                            mem_global_referenced;
  271.         bool                            initialized;
  272. };
  273.  
  274. struct radeon_bo {
  275.         /* Protected by gem.mutex */
  276.         struct list_head                list;
  277.         /* Protected by tbo.reserved */
  278.         u32                             placements[3];
  279.         struct ttm_placement            placement;
  280.         struct ttm_buffer_object        tbo;
  281.         struct ttm_bo_kmap_obj          kmap;
  282.         unsigned                        pin_count;
  283.         void                            *kptr;
  284.         u32                             tiling_flags;
  285.         u32                             pitch;
  286.         int                             surface_reg;
  287.         /* Constant after initialization */
  288.         struct radeon_device            *rdev;
  289.         struct drm_gem_object           *gobj;
  290. };
  291.  
  292. struct radeon_bo_list {
  293.         struct list_head        list;
  294.         struct radeon_bo        *bo;
  295.         uint64_t                gpu_offset;
  296.         unsigned                rdomain;
  297.         unsigned                wdomain;
  298.         u32                     tiling_flags;
  299. };
  300.  
  301. /*
  302.  * GEM objects.
  303.  */
  304. struct radeon_gem {
  305.         struct list_head        objects;
  306. };
  307.  
  308. int radeon_gem_init(struct radeon_device *rdev);
  309. void radeon_gem_fini(struct radeon_device *rdev);
  310. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  311.                              int alignment, int initial_domain,
  312.                              bool discardable, bool kernel,
  313.                              struct drm_gem_object **obj);
  314. int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
  315.                           uint64_t *gpu_addr);
  316. void radeon_gem_object_unpin(struct drm_gem_object *obj);
  317.  
  318.  
  319. /*
  320.  * GART structures, functions & helpers
  321.  */
  322. struct radeon_mc;
  323.  
  324. struct radeon_gart_table_ram {
  325.     volatile uint32_t       *ptr;
  326. };
  327.  
  328. struct radeon_gart_table_vram {
  329.         struct radeon_bo                *robj;
  330.     volatile uint32_t       *ptr;
  331. };
  332.  
  333. union radeon_gart_table {
  334.     struct radeon_gart_table_ram    ram;
  335.     struct radeon_gart_table_vram   vram;
  336. };
  337.  
  338. #define RADEON_GPU_PAGE_SIZE 4096
  339.  
  340. struct radeon_gart {
  341.     dma_addr_t          table_addr;
  342.     unsigned            num_gpu_pages;
  343.     unsigned            num_cpu_pages;
  344.     unsigned            table_size;
  345.     union radeon_gart_table     table;
  346.     struct page         **pages;
  347.     dma_addr_t          *pages_addr;
  348.     bool                ready;
  349. };
  350.  
  351. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  352. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  353. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  354. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  355. int radeon_gart_init(struct radeon_device *rdev);
  356. void radeon_gart_fini(struct radeon_device *rdev);
  357. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  358.                         int pages);
  359. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  360.             int pages, u32_t *pagelist);
  361.  
  362.  
  363. /*
  364.  * GPU MC structures, functions & helpers
  365.  */
  366. struct radeon_mc {
  367.     resource_size_t     aper_size;
  368.     resource_size_t     aper_base;
  369.     resource_size_t     agp_base;
  370.         /* for some chips with <= 32MB we need to lie
  371.          * about vram size near mc fb location */
  372.         u64                     mc_vram_size;
  373.         u64                     gtt_location;
  374.         u64                     gtt_size;
  375.         u64                     gtt_start;
  376.         u64                     gtt_end;
  377.         u64                     vram_location;
  378.         u64                     vram_start;
  379.         u64                     vram_end;
  380.     unsigned            vram_width;
  381.         u64                     real_vram_size;
  382.     int                 vram_mtrr;
  383.     bool                vram_is_ddr;
  384.         bool                    igp_sideport_enabled;
  385. };
  386.  
  387. int radeon_mc_setup(struct radeon_device *rdev);
  388. bool radeon_combios_sideport_present(struct radeon_device *rdev);
  389. bool radeon_atombios_sideport_present(struct radeon_device *rdev);
  390.  
  391. /*
  392.  * GPU scratch registers structures, functions & helpers
  393.  */
  394. struct radeon_scratch {
  395.     unsigned        num_reg;
  396.     bool            free[32];
  397.     uint32_t        reg[32];
  398. };
  399.  
  400. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  401. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  402.  
  403.  
  404. /*
  405.  * IRQS.
  406.  */
  407. struct radeon_irq {
  408.         bool            installed;
  409.         bool            sw_int;
  410.         /* FIXME: use a define max crtc rather than hardcode it */
  411.         bool            crtc_vblank_int[2];
  412.         /* FIXME: use defines for max hpd/dacs */
  413.         bool            hpd[6];
  414.     spinlock_t  sw_lock;
  415.         int sw_refcount;
  416. };
  417.  
  418. int radeon_irq_kms_init(struct radeon_device *rdev);
  419. void radeon_irq_kms_fini(struct radeon_device *rdev);
  420. void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
  421. void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
  422.  
  423. /*
  424.  * CP & ring.
  425.  */
  426. struct radeon_ib {
  427.     struct list_head    list;
  428.         unsigned long           idx;
  429.     uint64_t            gpu_addr;
  430.         struct radeon_fence     *fence;
  431.     uint32_t            *ptr;
  432.     uint32_t            length_dw;
  433. };
  434.  
  435. /*
  436.  * locking -
  437.  * mutex protects scheduled_ibs, ready, alloc_bm
  438.  */
  439. struct radeon_ib_pool {
  440. //   struct mutex        mutex;
  441.         struct radeon_bo        *robj;
  442.         struct list_head        scheduled_ibs;
  443.         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
  444.     bool                ready;
  445.         DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
  446. };
  447.  
  448. struct radeon_cp {
  449.         struct radeon_bo        *ring_obj;
  450.         volatile uint32_t       *ring;
  451.     unsigned            rptr;
  452.     unsigned            wptr;
  453.     unsigned            wptr_old;
  454.     unsigned            ring_size;
  455.     unsigned            ring_free_dw;
  456.     int                 count_dw;
  457.     uint64_t            gpu_addr;
  458.     uint32_t            align_mask;
  459.     uint32_t            ptr_mask;
  460. //      struct mutex            mutex;
  461.     bool                ready;
  462. };
  463.  
  464. /*
  465.  * R6xx+ IH ring
  466.  */
  467. struct r600_ih {
  468.         struct radeon_bo        *ring_obj;
  469.         volatile uint32_t       *ring;
  470.     unsigned            rptr;
  471.     unsigned            wptr;
  472.     unsigned            wptr_old;
  473.     unsigned            ring_size;
  474.     uint64_t            gpu_addr;
  475.     uint32_t            ptr_mask;
  476.     spinlock_t              lock;
  477.     bool                enabled;
  478. };
  479.  
  480. struct r600_blit {
  481.         struct radeon_bo        *shader_obj;
  482.         u64 shader_gpu_addr;
  483.         u32 vs_offset, ps_offset;
  484.         u32 state_offset;
  485.         u32 state_len;
  486.         u32 vb_used, vb_total;
  487.         struct radeon_ib *vb_ib;
  488. };
  489.  
  490. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
  491. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
  492. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
  493. int radeon_ib_pool_init(struct radeon_device *rdev);
  494. void radeon_ib_pool_fini(struct radeon_device *rdev);
  495. int radeon_ib_test(struct radeon_device *rdev);
  496. /* Ring access between begin & end cannot sleep */
  497. void radeon_ring_free_size(struct radeon_device *rdev);
  498. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
  499. void radeon_ring_unlock_commit(struct radeon_device *rdev);
  500. void radeon_ring_unlock_undo(struct radeon_device *rdev);
  501. int radeon_ring_test(struct radeon_device *rdev);
  502. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
  503. void radeon_ring_fini(struct radeon_device *rdev);
  504.  
  505.  
  506. /*
  507.  * CS.
  508.  */
  509. struct radeon_cs_reloc {
  510. //      struct drm_gem_object           *gobj;
  511.         struct radeon_bo                *robj;
  512. //    struct radeon_bo_list   lobj;
  513.     uint32_t                handle;
  514.     uint32_t                flags;
  515. };
  516.  
  517. struct radeon_cs_chunk {
  518.         uint32_t                chunk_id;
  519.         uint32_t                length_dw;
  520.         int kpage_idx[2];
  521.         uint32_t                *kpage[2];
  522.         uint32_t                *kdata;
  523.         void __user *user_ptr;
  524.         int last_copied_page;
  525.         int last_page_index;
  526. };
  527.  
  528. struct radeon_cs_parser {
  529.         struct radeon_device    *rdev;
  530. //      struct drm_file         *filp;
  531.         /* chunks */
  532.         unsigned                nchunks;
  533.         struct radeon_cs_chunk  *chunks;
  534.         uint64_t                *chunks_array;
  535.         /* IB */
  536.         unsigned                idx;
  537.         /* relocations */
  538.         unsigned                nrelocs;
  539.         struct radeon_cs_reloc  *relocs;
  540.         struct radeon_cs_reloc  **relocs_ptr;
  541.         struct list_head        validated;
  542.         /* indices of various chunks */
  543.         int                     chunk_ib_idx;
  544.         int                     chunk_relocs_idx;
  545.         struct radeon_ib        *ib;
  546.         void                    *track;
  547.         unsigned                family;
  548.         int parser_error;
  549. };
  550.  
  551. extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
  552. extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
  553.  
  554.  
  555. static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
  556. {
  557.         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  558.         u32 pg_idx, pg_offset;
  559.         u32 idx_value = 0;
  560.         int new_page;
  561.  
  562.         pg_idx = (idx * 4) / PAGE_SIZE;
  563.         pg_offset = (idx * 4) % PAGE_SIZE;
  564.  
  565.         if (ibc->kpage_idx[0] == pg_idx)
  566.                 return ibc->kpage[0][pg_offset/4];
  567.         if (ibc->kpage_idx[1] == pg_idx)
  568.                 return ibc->kpage[1][pg_offset/4];
  569.  
  570.         new_page = radeon_cs_update_pages(p, pg_idx);
  571.         if (new_page < 0) {
  572.                 p->parser_error = new_page;
  573.                 return 0;
  574.         }
  575.  
  576.         idx_value = ibc->kpage[new_page][pg_offset/4];
  577.         return idx_value;
  578. }
  579.  
  580. struct radeon_cs_packet {
  581.         unsigned        idx;
  582.         unsigned        type;
  583.         unsigned        reg;
  584.         unsigned        opcode;
  585.         int             count;
  586.         unsigned        one_reg_wr;
  587. };
  588.  
  589. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  590.                                       struct radeon_cs_packet *pkt,
  591.                                       unsigned idx, unsigned reg);
  592. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  593.                                       struct radeon_cs_packet *pkt);
  594.  
  595.  
  596. /*
  597.  * AGP
  598.  */
  599. int radeon_agp_init(struct radeon_device *rdev);
  600. void radeon_agp_resume(struct radeon_device *rdev);
  601. void radeon_agp_fini(struct radeon_device *rdev);
  602.  
  603.  
  604. /*
  605.  * Writeback
  606.  */
  607. struct radeon_wb {
  608.         struct radeon_bo        *wb_obj;
  609.         volatile uint32_t       *wb;
  610.         uint64_t                gpu_addr;
  611. };
  612.  
  613. /**
  614.  * struct radeon_pm - power management datas
  615.  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
  616.  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
  617.  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
  618.  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
  619.  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
  620.  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
  621.  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
  622.  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
  623.  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
  624.  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
  625.  * @needed_bandwidth:   current bandwidth needs
  626.  *
  627.  * It keeps track of various data needed to take powermanagement decision.
  628.  * Bandwith need is used to determine minimun clock of the GPU and memory.
  629.  * Equation between gpu/memory clock and available bandwidth is hw dependent
  630.  * (type of memory, bus size, efficiency, ...)
  631.  */
  632. struct radeon_pm {
  633.         fixed20_12              max_bandwidth;
  634.         fixed20_12              igp_sideport_mclk;
  635.         fixed20_12              igp_system_mclk;
  636.         fixed20_12              igp_ht_link_clk;
  637.         fixed20_12              igp_ht_link_width;
  638.         fixed20_12              k8_bandwidth;
  639.         fixed20_12              sideport_bandwidth;
  640.         fixed20_12              ht_bandwidth;
  641.         fixed20_12              core_bandwidth;
  642.         fixed20_12              sclk;
  643.         fixed20_12              needed_bandwidth;
  644. };
  645.  
  646. /*
  647.  * ASIC specific functions.
  648.  */
  649. struct radeon_asic {
  650.         int (*init)(struct radeon_device *rdev);
  651.         void (*fini)(struct radeon_device *rdev);
  652.         int (*resume)(struct radeon_device *rdev);
  653.         int (*suspend)(struct radeon_device *rdev);
  654.         void (*vga_set_state)(struct radeon_device *rdev, bool state);
  655.         int (*gpu_reset)(struct radeon_device *rdev);
  656.         void (*gart_tlb_flush)(struct radeon_device *rdev);
  657.         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  658.         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
  659.         void (*cp_fini)(struct radeon_device *rdev);
  660.         void (*cp_disable)(struct radeon_device *rdev);
  661.         void (*cp_commit)(struct radeon_device *rdev);
  662.         void (*ring_start)(struct radeon_device *rdev);
  663.         int (*ring_test)(struct radeon_device *rdev);
  664.         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
  665.         int (*irq_set)(struct radeon_device *rdev);
  666.         int (*irq_process)(struct radeon_device *rdev);
  667.         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
  668.         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
  669.         int (*cs_parse)(struct radeon_cs_parser *p);
  670.         int (*copy_blit)(struct radeon_device *rdev,
  671.                          uint64_t src_offset,
  672.                          uint64_t dst_offset,
  673.                          unsigned num_pages,
  674.                          struct radeon_fence *fence);
  675.         int (*copy_dma)(struct radeon_device *rdev,
  676.                         uint64_t src_offset,
  677.                         uint64_t dst_offset,
  678.                         unsigned num_pages,
  679.                         struct radeon_fence *fence);
  680.         int (*copy)(struct radeon_device *rdev,
  681.                     uint64_t src_offset,
  682.                     uint64_t dst_offset,
  683.                     unsigned num_pages,
  684.                     struct radeon_fence *fence);
  685.         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
  686.         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  687.         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
  688.         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  689.         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  690.         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  691.         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
  692.                                uint32_t tiling_flags, uint32_t pitch,
  693.                                uint32_t offset, uint32_t obj_size);
  694.         int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
  695.         void (*bandwidth_update)(struct radeon_device *rdev);
  696.         void (*hpd_init)(struct radeon_device *rdev);
  697.         void (*hpd_fini)(struct radeon_device *rdev);
  698.         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  699.         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
  700. };
  701.  
  702. /*
  703.  * Asic structures
  704.  */
  705. struct r100_asic {
  706.         const unsigned  *reg_safe_bm;
  707.         unsigned        reg_safe_bm_size;
  708.         u32             hdp_cntl;
  709. };
  710.  
  711. struct r300_asic {
  712.         const unsigned  *reg_safe_bm;
  713.         unsigned        reg_safe_bm_size;
  714.         u32             resync_scratch;
  715.         u32             hdp_cntl;
  716. };
  717.  
  718. struct r600_asic {
  719.         unsigned max_pipes;
  720.         unsigned max_tile_pipes;
  721.         unsigned max_simds;
  722.         unsigned max_backends;
  723.         unsigned max_gprs;
  724.         unsigned max_threads;
  725.         unsigned max_stack_entries;
  726.         unsigned max_hw_contexts;
  727.         unsigned max_gs_threads;
  728.         unsigned sx_max_export_size;
  729.         unsigned sx_max_export_pos_size;
  730.         unsigned sx_max_export_smx_size;
  731.         unsigned sq_num_cf_insts;
  732. };
  733.  
  734. struct rv770_asic {
  735.         unsigned max_pipes;
  736.         unsigned max_tile_pipes;
  737.         unsigned max_simds;
  738.         unsigned max_backends;
  739.         unsigned max_gprs;
  740.         unsigned max_threads;
  741.         unsigned max_stack_entries;
  742.         unsigned max_hw_contexts;
  743.         unsigned max_gs_threads;
  744.         unsigned sx_max_export_size;
  745.         unsigned sx_max_export_pos_size;
  746.         unsigned sx_max_export_smx_size;
  747.         unsigned sq_num_cf_insts;
  748.         unsigned sx_num_of_sets;
  749.         unsigned sc_prim_fifo_size;
  750.         unsigned sc_hiz_tile_fifo_size;
  751.         unsigned sc_earlyz_tile_fifo_fize;
  752. };
  753.  
  754. union radeon_asic_config {
  755.         struct r300_asic        r300;
  756.         struct r100_asic        r100;
  757.         struct r600_asic        r600;
  758.         struct rv770_asic       rv770;
  759. };
  760.  
  761.  
  762. /*
  763.  
  764.  
  765.  
  766.  
  767. /*
  768.  * Core structure, functions and helpers.
  769.  */
  770. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  771. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  772.  
  773. struct radeon_device {
  774.         void                               *dev;
  775.     struct drm_device          *ddev;
  776.     struct pci_dev             *pdev;
  777.     /* ASIC */
  778.     union radeon_asic_config    config;
  779.     enum radeon_family          family;
  780.     unsigned long               flags;
  781.     int                         usec_timeout;
  782.     enum radeon_pll_errata      pll_errata;
  783.     int                         num_gb_pipes;
  784.         int                             num_z_pipes;
  785.     int                         disp_priority;
  786.     /* BIOS */
  787.     uint8_t                     *bios;
  788.     bool                        is_atom_bios;
  789.     uint16_t                    bios_header_start;
  790.         struct radeon_bo                *stollen_vga_memory;
  791.     struct fb_info              *fbdev_info;
  792.         struct radeon_bo                *fbdev_rbo;
  793.     struct radeon_framebuffer   *fbdev_rfb;
  794.     /* Register mmio */
  795.     unsigned long               rmmio_base;
  796.     unsigned long               rmmio_size;
  797.     void                       *rmmio;
  798.     radeon_rreg_t               mc_rreg;
  799.     radeon_wreg_t               mc_wreg;
  800.     radeon_rreg_t               pll_rreg;
  801.     radeon_wreg_t               pll_wreg;
  802.         uint32_t                        pcie_reg_mask;
  803.     radeon_rreg_t               pciep_rreg;
  804.     radeon_wreg_t               pciep_wreg;
  805.     struct radeon_clock         clock;
  806.     struct radeon_mc            mc;
  807.     struct radeon_gart          gart;
  808.         struct radeon_mode_info         mode_info;
  809.     struct radeon_scratch       scratch;
  810.     struct radeon_mman          mman;
  811.         struct radeon_fence_driver      fence_drv;
  812.     struct radeon_cp            cp;
  813.     struct radeon_ib_pool       ib_pool;
  814. //    struct radeon_irq       irq;
  815.     struct radeon_asic         *asic;
  816.     struct radeon_gem       gem;
  817.         struct radeon_pm                pm;
  818.         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
  819. //    struct mutex            cs_mutex;
  820.     struct radeon_wb        wb;
  821.         struct radeon_dummy_page        dummy_page;
  822.     bool                gpu_lockup;
  823.     bool                shutdown;
  824.     bool                suspend;
  825.         bool                            need_dma32;
  826.         bool                            accel_working;
  827.         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
  828.         const struct firmware *me_fw;   /* all family ME firmware */
  829.         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
  830.         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
  831.         struct r600_blit r600_blit;
  832.         int msi_enabled; /* msi enabled */
  833.  
  834.         /* audio stuff */
  835. //   struct timer_list   audio_timer;
  836.         int                     audio_channels;
  837.         int                     audio_rate;
  838.         int                     audio_bits_per_sample;
  839.         uint8_t                 audio_status_bits;
  840.         uint8_t                 audio_category_code;
  841. };
  842.  
  843. int radeon_device_init(struct radeon_device *rdev,
  844.                        struct drm_device *ddev,
  845.                        struct pci_dev *pdev,
  846.                        uint32_t flags);
  847. void radeon_device_fini(struct radeon_device *rdev);
  848. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  849.  
  850. /* r600 blit */
  851. int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
  852. void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
  853. void r600_kms_blit_copy(struct radeon_device *rdev,
  854.                         u64 src_gpu_addr, u64 dst_gpu_addr,
  855.                         int size_bytes);
  856.  
  857. static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
  858. {
  859.         if (reg < rdev->rmmio_size)
  860.                 return readl(((void __iomem *)rdev->rmmio) + reg);
  861.         else {
  862.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  863.                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  864.         }
  865. }
  866.  
  867. static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  868. {
  869.         if (reg < rdev->rmmio_size)
  870.                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
  871.         else {
  872.                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  873.                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  874.         }
  875. }
  876.  
  877. /*
  878.  * Cast helper
  879.  */
  880. #define to_radeon_fence(p) ((struct radeon_fence *)(p))
  881.  
  882. /*
  883.  * Registers read & write functions.
  884.  */
  885. #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
  886. #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
  887. #define RREG32(reg) r100_mm_rreg(rdev, (reg))
  888. #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
  889. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  890. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  891. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  892. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  893. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  894. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  895. #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
  896. #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
  897. #define WREG32_P(reg, val, mask)                                \
  898.         do {                                                    \
  899.                 uint32_t tmp_ = RREG32(reg);                    \
  900.                 tmp_ &= (mask);                                 \
  901.                 tmp_ |= ((val) & ~(mask));                      \
  902.                 WREG32(reg, tmp_);                              \
  903.         } while (0)
  904. #define WREG32_PLL_P(reg, val, mask)                            \
  905.         do {                                                    \
  906.                 uint32_t tmp_ = RREG32_PLL(reg);                \
  907.                 tmp_ &= (mask);                                 \
  908.                 tmp_ |= ((val) & ~(mask));                      \
  909.                 WREG32_PLL(reg, tmp_);                          \
  910.         } while (0)
  911.  
  912. /*
  913.  * Indirect registers accessor
  914.  */
  915. static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  916. {
  917.         uint32_t r;
  918.  
  919.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  920.         r = RREG32(RADEON_PCIE_DATA);
  921.         return r;
  922. }
  923.  
  924. static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  925. {
  926.         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  927.         WREG32(RADEON_PCIE_DATA, (v));
  928. }
  929.  
  930. void r100_pll_errata_after_index(struct radeon_device *rdev);
  931.  
  932.  
  933. /*
  934.  * ASICs helpers.
  935.  */
  936. #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
  937.                             (rdev->pdev->device == 0x5969))
  938. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  939.         (rdev->family == CHIP_RV200) || \
  940.         (rdev->family == CHIP_RS100) || \
  941.         (rdev->family == CHIP_RS200) || \
  942.         (rdev->family == CHIP_RV250) || \
  943.         (rdev->family == CHIP_RV280) || \
  944.         (rdev->family == CHIP_RS300))
  945. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
  946.         (rdev->family == CHIP_RV350) ||         \
  947.         (rdev->family == CHIP_R350)  ||         \
  948.         (rdev->family == CHIP_RV380) ||         \
  949.         (rdev->family == CHIP_R420)  ||         \
  950.         (rdev->family == CHIP_R423)  ||         \
  951.         (rdev->family == CHIP_RV410) ||         \
  952.         (rdev->family == CHIP_RS400) ||         \
  953.         (rdev->family == CHIP_RS480))
  954. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  955. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  956. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  957.  
  958.  
  959. /*
  960.  * BIOS helpers.
  961.  */
  962. #define RBIOS8(i) (rdev->bios[i])
  963. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  964. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  965.  
  966. int radeon_combios_init(struct radeon_device *rdev);
  967. void radeon_combios_fini(struct radeon_device *rdev);
  968. int radeon_atombios_init(struct radeon_device *rdev);
  969. void radeon_atombios_fini(struct radeon_device *rdev);
  970.  
  971.  
  972. /*
  973.  * RING helpers.
  974.  */
  975. static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  976. {
  977. #if DRM_DEBUG_CODE
  978.         if (rdev->cp.count_dw <= 0) {
  979.                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  980.         }
  981. #endif
  982.         rdev->cp.ring[rdev->cp.wptr++] = v;
  983.         rdev->cp.wptr &= rdev->cp.ptr_mask;
  984.         rdev->cp.count_dw--;
  985.         rdev->cp.ring_free_dw--;
  986. }
  987.  
  988.  
  989. /*
  990.  * ASICs macro.
  991.  */
  992. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  993. #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
  994. #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
  995. #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
  996. #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
  997. #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
  998. #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
  999. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
  1000. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
  1001. #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
  1002. #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
  1003. #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
  1004. #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
  1005. #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
  1006. #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
  1007. #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
  1008. #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
  1009. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
  1010. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
  1011. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
  1012. #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
  1013. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  1014. #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
  1015. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
  1016. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
  1017. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
  1018. #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
  1019. #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
  1020. #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
  1021. #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
  1022. #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
  1023. #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
  1024. #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
  1025.  
  1026. /* Common functions */
  1027. /* AGP */
  1028. extern void radeon_agp_disable(struct radeon_device *rdev);
  1029. extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
  1030. extern int radeon_modeset_init(struct radeon_device *rdev);
  1031. extern void radeon_modeset_fini(struct radeon_device *rdev);
  1032. extern bool radeon_card_posted(struct radeon_device *rdev);
  1033. extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
  1034. extern int radeon_clocks_init(struct radeon_device *rdev);
  1035. extern void radeon_clocks_fini(struct radeon_device *rdev);
  1036. extern void radeon_scratch_init(struct radeon_device *rdev);
  1037. extern void radeon_surface_init(struct radeon_device *rdev);
  1038. extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
  1039. extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  1040. extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  1041. extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
  1042. extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
  1043.  
  1044. /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
  1045. struct r100_mc_save {
  1046.         u32     GENMO_WT;
  1047.         u32     CRTC_EXT_CNTL;
  1048.         u32     CRTC_GEN_CNTL;
  1049.         u32     CRTC2_GEN_CNTL;
  1050.         u32     CUR_OFFSET;
  1051.         u32     CUR2_OFFSET;
  1052. };
  1053. extern void r100_cp_disable(struct radeon_device *rdev);
  1054. extern int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
  1055. extern void r100_cp_fini(struct radeon_device *rdev);
  1056. extern void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  1057. extern int r100_pci_gart_init(struct radeon_device *rdev);
  1058. extern void r100_pci_gart_fini(struct radeon_device *rdev);
  1059. extern int r100_pci_gart_enable(struct radeon_device *rdev);
  1060. extern void r100_pci_gart_disable(struct radeon_device *rdev);
  1061. extern int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
  1062. extern int r100_debugfs_mc_info_init(struct radeon_device *rdev);
  1063. extern int r100_gui_wait_for_idle(struct radeon_device *rdev);
  1064. extern void r100_ib_fini(struct radeon_device *rdev);
  1065. extern int r100_ib_init(struct radeon_device *rdev);
  1066. extern void r100_irq_disable(struct radeon_device *rdev);
  1067. extern int r100_irq_set(struct radeon_device *rdev);
  1068. extern void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
  1069. extern void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
  1070. extern void r100_vram_init_sizes(struct radeon_device *rdev);
  1071. extern void r100_wb_disable(struct radeon_device *rdev);
  1072. extern void r100_wb_fini(struct radeon_device *rdev);
  1073. extern int r100_wb_init(struct radeon_device *rdev);
  1074. extern void r100_hdp_reset(struct radeon_device *rdev);
  1075. extern int r100_rb2d_reset(struct radeon_device *rdev);
  1076. extern int r100_cp_reset(struct radeon_device *rdev);
  1077. extern void r100_vga_render_disable(struct radeon_device *rdev);
  1078. extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  1079.                                                 struct radeon_cs_packet *pkt,
  1080.                                                 struct radeon_bo *robj);
  1081. extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  1082.                                 struct radeon_cs_packet *pkt,
  1083.                                 const unsigned *auth, unsigned n,
  1084.                                 radeon_packet0_check_t check);
  1085. extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
  1086.                                 struct radeon_cs_packet *pkt,
  1087.                                 unsigned idx);
  1088. extern void r100_enable_bm(struct radeon_device *rdev);
  1089. extern void r100_set_common_regs(struct radeon_device *rdev);
  1090.  
  1091. /* rv200,rv250,rv280 */
  1092. extern void r200_set_safe_registers(struct radeon_device *rdev);
  1093.  
  1094. /* r300,r350,rv350,rv370,rv380 */
  1095. extern void r300_set_reg_safe(struct radeon_device *rdev);
  1096. extern void r300_mc_program(struct radeon_device *rdev);
  1097. extern void r300_vram_info(struct radeon_device *rdev);
  1098. extern void r300_clock_startup(struct radeon_device *rdev);
  1099. extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
  1100. extern int rv370_pcie_gart_init(struct radeon_device *rdev);
  1101. extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
  1102. extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
  1103. extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
  1104.  
  1105. /* r420,r423,rv410 */
  1106. extern int r420_mc_init(struct radeon_device *rdev);
  1107. extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
  1108. extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
  1109. extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
  1110. extern void r420_pipes_init(struct radeon_device *rdev);
  1111.  
  1112. /* rv515 */
  1113. struct rv515_mc_save {
  1114.         u32 d1vga_control;
  1115.         u32 d2vga_control;
  1116.         u32 vga_render_control;
  1117.         u32 vga_hdp_control;
  1118.         u32 d1crtc_control;
  1119.         u32 d2crtc_control;
  1120. };
  1121. extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
  1122. extern void rv515_vga_render_disable(struct radeon_device *rdev);
  1123. extern void rv515_set_safe_registers(struct radeon_device *rdev);
  1124. extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
  1125. extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
  1126. extern void rv515_clock_startup(struct radeon_device *rdev);
  1127. extern void rv515_debugfs(struct radeon_device *rdev);
  1128. extern int rv515_suspend(struct radeon_device *rdev);
  1129.  
  1130. /* rs400 */
  1131. extern int rs400_gart_init(struct radeon_device *rdev);
  1132. extern int rs400_gart_enable(struct radeon_device *rdev);
  1133. extern void rs400_gart_adjust_size(struct radeon_device *rdev);
  1134. extern void rs400_gart_disable(struct radeon_device *rdev);
  1135. extern void rs400_gart_fini(struct radeon_device *rdev);
  1136.  
  1137. /* rs600 */
  1138. extern void rs600_set_safe_registers(struct radeon_device *rdev);
  1139. extern int rs600_irq_set(struct radeon_device *rdev);
  1140. extern void rs600_irq_disable(struct radeon_device *rdev);
  1141.  
  1142. /* rs690, rs740 */
  1143. extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
  1144.                                         struct drm_display_mode *mode1,
  1145.                                         struct drm_display_mode *mode2);
  1146.  
  1147. /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
  1148. extern bool r600_card_posted(struct radeon_device *rdev);
  1149. extern void r600_cp_stop(struct radeon_device *rdev);
  1150. extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1151. extern int r600_cp_resume(struct radeon_device *rdev);
  1152. extern int r600_count_pipe_bits(uint32_t val);
  1153. extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
  1154. extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
  1155. extern int r600_pcie_gart_init(struct radeon_device *rdev);
  1156. extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
  1157. extern int r600_ib_test(struct radeon_device *rdev);
  1158. extern int r600_ring_test(struct radeon_device *rdev);
  1159. extern void r600_wb_fini(struct radeon_device *rdev);
  1160. extern int r600_wb_enable(struct radeon_device *rdev);
  1161. extern void r600_wb_disable(struct radeon_device *rdev);
  1162. extern void r600_scratch_init(struct radeon_device *rdev);
  1163. extern int r600_blit_init(struct radeon_device *rdev);
  1164. extern void r600_blit_fini(struct radeon_device *rdev);
  1165. extern int r600_init_microcode(struct radeon_device *rdev);
  1166. extern int r600_gpu_reset(struct radeon_device *rdev);
  1167. /* r600 irq */
  1168. extern int r600_irq_init(struct radeon_device *rdev);
  1169. extern void r600_irq_fini(struct radeon_device *rdev);
  1170. extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
  1171. extern int r600_irq_set(struct radeon_device *rdev);
  1172. extern void r600_irq_suspend(struct radeon_device *rdev);
  1173. /* r600 audio */
  1174. extern int r600_audio_init(struct radeon_device *rdev);
  1175. extern int r600_audio_tmds_index(struct drm_encoder *encoder);
  1176. extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
  1177. extern void r600_audio_fini(struct radeon_device *rdev);
  1178. extern void r600_hdmi_init(struct drm_encoder *encoder);
  1179. extern void r600_hdmi_enable(struct drm_encoder *encoder, int enable);
  1180. extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
  1181. extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
  1182. extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
  1183.                                             int channels,
  1184.                                             int rate,
  1185.                                             int bps,
  1186.                                             uint8_t status_bits,
  1187.                                             uint8_t category_code);
  1188.  
  1189. #include "radeon_object.h"
  1190.  
  1191. #define DRM_UDELAY(d)           udelay(d)
  1192.  
  1193. resource_size_t
  1194. drm_get_resource_start(struct drm_device *dev, unsigned int resource);
  1195. resource_size_t
  1196. drm_get_resource_len(struct drm_device *dev, unsigned int resource);
  1197.  
  1198. bool set_mode(struct drm_device *dev, struct drm_connector *connector,
  1199.               videomode_t *mode, bool strict);
  1200.  
  1201.  
  1202. #endif
  1203.