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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #ifndef __RADEON_H__
  29. #define __RADEON_H__
  30.  
  31. //#include "radeon_object.h"
  32.  
  33. /* TODO: Here are things that needs to be done :
  34.  *      - surface allocator & initializer : (bit like scratch reg) should
  35.  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  36.  *        related to surface
  37.  *      - WB : write back stuff (do it bit like scratch reg things)
  38.  *      - Vblank : look at Jesse's rework and what we should do
  39.  *      - r600/r700: gart & cp
  40.  *      - cs : clean cs ioctl use bitmap & things like that.
  41.  *      - power management stuff
  42.  *      - Barrier in gart code
  43.  *      - Unmappabled vram ?
  44.  *      - TESTING, TESTING, TESTING
  45.  */
  46.  
  47. #include <types.h>
  48. #include <list.h>
  49.  
  50. #include <pci.h>
  51.  
  52. #include <errno-base.h>
  53. #include "drm_edid.h"
  54. #include "radeon_mode.h"
  55. #include "radeon_reg.h"
  56. #include "r300.h"
  57.  
  58. #include <syscall.h>
  59.  
  60. extern int radeon_modeset;
  61. extern int radeon_dynclks;
  62. extern int radeon_r4xx_atom;
  63. extern int radeon_agpmode;
  64. extern int radeon_vram_limit;
  65. extern int radeon_gart_size;
  66. extern int radeon_benchmarking;
  67. extern int radeon_connector_table;
  68.  
  69. /*
  70.  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  71.  * symbol;
  72.  */
  73. #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
  74. #define RADEON_IB_POOL_SIZE             16
  75. #define RADEON_DEBUGFS_MAX_NUM_FILES    32
  76. #define RADEONFB_CONN_LIMIT             4
  77.  
  78. enum radeon_family {
  79.     CHIP_R100,
  80.     CHIP_RV100,
  81.     CHIP_RS100,
  82.     CHIP_RV200,
  83.     CHIP_RS200,
  84.     CHIP_R200,
  85.     CHIP_RV250,
  86.     CHIP_RS300,
  87.     CHIP_RV280,
  88.     CHIP_R300,
  89.     CHIP_R350,
  90.     CHIP_RV350,
  91.     CHIP_RV380,
  92.     CHIP_R420,
  93.     CHIP_R423,
  94.     CHIP_RV410,
  95.     CHIP_RS400,
  96.     CHIP_RS480,
  97.     CHIP_RS600,
  98.     CHIP_RS690,
  99.     CHIP_RS740,
  100.     CHIP_RV515,
  101.     CHIP_R520,
  102.     CHIP_RV530,
  103.     CHIP_RV560,
  104.     CHIP_RV570,
  105.     CHIP_R580,
  106.     CHIP_R600,
  107.     CHIP_RV610,
  108.     CHIP_RV630,
  109.     CHIP_RV620,
  110.     CHIP_RV635,
  111.     CHIP_RV670,
  112.     CHIP_RS780,
  113.     CHIP_RV770,
  114.     CHIP_RV730,
  115.     CHIP_RV710,
  116.     CHIP_LAST,
  117. };
  118.  
  119. enum radeon_chip_flags {
  120.     RADEON_FAMILY_MASK = 0x0000ffffUL,
  121.     RADEON_FLAGS_MASK = 0xffff0000UL,
  122.     RADEON_IS_MOBILITY = 0x00010000UL,
  123.     RADEON_IS_IGP = 0x00020000UL,
  124.     RADEON_SINGLE_CRTC = 0x00040000UL,
  125.     RADEON_IS_AGP = 0x00080000UL,
  126.     RADEON_HAS_HIERZ = 0x00100000UL,
  127.     RADEON_IS_PCIE = 0x00200000UL,
  128.     RADEON_NEW_MEMMAP = 0x00400000UL,
  129.     RADEON_IS_PCI = 0x00800000UL,
  130.     RADEON_IS_IGPGART = 0x01000000UL,
  131. };
  132.  
  133.  
  134. /*
  135.  * Errata workarounds.
  136.  */
  137. enum radeon_pll_errata {
  138.     CHIP_ERRATA_R300_CG             = 0x00000001,
  139.     CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  140.     CHIP_ERRATA_PLL_DELAY           = 0x00000004
  141. };
  142.  
  143.  
  144. struct radeon_device;
  145.  
  146.  
  147. /*
  148.  * BIOS.
  149.  */
  150. bool radeon_get_bios(struct radeon_device *rdev);
  151.  
  152. /*
  153.  * Clocks
  154.  */
  155.  
  156. struct radeon_clock {
  157.         struct radeon_pll p1pll;
  158.         struct radeon_pll p2pll;
  159.         struct radeon_pll spll;
  160.         struct radeon_pll mpll;
  161.         /* 10 Khz units */
  162.         uint32_t default_mclk;
  163.         uint32_t default_sclk;
  164. };
  165.  
  166. /*
  167.  * Fences.
  168.  */
  169. struct radeon_fence_driver {
  170.         uint32_t                        scratch_reg;
  171. //      atomic_t                        seq;
  172.         uint32_t                        last_seq;
  173.         unsigned long                   count_timeout;
  174. //      wait_queue_head_t               queue;
  175. //      rwlock_t                        lock;
  176.         struct list_head                created;
  177.         struct list_head                emited;
  178.         struct list_head                signaled;
  179. };
  180.  
  181. struct radeon_fence {
  182.         struct radeon_device            *rdev;
  183. //      struct kref                     kref;
  184.         struct list_head                list;
  185.         /* protected by radeon_fence.lock */
  186.         uint32_t                        seq;
  187.         unsigned long                   timeout;
  188.         bool                            emited;
  189.         bool                            signaled;
  190. };
  191.  
  192. int radeon_fence_driver_init(struct radeon_device *rdev);
  193. void radeon_fence_driver_fini(struct radeon_device *rdev);
  194. int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
  195. int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
  196. void radeon_fence_process(struct radeon_device *rdev);
  197. bool radeon_fence_signaled(struct radeon_fence *fence);
  198. int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
  199. int radeon_fence_wait_next(struct radeon_device *rdev);
  200. int radeon_fence_wait_last(struct radeon_device *rdev);
  201. struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
  202. void radeon_fence_unref(struct radeon_fence **fence);
  203.  
  204.  
  205. /*
  206.  * Radeon buffer.
  207.  */
  208. struct radeon_object;
  209.  
  210. struct radeon_object_list {
  211.         struct list_head        list;
  212.         struct radeon_object    *robj;
  213.         uint64_t                gpu_offset;
  214.         unsigned                rdomain;
  215.         unsigned                wdomain;
  216. };
  217.  
  218. int radeon_object_init(struct radeon_device *rdev);
  219. void radeon_object_fini(struct radeon_device *rdev);
  220. int radeon_object_create(struct radeon_device *rdev,
  221.                          struct drm_gem_object *gobj,
  222.                          unsigned long size,
  223.                          bool kernel,
  224.                          uint32_t domain,
  225.                          bool interruptible,
  226.                          struct radeon_object **robj_ptr);
  227.  
  228.  
  229. /*
  230.  * GEM objects.
  231.  */
  232. struct radeon_gem {
  233.         struct list_head        objects;
  234. };
  235.  
  236. int radeon_gem_init(struct radeon_device *rdev);
  237. void radeon_gem_fini(struct radeon_device *rdev);
  238. int radeon_gem_object_create(struct radeon_device *rdev, int size,
  239.                              int alignment, int initial_domain,
  240.                              bool discardable, bool kernel,
  241.                              bool interruptible,
  242.                              struct drm_gem_object **obj);
  243. int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
  244.                           uint64_t *gpu_addr);
  245. void radeon_gem_object_unpin(struct drm_gem_object *obj);
  246.  
  247.  
  248. /*
  249.  * GART structures, functions & helpers
  250.  */
  251. struct radeon_mc;
  252.  
  253. struct radeon_gart_table_ram {
  254.     volatile uint32_t       *ptr;
  255. };
  256.  
  257. struct radeon_gart_table_vram {
  258.     struct radeon_object        *robj;
  259.     volatile uint32_t       *ptr;
  260. };
  261.  
  262. union radeon_gart_table {
  263.     struct radeon_gart_table_ram    ram;
  264.     struct radeon_gart_table_vram   vram;
  265. };
  266.  
  267. struct radeon_gart {
  268.     dma_addr_t          table_addr;
  269.     unsigned            num_gpu_pages;
  270.     unsigned            num_cpu_pages;
  271.     unsigned            table_size;
  272.     union radeon_gart_table     table;
  273.     struct page         **pages;
  274.     dma_addr_t          *pages_addr;
  275.     bool                ready;
  276. };
  277.  
  278. int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
  279. void radeon_gart_table_ram_free(struct radeon_device *rdev);
  280. int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
  281. void radeon_gart_table_vram_free(struct radeon_device *rdev);
  282. int radeon_gart_init(struct radeon_device *rdev);
  283. void radeon_gart_fini(struct radeon_device *rdev);
  284. void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
  285.                         int pages);
  286. int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
  287.             int pages, u32_t *pagelist);
  288.  
  289.  
  290. /*
  291.  * GPU MC structures, functions & helpers
  292.  */
  293. struct radeon_mc {
  294.     resource_size_t     aper_size;
  295.     resource_size_t     aper_base;
  296.     resource_size_t     agp_base;
  297.     unsigned            gtt_location;
  298.     unsigned            gtt_size;
  299.     unsigned            vram_location;
  300.     unsigned            vram_size;
  301.     unsigned            vram_width;
  302.     int                 vram_mtrr;
  303.     bool                vram_is_ddr;
  304. };
  305.  
  306. int radeon_mc_setup(struct radeon_device *rdev);
  307.  
  308.  
  309. /*
  310.  * GPU scratch registers structures, functions & helpers
  311.  */
  312. struct radeon_scratch {
  313.     unsigned        num_reg;
  314.     bool            free[32];
  315.     uint32_t        reg[32];
  316. };
  317.  
  318. int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
  319. void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
  320.  
  321.  
  322. /*
  323.  * IRQS.
  324.  */
  325. struct radeon_irq {
  326.         bool            installed;
  327.         bool            sw_int;
  328.         /* FIXME: use a define max crtc rather than hardcode it */
  329.         bool            crtc_vblank_int[2];
  330. };
  331.  
  332. int radeon_irq_kms_init(struct radeon_device *rdev);
  333. void radeon_irq_kms_fini(struct radeon_device *rdev);
  334.  
  335.  
  336. /*
  337.  * CP & ring.
  338.  */
  339. struct radeon_ib {
  340.         struct list_head        list;
  341.         unsigned long           idx;
  342.         uint64_t                gpu_addr;
  343.         struct radeon_fence     *fence;
  344.         volatile uint32_t       *ptr;
  345.         uint32_t                length_dw;
  346. };
  347.  
  348. struct radeon_ib_pool {
  349. //      struct mutex            mutex;
  350.         struct radeon_object    *robj;
  351.         struct list_head        scheduled_ibs;
  352.         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
  353.         bool                    ready;
  354.         DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
  355. };
  356.  
  357. struct radeon_cp {
  358.         struct radeon_object    *ring_obj;
  359.         volatile uint32_t       *ring;
  360.         unsigned                rptr;
  361.         unsigned                wptr;
  362.         unsigned                wptr_old;
  363.         unsigned                ring_size;
  364.         unsigned                ring_free_dw;
  365.         int                     count_dw;
  366.         uint64_t                gpu_addr;
  367.         uint32_t                align_mask;
  368.         uint32_t                ptr_mask;
  369. //      struct mutex            mutex;
  370.         bool                    ready;
  371. };
  372.  
  373. int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
  374. void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
  375. int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
  376. int radeon_ib_pool_init(struct radeon_device *rdev);
  377. void radeon_ib_pool_fini(struct radeon_device *rdev);
  378. int radeon_ib_test(struct radeon_device *rdev);
  379. /* Ring access between begin & end cannot sleep */
  380. void radeon_ring_free_size(struct radeon_device *rdev);
  381. int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
  382. void radeon_ring_unlock_commit(struct radeon_device *rdev);
  383. void radeon_ring_unlock_undo(struct radeon_device *rdev);
  384. int radeon_ring_test(struct radeon_device *rdev);
  385. int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
  386. void radeon_ring_fini(struct radeon_device *rdev);
  387.  
  388.  
  389. /*
  390.  * CS.
  391.  */
  392. struct radeon_cs_reloc {
  393. //      struct drm_gem_object           *gobj;
  394.         struct radeon_object            *robj;
  395.         struct radeon_object_list       lobj;
  396.         uint32_t                        handle;
  397.         uint32_t                        flags;
  398. };
  399.  
  400. struct radeon_cs_chunk {
  401.         uint32_t                chunk_id;
  402.         uint32_t                length_dw;
  403.         uint32_t                *kdata;
  404. };
  405.  
  406. struct radeon_cs_parser {
  407.         struct radeon_device    *rdev;
  408. //      struct drm_file         *filp;
  409.         /* chunks */
  410.         unsigned                nchunks;
  411.         struct radeon_cs_chunk  *chunks;
  412.         uint64_t                *chunks_array;
  413.         /* IB */
  414.         unsigned                idx;
  415.         /* relocations */
  416.         unsigned                nrelocs;
  417.         struct radeon_cs_reloc  *relocs;
  418.         struct radeon_cs_reloc  **relocs_ptr;
  419.         struct list_head        validated;
  420.         /* indices of various chunks */
  421.         int                     chunk_ib_idx;
  422.         int                     chunk_relocs_idx;
  423.         struct radeon_ib        *ib;
  424.         void                    *track;
  425. };
  426.  
  427. struct radeon_cs_packet {
  428.         unsigned        idx;
  429.         unsigned        type;
  430.         unsigned        reg;
  431.         unsigned        opcode;
  432.         int             count;
  433.         unsigned        one_reg_wr;
  434. };
  435.  
  436. typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
  437.                                       struct radeon_cs_packet *pkt,
  438.                                       unsigned idx, unsigned reg);
  439. typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
  440.                                       struct radeon_cs_packet *pkt);
  441.  
  442.  
  443. /*
  444.  * AGP
  445.  */
  446. int radeon_agp_init(struct radeon_device *rdev);
  447. void radeon_agp_fini(struct radeon_device *rdev);
  448.  
  449.  
  450. /*
  451.  * Writeback
  452.  */
  453. struct radeon_wb {
  454.         struct radeon_object    *wb_obj;
  455.         volatile uint32_t       *wb;
  456.         uint64_t                gpu_addr;
  457. };
  458.  
  459.  
  460. /*
  461.  * ASIC specific functions.
  462.  */
  463. struct radeon_asic {
  464.         int (*init)(struct radeon_device *rdev);
  465.         void (*errata)(struct radeon_device *rdev);
  466.         void (*vram_info)(struct radeon_device *rdev);
  467.         int (*gpu_reset)(struct radeon_device *rdev);
  468.         int (*mc_init)(struct radeon_device *rdev);
  469.         void (*mc_fini)(struct radeon_device *rdev);
  470.         int (*wb_init)(struct radeon_device *rdev);
  471.         void (*wb_fini)(struct radeon_device *rdev);
  472.         int (*gart_enable)(struct radeon_device *rdev);
  473.         void (*gart_disable)(struct radeon_device *rdev);
  474.         void (*gart_tlb_flush)(struct radeon_device *rdev);
  475.         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
  476.         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
  477.         void (*cp_fini)(struct radeon_device *rdev);
  478.         void (*cp_disable)(struct radeon_device *rdev);
  479.         void (*ring_start)(struct radeon_device *rdev);
  480.         int (*irq_set)(struct radeon_device *rdev);
  481.         int (*irq_process)(struct radeon_device *rdev);
  482.         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
  483.         int (*cs_parse)(struct radeon_cs_parser *p);
  484.         int (*copy_blit)(struct radeon_device *rdev,
  485.                          uint64_t src_offset,
  486.                          uint64_t dst_offset,
  487.                          unsigned num_pages,
  488.                          struct radeon_fence *fence);
  489.         int (*copy_dma)(struct radeon_device *rdev,
  490.                         uint64_t src_offset,
  491.                         uint64_t dst_offset,
  492.                         unsigned num_pages,
  493.                         struct radeon_fence *fence);
  494.         int (*copy)(struct radeon_device *rdev,
  495.                     uint64_t src_offset,
  496.                     uint64_t dst_offset,
  497.                     unsigned num_pages,
  498.                     struct radeon_fence *fence);
  499.         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
  500.         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
  501.         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
  502.         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
  503. };
  504.  
  505. union radeon_asic_config {
  506.         struct r300_asic        r300;
  507. };
  508.  
  509.  
  510. /*
  511. /*
  512.  * Core structure, functions and helpers.
  513.  */
  514. typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
  515. typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
  516.  
  517. struct radeon_device {
  518.     struct drm_device          *ddev;
  519.     struct pci_dev             *pdev;
  520.     /* ASIC */
  521.     union radeon_asic_config    config;
  522.     enum radeon_family          family;
  523.     unsigned long               flags;
  524.     int                         usec_timeout;
  525.     enum radeon_pll_errata      pll_errata;
  526.     int                         num_gb_pipes;
  527.     int                         disp_priority;
  528.     /* BIOS */
  529.     uint8_t                     *bios;
  530.     bool                        is_atom_bios;
  531.     uint16_t                    bios_header_start;
  532.  
  533. //    struct radeon_object        *stollen_vga_memory;
  534.     struct fb_info              *fbdev_info;
  535.     struct radeon_object        *fbdev_robj;
  536.     struct radeon_framebuffer   *fbdev_rfb;
  537.  
  538.     /* Register mmio */
  539.     unsigned long               rmmio_base;
  540.     unsigned long               rmmio_size;
  541.     void                       *rmmio;
  542.  
  543.     radeon_rreg_t               mm_rreg;
  544.     radeon_wreg_t               mm_wreg;
  545.     radeon_rreg_t               mc_rreg;
  546.     radeon_wreg_t               mc_wreg;
  547.     radeon_rreg_t               pll_rreg;
  548.     radeon_wreg_t               pll_wreg;
  549.     radeon_rreg_t               pcie_rreg;
  550.     radeon_wreg_t               pcie_wreg;
  551.     radeon_rreg_t               pciep_rreg;
  552.     radeon_wreg_t               pciep_wreg;
  553.     struct radeon_clock         clock;
  554.     struct radeon_mc            mc;
  555.     struct radeon_gart          gart;
  556.         struct radeon_mode_info         mode_info;
  557.     struct radeon_scratch       scratch;
  558. //    struct radeon_mman          mman;
  559.         struct radeon_fence_driver      fence_drv;
  560.     struct radeon_cp            cp;
  561.     struct radeon_ib_pool       ib_pool;
  562. //    struct radeon_irq       irq;
  563.     struct radeon_asic         *asic;
  564.     struct radeon_gem       gem;
  565. //    struct mutex            cs_mutex;
  566.     struct radeon_wb        wb;
  567.     bool                gpu_lockup;
  568.     bool                shutdown;
  569.     bool                suspend;
  570. };
  571.  
  572. int radeon_device_init(struct radeon_device *rdev,
  573.                        struct drm_device *ddev,
  574.                        struct pci_dev *pdev,
  575.                        uint32_t flags);
  576. void radeon_device_fini(struct radeon_device *rdev);
  577. int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
  578.  
  579. #define __iomem
  580. #define __force
  581.  
  582.  
  583.  
  584. static inline uint8_t __raw_readb(const volatile void __iomem *addr)
  585. {
  586.     return *(const volatile uint8_t __force *) addr;
  587. }
  588.  
  589. static inline uint16_t __raw_readw(const volatile void __iomem *addr)
  590. {
  591.     return *(const volatile uint16_t __force *) addr;
  592. }
  593.  
  594. static inline uint32_t __raw_readl(const volatile void __iomem *addr)
  595. {
  596.     return *(const volatile uint32_t __force *) addr;
  597. }
  598.  
  599. #define readb __raw_readb
  600. #define readw __raw_readw
  601. #define readl __raw_readl
  602.  
  603.  
  604.  
  605. static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr)
  606. {
  607.     *(volatile uint8_t __force *) addr = b;
  608. }
  609.  
  610. static inline void __raw_writew(uint16_t b, volatile void __iomem *addr)
  611. {
  612.     *(volatile uint16_t __force *) addr = b;
  613. }
  614.  
  615. static inline void __raw_writel(uint32_t b, volatile void __iomem *addr)
  616. {
  617.     *(volatile uint32_t __force *) addr = b;
  618. }
  619.  
  620. static inline void __raw_writeq(__u64 b, volatile void __iomem *addr)
  621. {
  622.         *(volatile __u64 *)addr = b;
  623. }
  624.  
  625. #define writeb __raw_writeb
  626. #define writew __raw_writew
  627. #define writel __raw_writel
  628. #define writeq __raw_writeq
  629.  
  630. //#define writeb(b,addr) *(volatile uint8_t* ) addr = (uint8_t)b
  631. //#define writew(b,addr) *(volatile uint16_t*) addr = (uint16_t)b
  632. //#define writel(b,addr) *(volatile uint32_t*) addr = (uint32_t)b
  633.  
  634.  
  635.  
  636. /*
  637.  * Registers read & write functions.
  638.  */
  639. #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
  640. #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
  641. #define RREG32(reg) rdev->mm_rreg(rdev, (reg))
  642. #define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v))
  643. #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  644. #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
  645. #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
  646. #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
  647. #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
  648. #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
  649. #define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg))
  650. #define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v))
  651. #define WREG32_P(reg, val, mask)                                \
  652.         do {                                                    \
  653.                 uint32_t tmp_ = RREG32(reg);                    \
  654.                 tmp_ &= (mask);                                 \
  655.                 tmp_ |= ((val) & ~(mask));                      \
  656.                 WREG32(reg, tmp_);                              \
  657.         } while (0)
  658. #define WREG32_PLL_P(reg, val, mask)                            \
  659.         do {                                                    \
  660.                 uint32_t tmp_ = RREG32_PLL(reg);                \
  661.                 tmp_ &= (mask);                                 \
  662.                 tmp_ |= ((val) & ~(mask));                      \
  663.                 WREG32_PLL(reg, tmp_);                          \
  664.         } while (0)
  665.  
  666.  
  667. #define radeon_PCI_IDS \
  668.     {0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
  669.     {0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  670.     {0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  671.     {0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
  672.     {0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
  673.     {0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP}, \
  674.     {0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \
  675.     {0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
  676.     {0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
  677.     {0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
  678.     {0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
  679.     {0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
  680.     {0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
  681.     {0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
  682.     {0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
  683.     {0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
  684.     {0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
  685.     {0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
  686.     {0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
  687.     {0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
  688.     {0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
  689.     {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
  690.     {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \
  691.     {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
  692.     {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
  693.     {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
  694.     {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
  695.     {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
  696.     {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
  697.     {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
  698.     {0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  699.     {0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  700.     {0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  701.     {0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  702.     {0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  703.     {0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  704.     {0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  705.     {0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  706.     {0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  707.     {0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  708.     {0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  709.     {0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  710.     {0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  711.     {0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
  712.     {0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \
  713.     {0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \
  714.     {0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \
  715.     {0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \
  716.     {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
  717.     {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
  718.     {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
  719.     {0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
  720.     {0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
  721.     {0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
  722.     {0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
  723.     {0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
  724.     {0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
  725.     {0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
  726.     {0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
  727.     {0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
  728.     {0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
  729.     {0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
  730.     {0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
  731.     {0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
  732.     {0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
  733.     {0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
  734.     {0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
  735.     {0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
  736.     {0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
  737.     {0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
  738.     {0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
  739.     {0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
  740.     {0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
  741.     {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
  742.     {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
  743.     {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
  744.     {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
  745.     {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
  746.     {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
  747.     {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
  748.     {0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
  749.     {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  750.     {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  751.     {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  752.     {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  753.     {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  754.     {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  755.     {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  756.     {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  757.     {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  758.     {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  759.     {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  760.     {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  761.     {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  762.     {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  763.     {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  764.     {0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  765.     {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  766.     {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \
  767.     {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
  768.     {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
  769.     {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
  770.     {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
  771.     {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
  772.     {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
  773.     {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
  774.     {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
  775.     {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
  776.     {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
  777.     {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
  778.     {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
  779.     {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
  780.     {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
  781.     {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
  782.     {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
  783.     {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
  784.     {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
  785.     {0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
  786.     {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
  787.     {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
  788.     {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
  789.     {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  790.     {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  791.     {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  792.     {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  793.     {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  794.     {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  795.     {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  796.     {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  797.     {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  798.     {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
  799.     {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
  800.     {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
  801.     {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
  802.     {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
  803.     {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
  804.     {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
  805.     {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
  806.     {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  807.     {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  808.     {0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  809.     {0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
  810.     {0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
  811.     {0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  812.     {0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
  813.     {0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
  814.     {0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
  815.     {0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
  816.     {0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
  817.     {0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
  818.     {0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
  819.     {0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  820.     {0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  821.     {0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  822.     {0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  823.     {0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  824.     {0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  825.     {0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  826.     {0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  827.     {0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  828.     {0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  829.     {0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  830.     {0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  831.     {0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  832.     {0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  833.     {0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  834.     {0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  835.     {0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  836.     {0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  837.     {0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  838.     {0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  839.     {0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  840.     {0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  841.     {0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  842.     {0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  843.     {0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  844.     {0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  845.     {0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  846.     {0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  847.     {0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  848.     {0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  849.     {0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  850.     {0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  851.     {0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  852.     {0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  853.     {0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  854.     {0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
  855.     {0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
  856.     {0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
  857.     {0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
  858.     {0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  859.     {0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  860.     {0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
  861.     {0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
  862.     {0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
  863.     {0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
  864.     {0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
  865.     {0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  866.     {0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  867.     {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  868.     {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
  869.     {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  870.     {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
  871.     {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  872.     {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  873.     {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  874.     {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  875.     {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  876.     {0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  877.     {0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  878.     {0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  879.     {0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  880.     {0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  881.     {0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  882.     {0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  883.     {0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  884.     {0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  885.     {0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  886.     {0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
  887.     {0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
  888.     {0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
  889.     {0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
  890.     {0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  891.     {0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
  892.     {0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
  893.     {0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
  894.     {0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
  895.     {0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
  896.     {0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
  897.     {0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
  898.     {0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
  899.     {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
  900.     {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
  901.     {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  902.     {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
  903.     {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
  904.     {0x1002, 0x793f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
  905.     {0x1002, 0x7941, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
  906.     {0x1002, 0x7942, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
  907.     {0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
  908.     {0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
  909.     {0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
  910.     {0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
  911.     {0x1002, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
  912.     {0x1002, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
  913.     {0x1002, 0x9402, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
  914.     {0x1002, 0x9403, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
  915.     {0x1002, 0x9405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
  916.     {0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
  917.     {0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
  918.     {0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
  919.     {0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  920.     {0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  921.     {0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  922.     {0x1002, 0x9444, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  923.     {0x1002, 0x9446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  924.     {0x1002, 0x944A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  925.     {0x1002, 0x944B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  926.     {0x1002, 0x944C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  927.     {0x1002, 0x944E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  928.     {0x1002, 0x9450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  929.     {0x1002, 0x9452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  930.     {0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  931.     {0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  932.     {0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  933.     {0x1002, 0x9460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  934.     {0x1002, 0x9462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
  935.     {0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  936.     {0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  937.     {0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  938.     {0x1002, 0x947B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  939.     {0x1002, 0x9480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  940.     {0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
  941.     {0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  942.     {0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  943.     {0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
  944.     {0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
  945.     {0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  946.     {0x1002, 0x9498, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
  947.     {0x1002, 0x949C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
  948.     {0x1002, 0x949E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
  949.     {0x1002, 0x949F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
  950.     {0x1002, 0x94C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
  951.     {0x1002, 0x94C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
  952.     {0x1002, 0x94C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
  953.     {0x1002, 0x94C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
  954.     {0x1002, 0x94C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
  955.     {0x1002, 0x94C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
  956.     {0x1002, 0x94C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
  957.     {0x1002, 0x94C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  958.     {0x1002, 0x94C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  959.     {0x1002, 0x94CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  960.     {0x1002, 0x94CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
  961.     {0x1002, 0x94CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
  962.     {0x1002, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
  963.     {0x1002, 0x9501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
  964.     {0x1002, 0x9504, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  965.     {0x1002, 0x9505, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
  966.     {0x1002, 0x9506, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  967.     {0x1002, 0x9507, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
  968.     {0x1002, 0x9508, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  969.     {0x1002, 0x9509, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  970.     {0x1002, 0x950F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
  971.     {0x1002, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
  972.     {0x1002, 0x9515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
  973.     {0x1002, 0x9517, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
  974.     {0x1002, 0x9519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
  975.     {0x1002, 0x9540, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
  976.     {0x1002, 0x9541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
  977.     {0x1002, 0x9542, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
  978.     {0x1002, 0x954E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
  979.     {0x1002, 0x954F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
  980.     {0x1002, 0x9552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  981.     {0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  982.     {0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  983.     {0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
  984.     {0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  985.     {0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  986.     {0x1002, 0x9586, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
  987.     {0x1002, 0x9587, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
  988.     {0x1002, 0x9588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
  989.     {0x1002, 0x9589, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
  990.     {0x1002, 0x958A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
  991.     {0x1002, 0x958B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  992.     {0x1002, 0x958C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
  993.     {0x1002, 0x958D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
  994.     {0x1002, 0x958E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
  995.     {0x1002, 0x958F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  996.     {0x1002, 0x9590, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
  997.     {0x1002, 0x9591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  998.     {0x1002, 0x9593, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  999.     {0x1002, 0x9595, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  1000.     {0x1002, 0x9596, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
  1001.     {0x1002, 0x9597, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
  1002.     {0x1002, 0x9598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
  1003.     {0x1002, 0x9599, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
  1004.     {0x1002, 0x959B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  1005.     {0x1002, 0x95C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
  1006.     {0x1002, 0x95C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
  1007.     {0x1002, 0x95C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
  1008.     {0x1002, 0x95C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
  1009.     {0x1002, 0x95C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
  1010.     {0x1002, 0x95C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  1011.     {0x1002, 0x95C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
  1012.     {0x1002, 0x95CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
  1013.     {0x1002, 0x95CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
  1014.     {0x1002, 0x95CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
  1015.     {0x1002, 0x95CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
  1016.     {0x1002, 0x9610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
  1017.     {0x1002, 0x9611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
  1018.     {0x1002, 0x9612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
  1019.     {0x1002, 0x9613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
  1020.     {0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
  1021.     {0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
  1022.     {0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
  1023.     {0, 0, 0}
  1024.  
  1025.  
  1026. enum chipset_type {
  1027.     NOT_SUPPORTED,
  1028.     SUPPORTED,
  1029. };
  1030.  
  1031. struct agp_version {
  1032.     u16_t major;
  1033.     u16_t minor;
  1034. };
  1035.  
  1036. struct agp_bridge_data;
  1037.  
  1038. struct agp_kern_info {
  1039.     struct agp_version version;
  1040.     struct pci_dev *device;
  1041.     enum chipset_type chipset;
  1042.     unsigned long mode;
  1043.     unsigned long aper_base;
  1044.     size_t aper_size;
  1045.     int max_memory;     /* In pages */
  1046.     int current_memory;
  1047.     bool cant_use_aperture;
  1048.     unsigned long page_mask;
  1049. //    struct vm_operations_struct *vm_ops;
  1050. };
  1051.  
  1052.  
  1053. /**
  1054.  * AGP data.
  1055.  *
  1056.  * \sa drm_agp_init() and drm_device::agp.
  1057.  */
  1058. struct drm_agp_head {
  1059.     struct agp_kern_info agp_info;      /**< AGP device information */
  1060. //    struct list_head memory;
  1061.     unsigned long mode;     /**< AGP mode */
  1062.     struct agp_bridge_data *bridge;
  1063.     int enabled;            /**< whether the AGP bus as been enabled */
  1064.     int acquired;           /**< whether the AGP device has been acquired */
  1065.     unsigned long base;
  1066.     int agp_mtrr;
  1067.     int cant_use_aperture;
  1068.     unsigned long page_mask;
  1069. };
  1070.  
  1071.  
  1072. #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
  1073.  
  1074.  
  1075. /*
  1076.  * ASICs helpers.
  1077.  */
  1078. #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
  1079.         (rdev->family == CHIP_RV200) || \
  1080.         (rdev->family == CHIP_RS100) || \
  1081.         (rdev->family == CHIP_RS200) || \
  1082.         (rdev->family == CHIP_RV250) || \
  1083.         (rdev->family == CHIP_RV280) || \
  1084.         (rdev->family == CHIP_RS300))
  1085. #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  || \
  1086.         (rdev->family == CHIP_RV350) ||         \
  1087.         (rdev->family == CHIP_R350)  ||         \
  1088.         (rdev->family == CHIP_RV380) ||         \
  1089.         (rdev->family == CHIP_R420)  ||         \
  1090.         (rdev->family == CHIP_R423)  ||         \
  1091.         (rdev->family == CHIP_RV410) ||         \
  1092.         (rdev->family == CHIP_RS400) ||         \
  1093.         (rdev->family == CHIP_RS480))
  1094. #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
  1095. #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
  1096. #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
  1097.  
  1098.  
  1099. /*
  1100.  * BIOS helpers.
  1101.  */
  1102. #define RBIOS8(i) (rdev->bios[i])
  1103. #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
  1104. #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
  1105.  
  1106. int radeon_combios_init(struct radeon_device *rdev);
  1107. void radeon_combios_fini(struct radeon_device *rdev);
  1108. int radeon_atombios_init(struct radeon_device *rdev);
  1109. void radeon_atombios_fini(struct radeon_device *rdev);
  1110.  
  1111.  
  1112. /*
  1113.  * RING helpers.
  1114.  */
  1115. #define CP_PACKET0                      0x00000000
  1116. #define         PACKET0_BASE_INDEX_SHIFT        0
  1117. #define         PACKET0_BASE_INDEX_MASK         (0x1ffff << 0)
  1118. #define         PACKET0_COUNT_SHIFT             16
  1119. #define         PACKET0_COUNT_MASK              (0x3fff << 16)
  1120. #define CP_PACKET1                      0x40000000
  1121. #define CP_PACKET2                      0x80000000
  1122. #define         PACKET2_PAD_SHIFT               0
  1123. #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
  1124. #define CP_PACKET3                      0xC0000000
  1125. #define         PACKET3_IT_OPCODE_SHIFT         8
  1126. #define         PACKET3_IT_OPCODE_MASK          (0xff << 8)
  1127. #define         PACKET3_COUNT_SHIFT             16
  1128. #define         PACKET3_COUNT_MASK              (0x3fff << 16)
  1129. /* PACKET3 op code */
  1130. #define         PACKET3_NOP                     0x10
  1131. #define         PACKET3_3D_DRAW_VBUF            0x28
  1132. #define         PACKET3_3D_DRAW_IMMD            0x29
  1133. #define         PACKET3_3D_DRAW_INDX            0x2A
  1134. #define         PACKET3_3D_LOAD_VBPNTR          0x2F
  1135. #define         PACKET3_INDX_BUFFER             0x33
  1136. #define         PACKET3_3D_DRAW_VBUF_2          0x34
  1137. #define         PACKET3_3D_DRAW_IMMD_2          0x35
  1138. #define         PACKET3_3D_DRAW_INDX_2          0x36
  1139. #define         PACKET3_BITBLT_MULTI            0x9B
  1140.  
  1141. #define PACKET0(reg, n) (CP_PACKET0 |                                   \
  1142.                          REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) |      \
  1143.                          REG_SET(PACKET0_COUNT, (n)))
  1144. #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
  1145. #define PACKET3(op, n)  (CP_PACKET3 |                                   \
  1146.                          REG_SET(PACKET3_IT_OPCODE, (op)) |             \
  1147.                          REG_SET(PACKET3_COUNT, (n)))
  1148.  
  1149. #define PACKET_TYPE0    0
  1150. #define PACKET_TYPE1    1
  1151. #define PACKET_TYPE2    2
  1152. #define PACKET_TYPE3    3
  1153.  
  1154. #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
  1155. #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
  1156. #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
  1157. #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
  1158. #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
  1159.  
  1160. static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
  1161. {
  1162. #if DRM_DEBUG_CODE
  1163.         if (rdev->cp.count_dw <= 0) {
  1164.                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
  1165.         }
  1166. #endif
  1167.         rdev->cp.ring[rdev->cp.wptr++] = v;
  1168.         rdev->cp.wptr &= rdev->cp.ptr_mask;
  1169.         rdev->cp.count_dw--;
  1170.         rdev->cp.ring_free_dw--;
  1171. }
  1172.  
  1173.  
  1174. /*
  1175.  * ASICs macro.
  1176.  */
  1177. #define radeon_init(rdev) (rdev)->asic->init((rdev))
  1178. #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
  1179. #define radeon_errata(rdev) (rdev)->asic->errata((rdev))
  1180. #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev))
  1181. #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev))
  1182. #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev))
  1183. #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev))
  1184. #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev))
  1185. #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev))
  1186. #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev))
  1187. #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev))
  1188. #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
  1189. #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
  1190. #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize))
  1191. #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev))
  1192. #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev))
  1193. #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
  1194. #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
  1195. #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
  1196. #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
  1197. #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
  1198. #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
  1199. #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
  1200. #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  1201. #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
  1202. #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
  1203. #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
  1204.  
  1205.  
  1206. #define DRM_UDELAY(d)           udelay(d)
  1207.  
  1208. resource_size_t
  1209. drm_get_resource_start(struct drm_device *dev, unsigned int resource);
  1210. resource_size_t
  1211. drm_get_resource_len(struct drm_device *dev, unsigned int resource);
  1212.  
  1213. bool set_mode(struct drm_device *dev, int width, int height);
  1214.  
  1215. #endif
  1216.