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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Christian König.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Christian König
  25.  */
  26. #include <linux/hdmi.h>
  27. #include <drm/drmP.h>
  28. #include <drm/radeon_drm.h>
  29. #include "radeon.h"
  30. #include "radeon_asic.h"
  31. #include "r600d.h"
  32. #include "atom.h"
  33.  
  34. /*
  35.  * HDMI color format
  36.  */
  37. enum r600_hdmi_color_format {
  38.         RGB = 0,
  39.         YCC_422 = 1,
  40.         YCC_444 = 2
  41. };
  42.  
  43. /*
  44.  * IEC60958 status bits
  45.  */
  46. enum r600_hdmi_iec_status_bits {
  47.         AUDIO_STATUS_DIG_ENABLE   = 0x01,
  48.         AUDIO_STATUS_V      = 0x02,
  49.         AUDIO_STATUS_VCFG        = 0x04,
  50.         AUDIO_STATUS_EMPHASIS     = 0x08,
  51.         AUDIO_STATUS_COPYRIGHT    = 0x10,
  52.         AUDIO_STATUS_NONAUDIO     = 0x20,
  53.         AUDIO_STATUS_PROFESSIONAL = 0x40,
  54.         AUDIO_STATUS_LEVEL      = 0x80
  55. };
  56.  
  57. static const struct radeon_hdmi_acr r600_hdmi_predefined_acr[] = {
  58.     /*       32kHz        44.1kHz       48kHz    */
  59.     /* Clock      N     CTS      N     CTS      N     CTS */
  60.     {  25175,  4096,  25175, 28224, 125875,  6144,  25175 }, /*  25,20/1.001 MHz */
  61.     {  25200,  4096,  25200,  6272,  28000,  6144,  25200 }, /*  25.20       MHz */
  62.     {  27000,  4096,  27000,  6272,  30000,  6144,  27000 }, /*  27.00       MHz */
  63.     {  27027,  4096,  27027,  6272,  30030,  6144,  27027 }, /*  27.00*1.001 MHz */
  64.     {  54000,  4096,  54000,  6272,  60000,  6144,  54000 }, /*  54.00       MHz */
  65.     {  54054,  4096,  54054,  6272,  60060,  6144,  54054 }, /*  54.00*1.001 MHz */
  66.     {  74176,  4096,  74176,  5733,  75335,  6144,  74176 }, /*  74.25/1.001 MHz */
  67.     {  74250,  4096,  74250,  6272,  82500,  6144,  74250 }, /*  74.25       MHz */
  68.     { 148352,  4096, 148352,  5733, 150670,  6144, 148352 }, /* 148.50/1.001 MHz */
  69.     { 148500,  4096, 148500,  6272, 165000,  6144, 148500 }, /* 148.50       MHz */
  70. };
  71.  
  72.  
  73. /*
  74.  * calculate CTS and N values if they are not found in the table
  75.  */
  76. static void r600_hdmi_calc_cts(uint32_t clock, int *CTS, int *N, int freq)
  77. {
  78.         int n, cts;
  79.         unsigned long div, mul;
  80.  
  81.         /* Safe, but overly large values */
  82.         n = 128 * freq;
  83.         cts = clock * 1000;
  84.  
  85.         /* Smallest valid fraction */
  86.         div = gcd(n, cts);
  87.  
  88.         n /= div;
  89.         cts /= div;
  90.  
  91.         /*
  92.          * The optimal N is 128*freq/1000. Calculate the closest larger
  93.          * value that doesn't truncate any bits.
  94.          */
  95.         mul = ((128*freq/1000) + (n-1))/n;
  96.  
  97.         n *= mul;
  98.         cts *= mul;
  99.  
  100.         /* Check that we are in spec (not always possible) */
  101.         if (n < (128*freq/1500))
  102.                 printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");
  103.         if (n > (128*freq/300))
  104.                 printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");
  105.  
  106.         *N = n;
  107.         *CTS = cts;
  108.  
  109.         DRM_DEBUG("Calculated ACR timing N=%d CTS=%d for frequency %d\n",
  110.                   *N, *CTS, freq);
  111. }
  112.  
  113. struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock)
  114. {
  115.         struct radeon_hdmi_acr res;
  116.         u8 i;
  117.  
  118.         /* Precalculated values for common clocks */
  119.         for (i = 0; i < ARRAY_SIZE(r600_hdmi_predefined_acr); i++) {
  120.                 if (r600_hdmi_predefined_acr[i].clock == clock)
  121.                         return r600_hdmi_predefined_acr[i];
  122.         }
  123.  
  124.         /* And odd clocks get manually calculated */
  125.         r600_hdmi_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);
  126.         r600_hdmi_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);
  127.         r600_hdmi_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);
  128.  
  129.         return res;
  130. }
  131.  
  132. /*
  133.  * update the N and CTS parameters for a given pixel clock rate
  134.  */
  135. void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  136. {
  137.         struct drm_device *dev = encoder->dev;
  138.         struct radeon_device *rdev = dev->dev_private;
  139.         struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
  140.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  141.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  142.         uint32_t offset = dig->afmt->offset;
  143.  
  144.         WREG32_P(HDMI0_ACR_32_0 + offset,
  145.                  HDMI0_ACR_CTS_32(acr.cts_32khz),
  146.                  ~HDMI0_ACR_CTS_32_MASK);
  147.         WREG32_P(HDMI0_ACR_32_1 + offset,
  148.                  HDMI0_ACR_N_32(acr.n_32khz),
  149.                  ~HDMI0_ACR_N_32_MASK);
  150.  
  151.         WREG32_P(HDMI0_ACR_44_0 + offset,
  152.                  HDMI0_ACR_CTS_44(acr.cts_44_1khz),
  153.                  ~HDMI0_ACR_CTS_44_MASK);
  154.         WREG32_P(HDMI0_ACR_44_1 + offset,
  155.                  HDMI0_ACR_N_44(acr.n_44_1khz),
  156.                  ~HDMI0_ACR_N_44_MASK);
  157.  
  158.         WREG32_P(HDMI0_ACR_48_0 + offset,
  159.                  HDMI0_ACR_CTS_48(acr.cts_48khz),
  160.                  ~HDMI0_ACR_CTS_48_MASK);
  161.         WREG32_P(HDMI0_ACR_48_1 + offset,
  162.                  HDMI0_ACR_N_48(acr.n_48khz),
  163.                  ~HDMI0_ACR_N_48_MASK);
  164. }
  165.  
  166. /*
  167.  * build a HDMI Video Info Frame
  168.  */
  169. void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
  170.                                     size_t size)
  171. {
  172.         struct drm_device *dev = encoder->dev;
  173.         struct radeon_device *rdev = dev->dev_private;
  174.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  175.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  176.         uint32_t offset = dig->afmt->offset;
  177.         uint8_t *frame = buffer + 3;
  178.         uint8_t *header = buffer;
  179.  
  180.         WREG32(HDMI0_AVI_INFO0 + offset,
  181.                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
  182.         WREG32(HDMI0_AVI_INFO1 + offset,
  183.                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
  184.         WREG32(HDMI0_AVI_INFO2 + offset,
  185.                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
  186.         WREG32(HDMI0_AVI_INFO3 + offset,
  187.                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
  188. }
  189.  
  190. /*
  191.  * build a Audio Info Frame
  192.  */
  193. static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder,
  194.                                              const void *buffer, size_t size)
  195. {
  196.         struct drm_device *dev = encoder->dev;
  197.         struct radeon_device *rdev = dev->dev_private;
  198.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  199.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  200.         uint32_t offset = dig->afmt->offset;
  201.         const u8 *frame = buffer + 3;
  202.  
  203.         WREG32(HDMI0_AUDIO_INFO0 + offset,
  204.                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
  205.         WREG32(HDMI0_AUDIO_INFO1 + offset,
  206.                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24));
  207. }
  208.  
  209. /*
  210.  * test if audio buffer is filled enough to start playing
  211.  */
  212. static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder)
  213. {
  214.         struct drm_device *dev = encoder->dev;
  215.         struct radeon_device *rdev = dev->dev_private;
  216.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  217.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  218.         uint32_t offset = dig->afmt->offset;
  219.  
  220.         return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
  221. }
  222.  
  223. /*
  224.  * have buffer status changed since last call?
  225.  */
  226. int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder)
  227. {
  228.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  229.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  230.         int status, result;
  231.  
  232.         if (!dig->afmt || !dig->afmt->enabled)
  233.                 return 0;
  234.  
  235.         status = r600_hdmi_is_audio_buffer_filled(encoder);
  236.         result = dig->afmt->last_buffer_filled_status != status;
  237.         dig->afmt->last_buffer_filled_status = status;
  238.  
  239.         return result;
  240. }
  241.  
  242. /*
  243.  * write the audio workaround status to the hardware
  244.  */
  245. void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
  246. {
  247.         struct drm_device *dev = encoder->dev;
  248.         struct radeon_device *rdev = dev->dev_private;
  249.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  250.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  251.         uint32_t offset = dig->afmt->offset;
  252.         bool hdmi_audio_workaround = false; /* FIXME */
  253.         u32 value;
  254.  
  255.         if (!hdmi_audio_workaround ||
  256.             r600_hdmi_is_audio_buffer_filled(encoder))
  257.                 value = 0; /* disable workaround */
  258.         else
  259.                 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */
  260.         WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
  261.                  value, ~HDMI0_AUDIO_TEST_EN);
  262. }
  263.  
  264. void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
  265. {
  266.         struct drm_device *dev = encoder->dev;
  267.         struct radeon_device *rdev = dev->dev_private;
  268.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  269.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  270.         u32 base_rate = 24000;
  271.         u32 max_ratio = clock / base_rate;
  272.         u32 dto_phase;
  273.         u32 dto_modulo = clock;
  274.         u32 wallclock_ratio;
  275.         u32 dto_cntl;
  276.  
  277.         if (!dig || !dig->afmt)
  278.                 return;
  279.  
  280.         if (max_ratio >= 8) {
  281.                 dto_phase = 192 * 1000;
  282.                 wallclock_ratio = 3;
  283.         } else if (max_ratio >= 4) {
  284.                 dto_phase = 96 * 1000;
  285.                 wallclock_ratio = 2;
  286.         } else if (max_ratio >= 2) {
  287.                 dto_phase = 48 * 1000;
  288.                 wallclock_ratio = 1;
  289.         } else {
  290.                 dto_phase = 24 * 1000;
  291.                 wallclock_ratio = 0;
  292.         }
  293.  
  294.         /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
  295.          * doesn't matter which one you use.  Just use the first one.
  296.          */
  297.         /* XXX two dtos; generally use dto0 for hdmi */
  298.         /* Express [24MHz / target pixel clock] as an exact rational
  299.          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
  300.          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
  301.          */
  302.         if (ASIC_IS_DCE32(rdev)) {
  303.                 if (dig->dig_encoder == 0) {
  304.                         dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
  305.                         dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
  306.                         WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
  307.                         WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
  308.                         WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
  309.                         WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
  310.                 } else {
  311.                         dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
  312.                         dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
  313.                         WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
  314.                         WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
  315.                         WREG32(DCCG_AUDIO_DTO1_MODULE, dto_modulo);
  316.                         WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
  317.                 }
  318.         } else {
  319.                 /* according to the reg specs, this should DCE3.2 only, but in
  320.                  * practice it seems to cover DCE2.0/3.0/3.1 as well.
  321.                  */
  322.                 if (dig->dig_encoder == 0) {
  323.                 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 100);
  324.                 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
  325.                 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
  326.         } else {
  327.                         WREG32(DCCG_AUDIO_DTO1_PHASE, base_rate * 100);
  328.                         WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);
  329.                         WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
  330.                 }
  331.         }
  332. }
  333.  
  334. /*
  335.  * update the info frames with the data from the current display mode
  336.  */
  337. void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
  338. {
  339.         struct drm_device *dev = encoder->dev;
  340.         struct radeon_device *rdev = dev->dev_private;
  341.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  342.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  343.         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
  344.         struct hdmi_avi_infoframe frame;
  345.         uint32_t offset;
  346.         uint32_t acr_ctl;
  347.         ssize_t err;
  348.  
  349.         if (!dig || !dig->afmt)
  350.                 return;
  351.  
  352.         /* Silent, r600_hdmi_enable will raise WARN for us */
  353.         if (!dig->afmt->enabled)
  354.                 return;
  355.         offset = dig->afmt->offset;
  356.  
  357.         /* disable audio prior to setting up hw */
  358.         dig->afmt->pin = r600_audio_get_pin(rdev);
  359.         r600_audio_enable(rdev, dig->afmt->pin, false);
  360.  
  361.         r600_audio_set_dto(encoder, mode->clock);
  362.  
  363.         WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,
  364.                        HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
  365.                        HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
  366.                        HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
  367.                  HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */
  368.                  ~(HDMI0_AUDIO_SAMPLE_SEND |
  369.                    HDMI0_AUDIO_DELAY_EN_MASK |
  370.                    HDMI0_AUDIO_PACKETS_PER_LINE_MASK |
  371.                    HDMI0_60958_CS_UPDATE));
  372.  
  373.         /* DCE 3.0 uses register that's normally for CRC_CONTROL */
  374.         acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL :
  375.                                        HDMI0_ACR_PACKET_CONTROL;
  376.         WREG32_P(acr_ctl + offset,
  377.                HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
  378.                  HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */
  379.                  ~(HDMI0_ACR_SOURCE |
  380.                    HDMI0_ACR_AUTO_SEND));
  381.  
  382.         WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
  383.                HDMI0_NULL_SEND | /* send null packets when required */
  384.                HDMI0_GC_SEND | /* send general control packets */
  385.                HDMI0_GC_CONT); /* send general control packets every frame */
  386.  
  387.         WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
  388.                HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
  389.                HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
  390.                HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
  391.                   HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
  392.  
  393.         WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset,
  394.                HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
  395.                  HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */
  396.                  ~(HDMI0_AVI_INFO_LINE_MASK |
  397.                    HDMI0_AUDIO_INFO_LINE_MASK));
  398.  
  399.         WREG32_AND(HDMI0_GC + offset,
  400.                    ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */
  401.  
  402.         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
  403.         if (err < 0) {
  404.                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
  405.                 return;
  406.         }
  407.  
  408.         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
  409.         if (err < 0) {
  410.                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
  411.                 return;
  412.         }
  413.  
  414.         r600_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
  415.  
  416.         /* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */
  417.  
  418.         WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,
  419.                    ~(HDMI0_GENERIC0_SEND |
  420.                      HDMI0_GENERIC0_CONT |
  421.                      HDMI0_GENERIC0_UPDATE |
  422.                      HDMI0_GENERIC1_SEND |
  423.                      HDMI0_GENERIC1_CONT |
  424.                      HDMI0_GENERIC0_LINE_MASK |
  425.                      HDMI0_GENERIC1_LINE_MASK));
  426.  
  427.         r600_hdmi_update_ACR(encoder, mode->clock);
  428.  
  429.         WREG32_P(HDMI0_60958_0 + offset,
  430.                  HDMI0_60958_CS_CHANNEL_NUMBER_L(1),
  431.                  ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
  432.                    HDMI0_60958_CS_CLOCK_ACCURACY_MASK));
  433.  
  434.         WREG32_P(HDMI0_60958_1 + offset,
  435.                  HDMI0_60958_CS_CHANNEL_NUMBER_R(2),
  436.                  ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);
  437.  
  438.         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
  439.         WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
  440.         WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
  441.         WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
  442.         WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
  443.  
  444.         /* enable audio after to setting up hw */
  445.         r600_audio_enable(rdev, dig->afmt->pin, true);
  446. }
  447.  
  448. /**
  449.  * r600_hdmi_update_audio_settings - Update audio infoframe
  450.  *
  451.  * @encoder: drm encoder
  452.  *
  453.  * Gets info about current audio stream and updates audio infoframe.
  454.  */
  455. void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
  456. {
  457.         struct drm_device *dev = encoder->dev;
  458.         struct radeon_device *rdev = dev->dev_private;
  459.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  460.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  461.         struct r600_audio_pin audio = r600_audio_status(rdev);
  462.         uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
  463.         struct hdmi_audio_infoframe frame;
  464.         uint32_t offset;
  465.         uint32_t value;
  466.         ssize_t err;
  467.  
  468.         if (!dig->afmt || !dig->afmt->enabled)
  469.                 return;
  470.         offset = dig->afmt->offset;
  471.  
  472.         DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n",
  473.                  r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped",
  474.                   audio.channels, audio.rate, audio.bits_per_sample);
  475.         DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n",
  476.                   (int)audio.status_bits, (int)audio.category_code);
  477.  
  478.         err = hdmi_audio_infoframe_init(&frame);
  479.         if (err < 0) {
  480.                 DRM_ERROR("failed to setup audio infoframe\n");
  481.                 return;
  482.         }
  483.  
  484.         frame.channels = audio.channels;
  485.  
  486.         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
  487.         if (err < 0) {
  488.                 DRM_ERROR("failed to pack audio infoframe\n");
  489.                 return;
  490.         }
  491.  
  492.         value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
  493.         if (value & HDMI0_AUDIO_TEST_EN)
  494.                 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
  495.                        value & ~HDMI0_AUDIO_TEST_EN);
  496.  
  497.         WREG32_OR(HDMI0_CONTROL + offset,
  498.                   HDMI0_ERROR_ACK);
  499.  
  500.         WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset,
  501.                    ~HDMI0_AUDIO_INFO_SOURCE);
  502.  
  503.         r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer));
  504.  
  505.         WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
  506.                   HDMI0_AUDIO_INFO_CONT |
  507.                   HDMI0_AUDIO_INFO_UPDATE);
  508. }
  509.  
  510. /*
  511.  * enable the HDMI engine
  512.  */
  513. void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
  514. {
  515.         struct drm_device *dev = encoder->dev;
  516.         struct radeon_device *rdev = dev->dev_private;
  517.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  518.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  519.         u32 hdmi = HDMI0_ERROR_ACK;
  520.  
  521.         if (!dig || !dig->afmt)
  522.                 return;
  523.  
  524.         /* Silent, r600_hdmi_enable will raise WARN for us */
  525.         if (enable && dig->afmt->enabled)
  526.                 return;
  527.         if (!enable && !dig->afmt->enabled)
  528.                 return;
  529.  
  530.         /* Older chipsets require setting HDMI and routing manually */
  531.         if (!ASIC_IS_DCE3(rdev)) {
  532.                 if (enable)
  533.                         hdmi |= HDMI0_ENABLE;
  534.         switch (radeon_encoder->encoder_id) {
  535.         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
  536.                         if (enable) {
  537.                                 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
  538.                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
  539.                         } else {
  540.                                 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
  541.                         }
  542.                 break;
  543.         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
  544.                         if (enable) {
  545.                                 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
  546.                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
  547.                         } else {
  548.                                 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
  549.                         }
  550.                         break;
  551.                 case ENCODER_OBJECT_ID_INTERNAL_DDI:
  552.                         if (enable) {
  553.                                 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
  554.                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
  555.                         } else {
  556.                                 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
  557.                         }
  558.                         break;
  559.                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  560.                         if (enable)
  561.                         hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
  562.                 break;
  563.         default:
  564.                         dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
  565.                                 radeon_encoder->encoder_id);
  566.                 break;
  567.         }
  568.                 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
  569.         }
  570.  
  571.         if (rdev->irq.installed) {
  572.                 /* if irq is available use it */
  573.                 /* XXX: shouldn't need this on any asics.  Double check DCE2/3 */
  574. //       if (enable)
  575. //           radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
  576. //       else
  577. //           radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
  578.         }
  579.  
  580.         dig->afmt->enabled = enable;
  581.  
  582.         DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
  583.                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
  584. }
  585.  
  586.