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  1. /*
  2.  * Copyright 2008 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  * Copyright 2009 Jerome Glisse.
  5.  *
  6.  * Permission is hereby granted, free of charge, to any person obtaining a
  7.  * copy of this software and associated documentation files (the "Software"),
  8.  * to deal in the Software without restriction, including without limitation
  9.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10.  * and/or sell copies of the Software, and to permit persons to whom the
  11.  * Software is furnished to do so, subject to the following conditions:
  12.  *
  13.  * The above copyright notice and this permission notice shall be included in
  14.  * all copies or substantial portions of the Software.
  15.  *
  16.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22.  * OTHER DEALINGS IN THE SOFTWARE.
  23.  *
  24.  * Authors: Dave Airlie
  25.  *          Alex Deucher
  26.  *          Jerome Glisse
  27.  */
  28. #include <linux/seq_file.h>
  29. #include "drmP.h"
  30. #include "radeon_reg.h"
  31. #include "radeon.h"
  32. #include "atom.h"
  33. #include "r420d.h"
  34.  
  35. int r420_mc_init(struct radeon_device *rdev)
  36. {
  37.         int r;
  38.  
  39.         /* Setup GPU memory space */
  40.         rdev->mc.vram_location = 0xFFFFFFFFUL;
  41.         rdev->mc.gtt_location = 0xFFFFFFFFUL;
  42.         r = radeon_mc_setup(rdev);
  43.         if (r) {
  44.                 return r;
  45.         }
  46.         return 0;
  47. }
  48.  
  49. void r420_pipes_init(struct radeon_device *rdev)
  50. {
  51.         unsigned tmp;
  52.         unsigned gb_pipe_select;
  53.         unsigned num_pipes;
  54.  
  55.         /* GA_ENHANCE workaround TCL deadlock issue */
  56.         WREG32(0x4274, (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3));
  57.         /* add idle wait as per freedesktop.org bug 24041 */
  58.         if (r100_gui_wait_for_idle(rdev)) {
  59.                 printk(KERN_WARNING "Failed to wait GUI idle while "
  60.                        "programming pipes. Bad things might happen.\n");
  61.         }
  62.         /* get max number of pipes */
  63.         gb_pipe_select = RREG32(0x402C);
  64.         num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
  65.         rdev->num_gb_pipes = num_pipes;
  66.         tmp = 0;
  67.         switch (num_pipes) {
  68.         default:
  69.                 /* force to 1 pipe */
  70.                 num_pipes = 1;
  71.         case 1:
  72.                 tmp = (0 << 1);
  73.                 break;
  74.         case 2:
  75.                 tmp = (3 << 1);
  76.                 break;
  77.         case 3:
  78.                 tmp = (6 << 1);
  79.                 break;
  80.         case 4:
  81.                 tmp = (7 << 1);
  82.                 break;
  83.         }
  84.         WREG32(0x42C8, (1 << num_pipes) - 1);
  85.         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
  86.         tmp |= (1 << 4) | (1 << 0);
  87.         WREG32(0x4018, tmp);
  88.         if (r100_gui_wait_for_idle(rdev)) {
  89.                 printk(KERN_WARNING "Failed to wait GUI idle while "
  90.                        "programming pipes. Bad things might happen.\n");
  91.         }
  92.  
  93.         tmp = RREG32(0x170C);
  94.         WREG32(0x170C, tmp | (1 << 31));
  95.  
  96.         WREG32(R300_RB2D_DSTCACHE_MODE,
  97.                RREG32(R300_RB2D_DSTCACHE_MODE) |
  98.                R300_DC_AUTOFLUSH_ENABLE |
  99.                R300_DC_DC_DISABLE_IGNORE_PE);
  100.  
  101.         if (r100_gui_wait_for_idle(rdev)) {
  102.                 printk(KERN_WARNING "Failed to wait GUI idle while "
  103.                        "programming pipes. Bad things might happen.\n");
  104.         }
  105.  
  106.         if (rdev->family == CHIP_RV530) {
  107.                 tmp = RREG32(RV530_GB_PIPE_SELECT2);
  108.                 if ((tmp & 3) == 3)
  109.                         rdev->num_z_pipes = 2;
  110.                 else
  111.                         rdev->num_z_pipes = 1;
  112.         } else
  113.                 rdev->num_z_pipes = 1;
  114.  
  115.         DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",
  116.                  rdev->num_gb_pipes, rdev->num_z_pipes);
  117. }
  118.  
  119. u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
  120. {
  121.         u32 r;
  122.  
  123.         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));
  124.         r = RREG32(R_0001FC_MC_IND_DATA);
  125.         return r;
  126. }
  127.  
  128. void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  129. {
  130.         WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |
  131.                 S_0001F8_MC_IND_WR_EN(1));
  132.         WREG32(R_0001FC_MC_IND_DATA, v);
  133. }
  134.  
  135. static void r420_debugfs(struct radeon_device *rdev)
  136. {
  137.         if (r100_debugfs_rbbm_init(rdev)) {
  138.                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
  139.         }
  140.         if (r420_debugfs_pipes_info_init(rdev)) {
  141.                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
  142.         }
  143. }
  144.  
  145. static void r420_clock_resume(struct radeon_device *rdev)
  146. {
  147.         u32 sclk_cntl;
  148.         sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
  149.         sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
  150.         if (rdev->family == CHIP_R420)
  151.                 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
  152.         WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
  153. }
  154.  
  155. static int r420_startup(struct radeon_device *rdev)
  156. {
  157.         int r;
  158.  
  159.         r300_mc_program(rdev);
  160.         /* Initialize GART (initialize after TTM so we can allocate
  161.          * memory through TTM but finalize after TTM) */
  162.         if (rdev->flags & RADEON_IS_PCIE) {
  163.                 r = rv370_pcie_gart_enable(rdev);
  164.                 if (r)
  165.                         return r;
  166.         }
  167.         if (rdev->flags & RADEON_IS_PCI) {
  168.                 r = r100_pci_gart_enable(rdev);
  169.                 if (r)
  170.                         return r;
  171.         }
  172.         r420_pipes_init(rdev);
  173.         /* Enable IRQ */
  174. //      rdev->irq.sw_int = true;
  175. //      r100_irq_set(rdev);
  176.         /* 1M ring buffer */
  177.         r = r100_cp_init(rdev, 1024 * 1024);
  178.         if (r) {
  179.                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
  180.                 return r;
  181.         }
  182. //      r = r100_wb_init(rdev);
  183. //      if (r) {
  184. //              dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
  185. //      }
  186. //      r = r100_ib_init(rdev);
  187. //      if (r) {
  188. //              dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
  189. //              return r;
  190. //      }
  191.         return 0;
  192. }
  193.  
  194. int r420_resume(struct radeon_device *rdev)
  195. {
  196.         /* Make sur GART are not working */
  197.         if (rdev->flags & RADEON_IS_PCIE)
  198.                 rv370_pcie_gart_disable(rdev);
  199.         if (rdev->flags & RADEON_IS_PCI)
  200.                 r100_pci_gart_disable(rdev);
  201.         /* Resume clock before doing reset */
  202.         r420_clock_resume(rdev);
  203.         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  204.         if (radeon_gpu_reset(rdev)) {
  205.                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  206.                         RREG32(R_000E40_RBBM_STATUS),
  207.                         RREG32(R_0007C0_CP_STAT));
  208.         }
  209.         /* check if cards are posted or not */
  210.         if (rdev->is_atom_bios) {
  211.                 atom_asic_init(rdev->mode_info.atom_context);
  212.         } else {
  213.                 radeon_combios_asic_init(rdev->ddev);
  214.         }
  215.         /* Resume clock after posting */
  216.         r420_clock_resume(rdev);
  217.  
  218.         return r420_startup(rdev);
  219. }
  220.  
  221. int r420_suspend(struct radeon_device *rdev)
  222. {
  223.         r100_cp_disable(rdev);
  224. //      r100_wb_disable(rdev);
  225. //      r100_irq_disable(rdev);
  226.         if (rdev->flags & RADEON_IS_PCIE)
  227.                 rv370_pcie_gart_disable(rdev);
  228.         if (rdev->flags & RADEON_IS_PCI)
  229.                 r100_pci_gart_disable(rdev);
  230.         return 0;
  231. }
  232.  
  233. void r420_fini(struct radeon_device *rdev)
  234. {
  235.         r100_cp_fini(rdev);
  236. //      r100_wb_fini(rdev);
  237. //      r100_ib_fini(rdev);
  238.         radeon_gem_fini(rdev);
  239.         if (rdev->flags & RADEON_IS_PCIE)
  240.                 rv370_pcie_gart_fini(rdev);
  241.         if (rdev->flags & RADEON_IS_PCI)
  242.                 r100_pci_gart_fini(rdev);
  243. //      radeon_agp_fini(rdev);
  244. //      radeon_irq_kms_fini(rdev);
  245. //      radeon_fence_driver_fini(rdev);
  246. //   radeon_object_fini(rdev);
  247.         if (rdev->is_atom_bios) {
  248.                 radeon_atombios_fini(rdev);
  249.         } else {
  250.                 radeon_combios_fini(rdev);
  251.         }
  252.         kfree(rdev->bios);
  253.         rdev->bios = NULL;
  254. }
  255.  
  256. int r420_init(struct radeon_device *rdev)
  257. {
  258.         int r;
  259.  
  260.         rdev->new_init_path = true;
  261.         /* Initialize scratch registers */
  262.         radeon_scratch_init(rdev);
  263.         /* Initialize surface registers */
  264.         radeon_surface_init(rdev);
  265.         /* TODO: disable VGA need to use VGA request */
  266.         /* BIOS*/
  267.         if (!radeon_get_bios(rdev)) {
  268.                 if (ASIC_IS_AVIVO(rdev))
  269.                         return -EINVAL;
  270.         }
  271.         if (rdev->is_atom_bios) {
  272.                 r = radeon_atombios_init(rdev);
  273.                 if (r) {
  274.                         return r;
  275.                 }
  276.         } else {
  277.                 r = radeon_combios_init(rdev);
  278.                 if (r) {
  279.                         return r;
  280.                 }
  281.         }
  282.         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  283.         if (radeon_gpu_reset(rdev)) {
  284.                 dev_warn(rdev->dev,
  285.                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  286.                         RREG32(R_000E40_RBBM_STATUS),
  287.                         RREG32(R_0007C0_CP_STAT));
  288.         }
  289.         /* check if cards are posted or not */
  290.         if (!radeon_card_posted(rdev) && rdev->bios) {
  291.                 DRM_INFO("GPU not posted. posting now...\n");
  292.                 if (rdev->is_atom_bios) {
  293.                         atom_asic_init(rdev->mode_info.atom_context);
  294.                 } else {
  295.                         radeon_combios_asic_init(rdev->ddev);
  296.                 }
  297.         }
  298.         /* Initialize clocks */
  299.         radeon_get_clock_info(rdev->ddev);
  300.         /* Get vram informations */
  301.         r300_vram_info(rdev);
  302.         /* Initialize memory controller (also test AGP) */
  303.         r = r420_mc_init(rdev);
  304.         if (r) {
  305.                 return r;
  306.         }
  307.         r420_debugfs(rdev);
  308.         /* Fence driver */
  309. //      r = radeon_fence_driver_init(rdev);
  310. //      if (r) {
  311. //              return r;
  312. //      }
  313. //      r = radeon_irq_kms_init(rdev);
  314. //      if (r) {
  315. //              return r;
  316. //      }
  317.         /* Memory manager */
  318.         r = radeon_object_init(rdev);
  319.         if (r) {
  320.                 return r;
  321.         }
  322.         if (rdev->flags & RADEON_IS_PCIE) {
  323.                 r = rv370_pcie_gart_init(rdev);
  324.                 if (r)
  325.                         return r;
  326.         }
  327.         if (rdev->flags & RADEON_IS_PCI) {
  328.                 r = r100_pci_gart_init(rdev);
  329.                 if (r)
  330.                         return r;
  331.         }
  332.         r300_set_reg_safe(rdev);
  333.         rdev->accel_working = true;
  334.         r = r420_startup(rdev);
  335.         if (r) {
  336.                 /* Somethings want wront with the accel init stop accel */
  337.                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
  338.                 r420_suspend(rdev);
  339. //              r100_cp_fini(rdev);
  340. //              r100_wb_fini(rdev);
  341. //              r100_ib_fini(rdev);
  342.                 if (rdev->flags & RADEON_IS_PCIE)
  343.                         rv370_pcie_gart_fini(rdev);
  344.                 if (rdev->flags & RADEON_IS_PCI)
  345.                         r100_pci_gart_fini(rdev);
  346. //              radeon_agp_fini(rdev);
  347. //              radeon_irq_kms_fini(rdev);
  348.                 rdev->accel_working = false;
  349.         }
  350.         return 0;
  351. }
  352.  
  353. /*
  354.  * Debugfs info
  355.  */
  356. #if defined(CONFIG_DEBUG_FS)
  357. static int r420_debugfs_pipes_info(struct seq_file *m, void *data)
  358. {
  359.         struct drm_info_node *node = (struct drm_info_node *) m->private;
  360.         struct drm_device *dev = node->minor->dev;
  361.         struct radeon_device *rdev = dev->dev_private;
  362.         uint32_t tmp;
  363.  
  364.         tmp = RREG32(R400_GB_PIPE_SELECT);
  365.         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
  366.         tmp = RREG32(R300_GB_TILE_CONFIG);
  367.         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
  368.         tmp = RREG32(R300_DST_PIPE_CONFIG);
  369.         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
  370.         return 0;
  371. }
  372.  
  373. static struct drm_info_list r420_pipes_info_list[] = {
  374.         {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL},
  375. };
  376. #endif
  377.  
  378. int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
  379. {
  380. #if defined(CONFIG_DEBUG_FS)
  381.         return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);
  382. #else
  383.         return 0;
  384. #endif
  385. }
  386.