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  1.  
  2. #include <pci.h>
  3. #include <errno-base.h>
  4. #include <syscall.h>
  5.  
  6. static LIST_HEAD(devices);
  7.  
  8. static dev_t* pci_scan_device(u32_t bus, int devfn);
  9.  
  10.  
  11. /* PCI control bits.  Shares IORESOURCE_BITS with above PCI ROM.  */
  12. #define IORESOURCE_PCI_FIXED            (1<<4)  /* Do not move resource */
  13.  
  14. #define LEGACY_IO_RESOURCE      (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
  15.  
  16. /*
  17.  * Translate the low bits of the PCI base
  18.  * to the resource type
  19.  */
  20. static inline unsigned int pci_calc_resource_flags(unsigned int flags)
  21. {
  22.     if (flags & PCI_BASE_ADDRESS_SPACE_IO)
  23.         return IORESOURCE_IO;
  24.  
  25.     if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
  26.         return IORESOURCE_MEM | IORESOURCE_PREFETCH;
  27.  
  28.     return IORESOURCE_MEM;
  29. }
  30.  
  31.  
  32. static u32_t pci_size(u32_t base, u32_t maxbase, u32_t mask)
  33. {
  34.     u32_t size = mask & maxbase;      /* Find the significant bits */
  35.  
  36.     if (!size)
  37.         return 0;
  38.  
  39.     /* Get the lowest of them to find the decode size, and
  40.        from that the extent.  */
  41.     size = (size & ~(size-1)) - 1;
  42.  
  43.     /* base == maxbase can be valid only if the BAR has
  44.        already been programmed with all 1s.  */
  45.     if (base == maxbase && ((base | size) & mask) != mask)
  46.         return 0;
  47.  
  48.     return size;
  49. }
  50.  
  51. static u64_t pci_size64(u64_t base, u64_t maxbase, u64_t mask)
  52. {
  53.     u64_t size = mask & maxbase;      /* Find the significant bits */
  54.  
  55.     if (!size)
  56.         return 0;
  57.  
  58.     /* Get the lowest of them to find the decode size, and
  59.        from that the extent.  */
  60.     size = (size & ~(size-1)) - 1;
  61.  
  62.     /* base == maxbase can be valid only if the BAR has
  63.        already been programmed with all 1s.  */
  64.     if (base == maxbase && ((base | size) & mask) != mask)
  65.         return 0;
  66.  
  67.     return size;
  68. }
  69.  
  70. static inline int is_64bit_memory(u32_t mask)
  71. {
  72.     if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
  73.         (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
  74.         return 1;
  75.     return 0;
  76. }
  77.  
  78. static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
  79. {
  80.     u32_t  pos, reg, next;
  81.     u32_t  l, sz;
  82.     struct resource *res;
  83.  
  84.     for(pos=0; pos < howmany; pos = next)
  85.     {
  86.         u64_t  l64;
  87.         u64_t  sz64;
  88.         u32_t  raw_sz;
  89.  
  90.         next = pos + 1;
  91.  
  92.         res  = &dev->resource[pos];
  93.  
  94.         reg = PCI_BASE_ADDRESS_0 + (pos << 2);
  95.         l = PciRead32(dev->bus, dev->devfn, reg);
  96.         PciWrite32(dev->bus, dev->devfn, reg, ~0);
  97.         sz = PciRead32(dev->bus, dev->devfn, reg);
  98.         PciWrite32(dev->bus, dev->devfn, reg, l);
  99.  
  100.         if (!sz || sz == 0xffffffff)
  101.             continue;
  102.  
  103.         if (l == 0xffffffff)
  104.             l = 0;
  105.  
  106.         raw_sz = sz;
  107.         if ((l & PCI_BASE_ADDRESS_SPACE) ==
  108.                         PCI_BASE_ADDRESS_SPACE_MEMORY)
  109.         {
  110.             sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK);
  111.             /*
  112.              * For 64bit prefetchable memory sz could be 0, if the
  113.              * real size is bigger than 4G, so we need to check
  114.              * szhi for that.
  115.              */
  116.             if (!is_64bit_memory(l) && !sz)
  117.                     continue;
  118.             res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
  119.             res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
  120.         }
  121.         else {
  122.             sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
  123.             if (!sz)
  124.                 continue;
  125.             res->start = l & PCI_BASE_ADDRESS_IO_MASK;
  126.             res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
  127.         }
  128.         res->end = res->start + (unsigned long) sz;
  129.         res->flags |= pci_calc_resource_flags(l);
  130.         if (is_64bit_memory(l))
  131.         {
  132.             u32_t szhi, lhi;
  133.  
  134.             lhi = PciRead32(dev->bus, dev->devfn, reg+4);
  135.             PciWrite32(dev->bus, dev->devfn, reg+4, ~0);
  136.             szhi = PciRead32(dev->bus, dev->devfn, reg+4);
  137.             PciWrite32(dev->bus, dev->devfn, reg+4, lhi);
  138.             sz64 = ((u64_t)szhi << 32) | raw_sz;
  139.             l64 = ((u64_t)lhi << 32) | l;
  140.             sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
  141.             next++;
  142.  
  143. #if BITS_PER_LONG == 64
  144.             if (!sz64) {
  145.                 res->start = 0;
  146.                 res->end = 0;
  147.                 res->flags = 0;
  148.                 continue;
  149.             }
  150.             res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
  151.             res->end = res->start + sz64;
  152. #else
  153.             if (sz64 > 0x100000000ULL) {
  154.                 printk(KERN_ERR "PCI: Unable to handle 64-bit "
  155.                                 "BAR for device %s\n", pci_name(dev));
  156.                 res->start = 0;
  157.                 res->flags = 0;
  158.             }
  159.             else if (lhi)
  160.             {
  161.                 /* 64-bit wide address, treat as disabled */
  162.                 PciWrite32(dev->bus, dev->devfn, reg,
  163.                         l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK);
  164.                 PciWrite32(dev->bus, dev->devfn, reg+4, 0);
  165.                 res->start = 0;
  166.                 res->end = sz;
  167.             }
  168. #endif
  169.         }
  170.     }
  171.  
  172.     if ( rom )
  173.     {
  174.         dev->rom_base_reg = rom;
  175.         res = &dev->resource[PCI_ROM_RESOURCE];
  176.  
  177.         l = PciRead32(dev->bus, dev->devfn, rom);
  178.         PciWrite32(dev->bus, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
  179.         sz = PciRead32(dev->bus, dev->devfn, rom);
  180.         PciWrite32(dev->bus, dev->devfn, rom, l);
  181.  
  182.         if (l == 0xffffffff)
  183.             l = 0;
  184.  
  185.         if (sz && sz != 0xffffffff)
  186.         {
  187.             sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK);
  188.  
  189.             if (sz)
  190.             {
  191.                 res->flags = (l & IORESOURCE_ROM_ENABLE) |
  192.                                   IORESOURCE_MEM | IORESOURCE_PREFETCH |
  193.                                   IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
  194.                 res->start = l & PCI_ROM_ADDRESS_MASK;
  195.                 res->end = res->start + (unsigned long) sz;
  196.             }
  197.         }
  198.     }
  199. }
  200.  
  201. static void pci_read_irq(struct pci_dev *dev)
  202. {
  203.     u8_t irq;
  204.  
  205.     irq = PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_PIN);
  206.     dev->pin = irq;
  207.     if (irq)
  208.         PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_LINE);
  209.     dev->irq = irq;
  210. };
  211.  
  212.  
  213. static int pci_setup_device(struct pci_dev *dev)
  214. {
  215.     u32_t  class;
  216.  
  217.     class = PciRead32(dev->bus, dev->devfn, PCI_CLASS_REVISION);
  218.     dev->revision = class & 0xff;
  219.     class >>= 8;                                /* upper 3 bytes */
  220.     dev->class = class;
  221.  
  222.     /* "Unknown power state" */
  223. //    dev->current_state = PCI_UNKNOWN;
  224.  
  225.     /* Early fixups, before probing the BARs */
  226.  //   pci_fixup_device(pci_fixup_early, dev);
  227.     class = dev->class >> 8;
  228.  
  229.     switch (dev->hdr_type)
  230.     {
  231.         case PCI_HEADER_TYPE_NORMAL:                /* standard header */
  232.             if (class == PCI_CLASS_BRIDGE_PCI)
  233.                 goto bad;
  234.             pci_read_irq(dev);
  235.             pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
  236.             dev->subsystem_vendor = PciRead16(dev->bus, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
  237.             dev->subsystem_device = PciRead16(dev->bus, dev->devfn, PCI_SUBSYSTEM_ID);
  238.  
  239.             /*
  240.              *      Do the ugly legacy mode stuff here rather than broken chip
  241.              *      quirk code. Legacy mode ATA controllers have fixed
  242.              *      addresses. These are not always echoed in BAR0-3, and
  243.              *      BAR0-3 in a few cases contain junk!
  244.              */
  245.             if (class == PCI_CLASS_STORAGE_IDE)
  246.             {
  247.                 u8_t progif;
  248.  
  249.                 progif = PciRead8(dev->bus, dev->devfn,PCI_CLASS_PROG);
  250.                 if ((progif & 1) == 0)
  251.                 {
  252.                     dev->resource[0].start = 0x1F0;
  253.                     dev->resource[0].end = 0x1F7;
  254.                     dev->resource[0].flags = LEGACY_IO_RESOURCE;
  255.                     dev->resource[1].start = 0x3F6;
  256.                     dev->resource[1].end = 0x3F6;
  257.                     dev->resource[1].flags = LEGACY_IO_RESOURCE;
  258.                 }
  259.                 if ((progif & 4) == 0)
  260.                 {
  261.                     dev->resource[2].start = 0x170;
  262.                     dev->resource[2].end = 0x177;
  263.                     dev->resource[2].flags = LEGACY_IO_RESOURCE;
  264.                     dev->resource[3].start = 0x376;
  265.                     dev->resource[3].end = 0x376;
  266.                     dev->resource[3].flags = LEGACY_IO_RESOURCE;
  267.                 };
  268.             }
  269.             break;
  270.  
  271.         case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
  272.                 if (class != PCI_CLASS_BRIDGE_PCI)
  273.                         goto bad;
  274.                 /* The PCI-to-PCI bridge spec requires that subtractive
  275.                    decoding (i.e. transparent) bridge must have programming
  276.                    interface code of 0x01. */
  277.                 pci_read_irq(dev);
  278.                 dev->transparent = ((dev->class & 0xff) == 1);
  279.                 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
  280.                 break;
  281.  
  282.         case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
  283.                 if (class != PCI_CLASS_BRIDGE_CARDBUS)
  284.                         goto bad;
  285.                 pci_read_irq(dev);
  286.                 pci_read_bases(dev, 1, 0);
  287.                 dev->subsystem_vendor = PciRead16(dev->bus,
  288.                                                   dev->devfn,
  289.                                                   PCI_CB_SUBSYSTEM_VENDOR_ID);
  290.  
  291.                 dev->subsystem_device = PciRead16(dev->bus,
  292.                                                   dev->devfn,
  293.                                                   PCI_CB_SUBSYSTEM_ID);
  294.                 break;
  295.  
  296.         default:                                    /* unknown header */
  297.                 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
  298.                         pci_name(dev), dev->hdr_type);
  299.                 return -1;
  300.  
  301.         bad:
  302.                 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
  303.                        pci_name(dev), class, dev->hdr_type);
  304.                 dev->class = PCI_CLASS_NOT_DEFINED;
  305.     }
  306.  
  307.     /* We found a fine healthy device, go go go... */
  308.  
  309.     return 0;
  310. };
  311.  
  312. static dev_t* pci_scan_device(u32_t bus, int devfn)
  313. {
  314.     dev_t  *dev;
  315.  
  316.     u32_t   id;
  317.     u8_t    hdr;
  318.  
  319.     int     timeout = 10;
  320.  
  321.     id = PciRead32(bus,devfn, PCI_VENDOR_ID);
  322.  
  323.     /* some broken boards return 0 or ~0 if a slot is empty: */
  324.     if (id == 0xffffffff || id == 0x00000000 ||
  325.         id == 0x0000ffff || id == 0xffff0000)
  326.         return NULL;
  327.  
  328.     while (id == 0xffff0001)
  329.     {
  330.  
  331.         delay(timeout/10);
  332.         timeout *= 2;
  333.  
  334.         id = PciRead32(bus, devfn, PCI_VENDOR_ID);
  335.  
  336.         /* Card hasn't responded in 60 seconds?  Must be stuck. */
  337.         if (timeout > 60 * 100)
  338.         {
  339.             printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
  340.                    "responding\n", bus,PCI_SLOT(devfn),PCI_FUNC(devfn));
  341.             return NULL;
  342.         }
  343.     };
  344.  
  345.     hdr = PciRead8(bus, devfn, PCI_HEADER_TYPE);
  346.  
  347.     dev = (dev_t*)malloc(sizeof(dev_t));
  348.  
  349.     INIT_LIST_HEAD(&dev->link);
  350.  
  351.     if(unlikely(dev == NULL))
  352.         return NULL;
  353.  
  354.     dev->pci_dev.bus      = bus;
  355.     dev->pci_dev.devfn    = devfn;
  356.     dev->pci_dev.hdr_type = hdr & 0x7f;
  357.     dev->pci_dev.multifunction    = !!(hdr & 0x80);
  358.     dev->pci_dev.vendor   = id & 0xffff;
  359.     dev->pci_dev.device   = (id >> 16) & 0xffff;
  360.  
  361.     pci_setup_device(&dev->pci_dev);
  362.  
  363.     return dev;
  364.  
  365. };
  366.  
  367. int pci_scan_slot(u32_t bus, int devfn)
  368. {
  369.     int  func, nr = 0;
  370.  
  371.     for (func = 0; func < 8; func++, devfn++)
  372.     {
  373.         dev_t  *dev;
  374.  
  375.         dev = pci_scan_device(bus, devfn);
  376.         if( dev )
  377.         {
  378.             list_add(&dev->link, &devices);
  379.  
  380.             nr++;
  381.  
  382.             /*
  383.              * If this is a single function device,
  384.              * don't scan past the first function.
  385.              */
  386.             if (!dev->pci_dev.multifunction)
  387.             {
  388.                 if (func > 0) {
  389.                     dev->pci_dev.multifunction = 1;
  390.                 }
  391.                 else {
  392.                     break;
  393.                 }
  394.              }
  395.         }
  396.         else {
  397.             if (func == 0)
  398.                 break;
  399.         }
  400.     };
  401.  
  402.     return nr;
  403. };
  404.  
  405.  
  406. void pci_scan_bus(u32_t bus)
  407. {
  408.     u32_t devfn;
  409.     dev_t *dev;
  410.  
  411.  
  412.     for (devfn = 0; devfn < 0x100; devfn += 8)
  413.         pci_scan_slot(bus, devfn);
  414.  
  415. }
  416.  
  417. int enum_pci_devices()
  418. {
  419.     dev_t  *dev;
  420.     u32_t   last_bus;
  421.     u32_t   bus = 0 , devfn = 0;
  422.  
  423.   //  list_initialize(&devices);
  424.  
  425.     last_bus = PciApi(1);
  426.  
  427.  
  428.     if( unlikely(last_bus == -1))
  429.         return -1;
  430.  
  431.     for(;bus <= last_bus; bus++)
  432.         pci_scan_bus(bus);
  433.  
  434. //    for(dev = (dev_t*)devices.next;
  435. //        &dev->link != &devices;
  436. //        dev = (dev_t*)dev->link.next)
  437. //    {
  438. //        dbgprintf("PCI device %x:%x bus:%x devfn:%x\n",
  439. //                dev->pci_dev.vendor,
  440. //                dev->pci_dev.device,
  441. //                dev->pci_dev.bus,
  442. //                dev->pci_dev.devfn);
  443. //
  444. //    }
  445.     return 0;
  446. }
  447.  
  448. #if 0
  449. /**
  450.  * pci_set_power_state - Set the power state of a PCI device
  451.  * @dev: PCI device to be suspended
  452.  * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
  453.  *
  454.  * Transition a device to a new power state, using the Power Management
  455.  * Capabilities in the device's config space.
  456.  *
  457.  * RETURN VALUE:
  458.  * -EINVAL if trying to enter a lower state than we're already in.
  459.  * 0 if we're already in the requested state.
  460.  * -EIO if device does not support PCI PM.
  461.  * 0 if we can successfully change the power state.
  462.  */
  463. int
  464. pci_set_power_state(struct pci_dev *dev, pci_power_t state)
  465. {
  466.         int pm, need_restore = 0;
  467.         u16 pmcsr, pmc;
  468.  
  469.         /* bound the state we're entering */
  470.         if (state > PCI_D3hot)
  471.                 state = PCI_D3hot;
  472.  
  473.         /*
  474.          * If the device or the parent bridge can't support PCI PM, ignore
  475.          * the request if we're doing anything besides putting it into D0
  476.          * (which would only happen on boot).
  477.          */
  478.         if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
  479.                 return 0;
  480.  
  481.         /* find PCI PM capability in list */
  482.         pm = pci_find_capability(dev, PCI_CAP_ID_PM);
  483.  
  484.         /* abort if the device doesn't support PM capabilities */
  485.         if (!pm)
  486.                 return -EIO;
  487.  
  488.         /* Validate current state:
  489.          * Can enter D0 from any state, but if we can only go deeper
  490.          * to sleep if we're already in a low power state
  491.          */
  492.         if (state != PCI_D0 && dev->current_state > state) {
  493.                 printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
  494.                         __FUNCTION__, pci_name(dev), state, dev->current_state);
  495.                 return -EINVAL;
  496.         } else if (dev->current_state == state)
  497.                 return 0;        /* we're already there */
  498.  
  499.  
  500.         pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
  501.         if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
  502.                 printk(KERN_DEBUG
  503.                        "PCI: %s has unsupported PM cap regs version (%u)\n",
  504.                        pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
  505.                 return -EIO;
  506.         }
  507.  
  508.         /* check if this device supports the desired state */
  509.         if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
  510.                 return -EIO;
  511.         else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
  512.                 return -EIO;
  513.  
  514.         pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
  515.  
  516.         /* If we're (effectively) in D3, force entire word to 0.
  517.          * This doesn't affect PME_Status, disables PME_En, and
  518.          * sets PowerState to 0.
  519.          */
  520.         switch (dev->current_state) {
  521.         case PCI_D0:
  522.         case PCI_D1:
  523.         case PCI_D2:
  524.                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
  525.                 pmcsr |= state;
  526.                 break;
  527.         case PCI_UNKNOWN: /* Boot-up */
  528.                 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
  529.                  && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
  530.                         need_restore = 1;
  531.                 /* Fall-through: force to D0 */
  532.         default:
  533.                 pmcsr = 0;
  534.                 break;
  535.         }
  536.  
  537.         /* enter specified state */
  538.         pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
  539.  
  540.         /* Mandatory power management transition delays */
  541.         /* see PCI PM 1.1 5.6.1 table 18 */
  542.         if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
  543.                 msleep(pci_pm_d3_delay);
  544.         else if (state == PCI_D2 || dev->current_state == PCI_D2)
  545.                 udelay(200);
  546.  
  547.         /*
  548.          * Give firmware a chance to be called, such as ACPI _PRx, _PSx
  549.          * Firmware method after native method ?
  550.          */
  551.         if (platform_pci_set_power_state)
  552.                 platform_pci_set_power_state(dev, state);
  553.  
  554.         dev->current_state = state;
  555.  
  556.         /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
  557.          * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
  558.          * from D3hot to D0 _may_ perform an internal reset, thereby
  559.          * going to "D0 Uninitialized" rather than "D0 Initialized".
  560.          * For example, at least some versions of the 3c905B and the
  561.          * 3c556B exhibit this behaviour.
  562.          *
  563.          * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
  564.          * devices in a D3hot state at boot.  Consequently, we need to
  565.          * restore at least the BARs so that the device will be
  566.          * accessible to its driver.
  567.          */
  568.         if (need_restore)
  569.                 pci_restore_bars(dev);
  570.  
  571.         return 0;
  572. }
  573. #endif
  574.  
  575. int pcibios_enable_resources(struct pci_dev *dev, int mask)
  576. {
  577.     u16_t cmd, old_cmd;
  578.     int  idx;
  579.     struct resource *r;
  580.  
  581.     cmd = PciRead16(dev->bus, dev->devfn, PCI_COMMAND);
  582.     old_cmd = cmd;
  583.     for (idx = 0; idx < PCI_NUM_RESOURCES; idx++)
  584.     {
  585.         /* Only set up the requested stuff */
  586.         if (!(mask & (1 << idx)))
  587.                 continue;
  588.  
  589.         r = &dev->resource[idx];
  590.         if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
  591.                 continue;
  592.         if ((idx == PCI_ROM_RESOURCE) &&
  593.                         (!(r->flags & IORESOURCE_ROM_ENABLE)))
  594.                 continue;
  595.         if (!r->start && r->end) {
  596.                 printk(KERN_ERR "PCI: Device %s not available "
  597.                         "because of resource %d collisions\n",
  598.                         pci_name(dev), idx);
  599.                 return -EINVAL;
  600.         }
  601.         if (r->flags & IORESOURCE_IO)
  602.                 cmd |= PCI_COMMAND_IO;
  603.         if (r->flags & IORESOURCE_MEM)
  604.                 cmd |= PCI_COMMAND_MEMORY;
  605.     }
  606.     if (cmd != old_cmd) {
  607.         printk("PCI: Enabling device %s (%04x -> %04x)\n",
  608.                 pci_name(dev), old_cmd, cmd);
  609.         PciWrite16(dev->bus, dev->devfn, PCI_COMMAND, cmd);
  610.     }
  611.     return 0;
  612. }
  613.  
  614.  
  615. int pcibios_enable_device(struct pci_dev *dev, int mask)
  616. {
  617.         int err;
  618.  
  619.         if ((err = pcibios_enable_resources(dev, mask)) < 0)
  620.                 return err;
  621.  
  622. //        if (!dev->msi_enabled)
  623. //                return pcibios_enable_irq(dev);
  624.         return 0;
  625. }
  626.  
  627.  
  628. static int do_pci_enable_device(struct pci_dev *dev, int bars)
  629. {
  630.         int err;
  631.  
  632. //        err = pci_set_power_state(dev, PCI_D0);
  633. //        if (err < 0 && err != -EIO)
  634. //                return err;
  635.         err = pcibios_enable_device(dev, bars);
  636. //        if (err < 0)
  637. //                return err;
  638. //        pci_fixup_device(pci_fixup_enable, dev);
  639.  
  640.         return 0;
  641. }
  642.  
  643.  
  644. static int __pci_enable_device_flags(struct pci_dev *dev,
  645.                                      resource_size_t flags)
  646. {
  647.         int err;
  648.         int i, bars = 0;
  649.  
  650. //        if (atomic_add_return(1, &dev->enable_cnt) > 1)
  651. //                return 0;               /* already enabled */
  652.  
  653.         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  654.                 if (dev->resource[i].flags & flags)
  655.                         bars |= (1 << i);
  656.  
  657.         err = do_pci_enable_device(dev, bars);
  658. //        if (err < 0)
  659. //                atomic_dec(&dev->enable_cnt);
  660.         return err;
  661. }
  662.  
  663.  
  664. /**
  665.  * pci_enable_device - Initialize device before it's used by a driver.
  666.  * @dev: PCI device to be initialized
  667.  *
  668.  *  Initialize device before it's used by a driver. Ask low-level code
  669.  *  to enable I/O and memory. Wake up the device if it was suspended.
  670.  *  Beware, this function can fail.
  671.  *
  672.  *  Note we don't actually enable the device many times if we call
  673.  *  this function repeatedly (we just increment the count).
  674.  */
  675. int pci_enable_device(struct pci_dev *dev)
  676. {
  677.         return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
  678. }
  679.  
  680.  
  681.  
  682. struct pci_device_id* find_pci_device(dev_t* pdev, struct pci_device_id *idlist)
  683. {
  684.     dev_t *dev;
  685.     struct pci_device_id *ent;
  686.  
  687.     for(dev = (dev_t*)devices.next;
  688.         &dev->link != &devices;
  689.         dev = (dev_t*)dev->link.next)
  690.     {
  691.         if( dev->pci_dev.vendor != idlist->vendor )
  692.             continue;
  693.  
  694.         for(ent = idlist; ent->vendor != 0; ent++)
  695.         {
  696.             if(unlikely(ent->device == dev->pci_dev.device))
  697.             {
  698.                 pdev->pci_dev = dev->pci_dev;
  699.                 return  ent;
  700.             }
  701.         };
  702.     }
  703.  
  704.     return NULL;
  705. };
  706.  
  707.  
  708.  
  709. /**
  710.  * pci_map_rom - map a PCI ROM to kernel space
  711.  * @pdev: pointer to pci device struct
  712.  * @size: pointer to receive size of pci window over ROM
  713.  * @return: kernel virtual pointer to image of ROM
  714.  *
  715.  * Map a PCI ROM into kernel space. If ROM is boot video ROM,
  716.  * the shadow BIOS copy will be returned instead of the
  717.  * actual ROM.
  718.  */
  719.  
  720. #define legacyBIOSLocation 0xC0000
  721. #define OS_BASE   0x80000000
  722.  
  723. void *pci_map_rom(struct pci_dev *pdev, size_t *size)
  724. {
  725.     struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
  726.     u32_t start;
  727.     void  *rom;
  728.  
  729. #if 0
  730.     /*
  731.      * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
  732.      * memory map if the VGA enable bit of the Bridge Control register is
  733.      * set for embedded VGA.
  734.      */
  735.     if (res->flags & IORESOURCE_ROM_SHADOW) {
  736.         /* primary video rom always starts here */
  737.         start = (u32_t)0xC0000;
  738.         *size = 0x20000; /* cover C000:0 through E000:0 */
  739.     } else {
  740.         if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
  741.             *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
  742.              return (void *)(unsigned long)
  743.                      pci_resource_start(pdev, PCI_ROM_RESOURCE);
  744.         } else {
  745.                 /* assign the ROM an address if it doesn't have one */
  746.             //if (res->parent == NULL &&
  747.             //     pci_assign_resource(pdev,PCI_ROM_RESOURCE))
  748.             //         return NULL;
  749.              start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
  750.              *size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
  751.              if (*size == 0)
  752.                      return NULL;
  753.  
  754.              /* Enable ROM space decodes */
  755.              if (pci_enable_rom(pdev))
  756.                      return NULL;
  757.         }
  758.     }
  759.  
  760.     rom = ioremap(start, *size);
  761.     if (!rom) {
  762.             /* restore enable if ioremap fails */
  763.             if (!(res->flags & (IORESOURCE_ROM_ENABLE |
  764.                                 IORESOURCE_ROM_SHADOW |
  765.                                 IORESOURCE_ROM_COPY)))
  766.                     pci_disable_rom(pdev);
  767.             return NULL;
  768.     }
  769.  
  770.     /*
  771.      * Try to find the true size of the ROM since sometimes the PCI window
  772.      * size is much larger than the actual size of the ROM.
  773.      * True size is important if the ROM is going to be copied.
  774.      */
  775.     *size = pci_get_rom_size(rom, *size);
  776.  
  777. #endif
  778.  
  779.     unsigned char tmp[32];
  780.     rom = NULL;
  781.  
  782.     dbgprintf("Getting BIOS copy from legacy VBIOS location\n");
  783.     memcpy(tmp,(char*)(OS_BASE+legacyBIOSLocation), 32);
  784.     *size = tmp[2] * 512;
  785.     if (*size > 0x10000 )
  786.     {
  787.         *size = 0;
  788.         dbgprintf("Invalid BIOS length field\n");
  789.     }
  790.     else
  791.         rom = (void*)( OS_BASE+legacyBIOSLocation);
  792.  
  793.     return rom;
  794. }
  795.  
  796.  
  797. int
  798. pci_set_dma_mask(struct pci_dev *dev, u64 mask)
  799. {
  800. //        if (!pci_dma_supported(dev, mask))
  801. //                return -EIO;
  802.  
  803.         dev->dma_mask = mask;
  804.  
  805.         return 0;
  806. }
  807.  
  808.