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  1. /*
  2.  * Copyright 2007-8 Advanced Micro Devices, Inc.
  3.  * Copyright 2008 Red Hat Inc.
  4.  *
  5.  * Permission is hereby granted, free of charge, to any person obtaining a
  6.  * copy of this software and associated documentation files (the "Software"),
  7.  * to deal in the Software without restriction, including without limitation
  8.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9.  * and/or sell copies of the Software, and to permit persons to whom the
  10.  * Software is furnished to do so, subject to the following conditions:
  11.  *
  12.  * The above copyright notice and this permission notice shall be included in
  13.  * all copies or substantial portions of the Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21.  * OTHER DEALINGS IN THE SOFTWARE.
  22.  *
  23.  * Authors: Dave Airlie
  24.  *          Alex Deucher
  25.  *          Jerome Glisse
  26.  */
  27. #include <drm/drmP.h>
  28. #include <drm/radeon_drm.h>
  29. #include "radeon.h"
  30.  
  31. #include "atom.h"
  32. #include "atom-bits.h"
  33. #include <drm/drm_dp_helper.h>
  34.  
  35. /* move these to drm_dp_helper.c/h */
  36. #define DP_LINK_CONFIGURATION_SIZE 9
  37. #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
  38.  
  39. static char *voltage_names[] = {
  40.         "0.4V", "0.6V", "0.8V", "1.2V"
  41. };
  42. static char *pre_emph_names[] = {
  43.         "0dB", "3.5dB", "6dB", "9.5dB"
  44. };
  45.  
  46. /***** radeon AUX functions *****/
  47.  
  48. /* Atom needs data in little endian format
  49.  * so swap as appropriate when copying data to
  50.  * or from atom. Note that atom operates on
  51.  * dw units.
  52.  */
  53. void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
  54. {
  55. #ifdef __BIG_ENDIAN
  56.         u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
  57.         u32 *dst32, *src32;
  58.         int i;
  59.  
  60.         memcpy(src_tmp, src, num_bytes);
  61.         src32 = (u32 *)src_tmp;
  62.         dst32 = (u32 *)dst_tmp;
  63.         if (to_le) {
  64.                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  65.                         dst32[i] = cpu_to_le32(src32[i]);
  66.                 memcpy(dst, dst_tmp, num_bytes);
  67.         } else {
  68.                 u8 dws = num_bytes & ~3;
  69.                 for (i = 0; i < ((num_bytes + 3) / 4); i++)
  70.                         dst32[i] = le32_to_cpu(src32[i]);
  71.                 memcpy(dst, dst_tmp, dws);
  72.                 if (num_bytes % 4) {
  73.                         for (i = 0; i < (num_bytes % 4); i++)
  74.                                 dst[dws+i] = dst_tmp[dws+i];
  75.                 }
  76.         }
  77. #else
  78.         memcpy(dst, src, num_bytes);
  79. #endif
  80. }
  81.  
  82. union aux_channel_transaction {
  83.         PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
  84.         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
  85. };
  86.  
  87. static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
  88.                                  u8 *send, int send_bytes,
  89.                                  u8 *recv, int recv_size,
  90.                                  u8 delay, u8 *ack)
  91. {
  92.         struct drm_device *dev = chan->dev;
  93.         struct radeon_device *rdev = dev->dev_private;
  94.         union aux_channel_transaction args;
  95.         int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
  96.         unsigned char *base;
  97.         int recv_bytes;
  98.         int r = 0;
  99.  
  100.         memset(&args, 0, sizeof(args));
  101.  
  102.         mutex_lock(&chan->mutex);
  103.  
  104.         base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
  105.  
  106.         radeon_atom_copy_swap(base, send, send_bytes, true);
  107.  
  108.         args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
  109.         args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
  110.         args.v1.ucDataOutLen = 0;
  111.         args.v1.ucChannelID = chan->rec.i2c_id;
  112.         args.v1.ucDelay = delay / 10;
  113.         if (ASIC_IS_DCE4(rdev))
  114.                 args.v2.ucHPD_ID = chan->rec.hpd;
  115.  
  116.         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  117.  
  118.         *ack = args.v1.ucReplyStatus;
  119.  
  120.         /* timeout */
  121.         if (args.v1.ucReplyStatus == 1) {
  122.                 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
  123.                 r = -ETIMEDOUT;
  124.                 goto done;
  125.                         }
  126.  
  127.         /* flags not zero */
  128.         if (args.v1.ucReplyStatus == 2) {
  129.                 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
  130.                 r = -EIO;
  131.                 goto done;
  132.                         }
  133.  
  134.         /* error */
  135.         if (args.v1.ucReplyStatus == 3) {
  136.                 DRM_DEBUG_KMS("dp_aux_ch error\n");
  137.                 r = -EIO;
  138.                 goto done;
  139.                 }
  140.  
  141.         recv_bytes = args.v1.ucDataOutLen;
  142.         if (recv_bytes > recv_size)
  143.                 recv_bytes = recv_size;
  144.  
  145.         if (recv && recv_size)
  146.                 radeon_atom_copy_swap(recv, base + 16, recv_bytes, false);
  147.  
  148.         r = recv_bytes;
  149. done:
  150.         mutex_unlock(&chan->mutex);
  151.  
  152.         return r;
  153. }
  154.  
  155. #define BARE_ADDRESS_SIZE 3
  156. #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
  157.  
  158. static ssize_t
  159. radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
  160. {
  161.         struct radeon_i2c_chan *chan =
  162.                 container_of(aux, struct radeon_i2c_chan, aux);
  163.         int ret;
  164.         u8 tx_buf[20];
  165.         size_t tx_size;
  166.         u8 ack, delay = 0;
  167.  
  168.         if (WARN_ON(msg->size > 16))
  169.                 return -E2BIG;
  170.  
  171.         tx_buf[0] = msg->address & 0xff;
  172.         tx_buf[1] = msg->address >> 8;
  173.         tx_buf[2] = msg->request << 4;
  174.         tx_buf[3] = msg->size ? (msg->size - 1) : 0;
  175.  
  176.         switch (msg->request & ~DP_AUX_I2C_MOT) {
  177.         case DP_AUX_NATIVE_WRITE:
  178.         case DP_AUX_I2C_WRITE:
  179.                 /* tx_size needs to be 4 even for bare address packets since the atom
  180.                  * table needs the info in tx_buf[3].
  181.                  */
  182.                 tx_size = HEADER_SIZE + msg->size;
  183.                 if (msg->size == 0)
  184.                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
  185.                 else
  186.                         tx_buf[3] |= tx_size << 4;
  187.                 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
  188.                 ret = radeon_process_aux_ch(chan,
  189.                                             tx_buf, tx_size, NULL, 0, delay, &ack);
  190.                 if (ret >= 0)
  191.                         /* Return payload size. */
  192.                         ret = msg->size;
  193.                 break;
  194.         case DP_AUX_NATIVE_READ:
  195.         case DP_AUX_I2C_READ:
  196.                 /* tx_size needs to be 4 even for bare address packets since the atom
  197.                  * table needs the info in tx_buf[3].
  198.                  */
  199.                 tx_size = HEADER_SIZE;
  200.                 if (msg->size == 0)
  201.                         tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
  202.                 else
  203.                         tx_buf[3] |= tx_size << 4;
  204.                 ret = radeon_process_aux_ch(chan,
  205.                                             tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
  206.                 break;
  207.         default:
  208.                 ret = -EINVAL;
  209.                 break;
  210.                         }
  211.  
  212.         if (ret >= 0)
  213.                 msg->reply = ack >> 4;
  214.  
  215.                         return ret;
  216. }
  217.  
  218. void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
  219. {
  220.         int ret;
  221.  
  222.         radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
  223.         radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
  224.         radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer;
  225.  
  226.         ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
  227.         if (!ret)
  228.                 radeon_connector->ddc_bus->has_aux = true;
  229.  
  230.         WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
  231. }
  232.  
  233. /***** general DP utility functions *****/
  234.  
  235. #define DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_1200
  236. #define DP_PRE_EMPHASIS_MAX    DP_TRAIN_PRE_EMPHASIS_9_5
  237.  
  238. static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
  239.                                 int lane_count,
  240.                                 u8 train_set[4])
  241. {
  242.         u8 v = 0;
  243.         u8 p = 0;
  244.         int lane;
  245.  
  246.         for (lane = 0; lane < lane_count; lane++) {
  247.                 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
  248.                 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
  249.  
  250.                 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
  251.                           lane,
  252.                           voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
  253.                           pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
  254.  
  255.                 if (this_v > v)
  256.                         v = this_v;
  257.                 if (this_p > p)
  258.                         p = this_p;
  259.         }
  260.  
  261.         if (v >= DP_VOLTAGE_MAX)
  262.                 v |= DP_TRAIN_MAX_SWING_REACHED;
  263.  
  264.         if (p >= DP_PRE_EMPHASIS_MAX)
  265.                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
  266.  
  267.         DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
  268.                   voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
  269.                   pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
  270.  
  271.         for (lane = 0; lane < 4; lane++)
  272.                 train_set[lane] = v | p;
  273. }
  274.  
  275. /* convert bits per color to bits per pixel */
  276. /* get bpc from the EDID */
  277. static int convert_bpc_to_bpp(int bpc)
  278. {
  279.         if (bpc == 0)
  280.                 return 24;
  281.         else
  282.                 return bpc * 3;
  283. }
  284.  
  285. /* get the max pix clock supported by the link rate and lane num */
  286. static int dp_get_max_dp_pix_clock(int link_rate,
  287.                                    int lane_num,
  288.                                    int bpp)
  289. {
  290.         return (link_rate * lane_num * 8) / bpp;
  291. }
  292.  
  293. /***** radeon specific DP functions *****/
  294.  
  295. static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
  296.                                        u8 dpcd[DP_DPCD_SIZE])
  297. {
  298.         int max_link_rate;
  299.  
  300.         if (radeon_connector_is_dp12_capable(connector))
  301.                 max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
  302.         else
  303.                 max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
  304.  
  305.         return max_link_rate;
  306. }
  307.  
  308. /* First get the min lane# when low rate is used according to pixel clock
  309.  * (prefer low rate), second check max lane# supported by DP panel,
  310.  * if the max lane# < low rate lane# then use max lane# instead.
  311.  */
  312. static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
  313.                                         u8 dpcd[DP_DPCD_SIZE],
  314.                                         int pix_clock)
  315. {
  316.         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
  317.         int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
  318.         int max_lane_num = drm_dp_max_lane_count(dpcd);
  319.         int lane_num;
  320.         int max_dp_pix_clock;
  321.  
  322.         for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
  323.                 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
  324.                 if (pix_clock <= max_dp_pix_clock)
  325.                         break;
  326.         }
  327.  
  328.         return lane_num;
  329. }
  330.  
  331. static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
  332.                                        u8 dpcd[DP_DPCD_SIZE],
  333.                                        int pix_clock)
  334. {
  335.         int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
  336.         int lane_num, max_pix_clock;
  337.  
  338.         if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
  339.             ENCODER_OBJECT_ID_NUTMEG)
  340.                 return 270000;
  341.  
  342.         lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
  343.         max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
  344.         if (pix_clock <= max_pix_clock)
  345.                 return 162000;
  346.         max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
  347.         if (pix_clock <= max_pix_clock)
  348.                 return 270000;
  349.         if (radeon_connector_is_dp12_capable(connector)) {
  350.                 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
  351.                 if (pix_clock <= max_pix_clock)
  352.                         return 540000;
  353.         }
  354.  
  355.         return radeon_dp_get_max_link_rate(connector, dpcd);
  356. }
  357.  
  358. static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
  359.                                     int action, int dp_clock,
  360.                                     u8 ucconfig, u8 lane_num)
  361. {
  362.         DP_ENCODER_SERVICE_PARAMETERS args;
  363.         int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
  364.  
  365.         memset(&args, 0, sizeof(args));
  366.         args.ucLinkClock = dp_clock / 10;
  367.         args.ucConfig = ucconfig;
  368.         args.ucAction = action;
  369.         args.ucLaneNum = lane_num;
  370.         args.ucStatus = 0;
  371.  
  372.         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  373.         return args.ucStatus;
  374. }
  375.  
  376. u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
  377. {
  378.         struct drm_device *dev = radeon_connector->base.dev;
  379.         struct radeon_device *rdev = dev->dev_private;
  380.  
  381.         return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
  382.                                          radeon_connector->ddc_bus->rec.i2c_id, 0);
  383. }
  384.  
  385. static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector)
  386. {
  387.         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
  388.         u8 buf[3];
  389.  
  390.         if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
  391.                 return;
  392.  
  393.         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
  394.                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
  395.                               buf[0], buf[1], buf[2]);
  396.  
  397.         if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
  398.                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
  399.                               buf[0], buf[1], buf[2]);
  400. }
  401.  
  402. bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
  403. {
  404.         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
  405.         u8 msg[DP_DPCD_SIZE];
  406.         int ret;
  407.  
  408.         char dpcd_hex_dump[DP_DPCD_SIZE * 3];
  409.  
  410.         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
  411.                                DP_DPCD_SIZE);
  412.         if (ret > 0) {
  413.                 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
  414.  
  415.                 hex_dump_to_buffer(dig_connector->dpcd, sizeof(dig_connector->dpcd),
  416.                                    32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
  417.                 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
  418.  
  419.                 radeon_dp_probe_oui(radeon_connector);
  420.  
  421.                 return true;
  422.         }
  423.         dig_connector->dpcd[0] = 0;
  424.         return false;
  425. }
  426.  
  427. int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
  428.                                      struct drm_connector *connector)
  429. {
  430.         struct drm_device *dev = encoder->dev;
  431.         struct radeon_device *rdev = dev->dev_private;
  432.         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  433.         struct radeon_connector_atom_dig *dig_connector;
  434.         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
  435.         u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
  436.         u8 tmp;
  437.  
  438.         if (!ASIC_IS_DCE4(rdev))
  439.                 return panel_mode;
  440.  
  441.         if (!radeon_connector->con_priv)
  442.                 return panel_mode;
  443.  
  444.         dig_connector = radeon_connector->con_priv;
  445.  
  446.         if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
  447.                 /* DP bridge chips */
  448.                 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
  449.                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
  450.                 if (tmp & 1)
  451.                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
  452.                 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
  453.                          (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
  454.                 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
  455.                 else
  456.                         panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
  457.                 }
  458.         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
  459.                 /* eDP */
  460.                 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
  461.                                       DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
  462.                 if (tmp & 1)
  463.                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
  464.         }
  465.         }
  466.  
  467.         return panel_mode;
  468. }
  469.  
  470. void radeon_dp_set_link_config(struct drm_connector *connector,
  471.                                const struct drm_display_mode *mode)
  472. {
  473.         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  474.         struct radeon_connector_atom_dig *dig_connector;
  475.  
  476.         if (!radeon_connector->con_priv)
  477.                 return;
  478.         dig_connector = radeon_connector->con_priv;
  479.  
  480.         if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
  481.             (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
  482.         dig_connector->dp_clock =
  483.                         radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
  484.         dig_connector->dp_lane_count =
  485.                         radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
  486.         }
  487. }
  488.  
  489. int radeon_dp_mode_valid_helper(struct drm_connector *connector,
  490.                                 struct drm_display_mode *mode)
  491. {
  492.         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  493.         struct radeon_connector_atom_dig *dig_connector;
  494.         int dp_clock;
  495.  
  496.         if (!radeon_connector->con_priv)
  497.                 return MODE_CLOCK_HIGH;
  498.         dig_connector = radeon_connector->con_priv;
  499.  
  500.         dp_clock =
  501.                 radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
  502.  
  503.         if ((dp_clock == 540000) &&
  504.             (!radeon_connector_is_dp12_capable(connector)))
  505.                 return MODE_CLOCK_HIGH;
  506.  
  507.         return MODE_OK;
  508. }
  509.  
  510. bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
  511. {
  512.         u8 link_status[DP_LINK_STATUS_SIZE];
  513.         struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
  514.  
  515.         if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux, link_status)
  516.             <= 0)
  517.                 return false;
  518.         if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
  519.                 return false;
  520.         return true;
  521. }
  522.  
  523. void radeon_dp_set_rx_power_state(struct drm_connector *connector,
  524.                                   u8 power_state)
  525. {
  526.         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  527.         struct radeon_connector_atom_dig *dig_connector;
  528.  
  529.         if (!radeon_connector->con_priv)
  530.                 return;
  531.  
  532.         dig_connector = radeon_connector->con_priv;
  533.  
  534.         /* power up/down the sink */
  535.         if (dig_connector->dpcd[0] >= 0x11) {
  536.                 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
  537.                                    DP_SET_POWER, power_state);
  538.                 usleep_range(1000, 2000);
  539.         }
  540. }
  541.  
  542.  
  543. struct radeon_dp_link_train_info {
  544.         struct radeon_device *rdev;
  545.         struct drm_encoder *encoder;
  546.         struct drm_connector *connector;
  547.         int enc_id;
  548.         int dp_clock;
  549.         int dp_lane_count;
  550.         bool tp3_supported;
  551.         u8 dpcd[DP_RECEIVER_CAP_SIZE];
  552.         u8 train_set[4];
  553.         u8 link_status[DP_LINK_STATUS_SIZE];
  554.         u8 tries;
  555.         bool use_dpencoder;
  556.         struct drm_dp_aux *aux;
  557. };
  558.  
  559. static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
  560. {
  561.         /* set the initial vs/emph on the source */
  562.         atombios_dig_transmitter_setup(dp_info->encoder,
  563.                                        ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
  564.                                        0, dp_info->train_set[0]); /* sets all lanes at once */
  565.  
  566.         /* set the vs/emph on the sink */
  567.         drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
  568.                           dp_info->train_set, dp_info->dp_lane_count);
  569. }
  570.  
  571. static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
  572. {
  573.         int rtp = 0;
  574.  
  575.         /* set training pattern on the source */
  576.         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
  577.                 switch (tp) {
  578.                 case DP_TRAINING_PATTERN_1:
  579.                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
  580.                         break;
  581.                 case DP_TRAINING_PATTERN_2:
  582.                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
  583.                         break;
  584.                 case DP_TRAINING_PATTERN_3:
  585.                         rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
  586.                         break;
  587.                 }
  588.                 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
  589.         } else {
  590.                 switch (tp) {
  591.                 case DP_TRAINING_PATTERN_1:
  592.                         rtp = 0;
  593.                         break;
  594.                 case DP_TRAINING_PATTERN_2:
  595.                         rtp = 1;
  596.                         break;
  597.                 }
  598.                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
  599.                                           dp_info->dp_clock, dp_info->enc_id, rtp);
  600.         }
  601.  
  602.         /* enable training pattern on the sink */
  603.         drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
  604. }
  605.  
  606. static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
  607. {
  608.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
  609.         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  610.         u8 tmp;
  611.  
  612.         /* power up the sink */
  613.         radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
  614.  
  615.         /* possibly enable downspread on the sink */
  616.         if (dp_info->dpcd[3] & 0x1)
  617.                 drm_dp_dpcd_writeb(dp_info->aux,
  618.                                       DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
  619.         else
  620.                 drm_dp_dpcd_writeb(dp_info->aux,
  621.                                       DP_DOWNSPREAD_CTRL, 0);
  622.  
  623.         if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) &&
  624.             (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) {
  625.                 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
  626.         }
  627.  
  628.         /* set the lane count on the sink */
  629.         tmp = dp_info->dp_lane_count;
  630.         if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
  631.                 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
  632.         drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
  633.  
  634.         /* set the link rate on the sink */
  635.         tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
  636.         drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
  637.  
  638.         /* start training on the source */
  639.         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
  640.                 atombios_dig_encoder_setup(dp_info->encoder,
  641.                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
  642.         else
  643.                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
  644.                                           dp_info->dp_clock, dp_info->enc_id, 0);
  645.  
  646.         /* disable the training pattern on the sink */
  647.         drm_dp_dpcd_writeb(dp_info->aux,
  648.                               DP_TRAINING_PATTERN_SET,
  649.                               DP_TRAINING_PATTERN_DISABLE);
  650.  
  651.         return 0;
  652. }
  653.  
  654. static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
  655. {
  656.         udelay(400);
  657.  
  658.         /* disable the training pattern on the sink */
  659.         drm_dp_dpcd_writeb(dp_info->aux,
  660.                               DP_TRAINING_PATTERN_SET,
  661.                               DP_TRAINING_PATTERN_DISABLE);
  662.  
  663.         /* disable the training pattern on the source */
  664.         if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
  665.                 atombios_dig_encoder_setup(dp_info->encoder,
  666.                                            ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
  667.         else
  668.                 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
  669.                                           dp_info->dp_clock, dp_info->enc_id, 0);
  670.  
  671.         return 0;
  672. }
  673.  
  674. static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
  675. {
  676.         bool clock_recovery;
  677.         u8 voltage;
  678.         int i;
  679.  
  680.         radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
  681.         memset(dp_info->train_set, 0, 4);
  682.         radeon_dp_update_vs_emph(dp_info);
  683.  
  684.         udelay(400);
  685.  
  686.         /* clock recovery loop */
  687.         clock_recovery = false;
  688.         dp_info->tries = 0;
  689.         voltage = 0xff;
  690.         while (1) {
  691.                 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
  692.  
  693.                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
  694.                                                  dp_info->link_status) <= 0) {
  695.                         DRM_ERROR("displayport link status failed\n");
  696.                         break;
  697.                 }
  698.  
  699.                 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
  700.                         clock_recovery = true;
  701.                         break;
  702.                 }
  703.  
  704.                 for (i = 0; i < dp_info->dp_lane_count; i++) {
  705.                         if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
  706.                                 break;
  707.                 }
  708.                 if (i == dp_info->dp_lane_count) {
  709.                         DRM_ERROR("clock recovery reached max voltage\n");
  710.                         break;
  711.                 }
  712.  
  713.                 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
  714.                         ++dp_info->tries;
  715.                         if (dp_info->tries == 5) {
  716.                                 DRM_ERROR("clock recovery tried 5 times\n");
  717.                                 break;
  718.                         }
  719.                 } else
  720.                         dp_info->tries = 0;
  721.  
  722.                 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
  723.  
  724.                 /* Compute new train_set as requested by sink */
  725.                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
  726.  
  727.                 radeon_dp_update_vs_emph(dp_info);
  728.         }
  729.         if (!clock_recovery) {
  730.                 DRM_ERROR("clock recovery failed\n");
  731.                 return -1;
  732.         } else {
  733.                 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
  734.                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
  735.                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
  736.                           DP_TRAIN_PRE_EMPHASIS_SHIFT);
  737.                 return 0;
  738.         }
  739. }
  740.  
  741. static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
  742. {
  743.         bool channel_eq;
  744.  
  745.         if (dp_info->tp3_supported)
  746.                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
  747.         else
  748.                 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
  749.  
  750.         /* channel equalization loop */
  751.         dp_info->tries = 0;
  752.         channel_eq = false;
  753.         while (1) {
  754.                 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
  755.  
  756.                 if (drm_dp_dpcd_read_link_status(dp_info->aux,
  757.                                                  dp_info->link_status) <= 0) {
  758.                         DRM_ERROR("displayport link status failed\n");
  759.                         break;
  760.                 }
  761.  
  762.                 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
  763.                         channel_eq = true;
  764.                         break;
  765.                 }
  766.  
  767.                 /* Try 5 times */
  768.                 if (dp_info->tries > 5) {
  769.                         DRM_ERROR("channel eq failed: 5 tries\n");
  770.                         break;
  771.                 }
  772.  
  773.                 /* Compute new train_set as requested by sink */
  774.                 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
  775.  
  776.                 radeon_dp_update_vs_emph(dp_info);
  777.                 dp_info->tries++;
  778.         }
  779.  
  780.         if (!channel_eq) {
  781.                 DRM_ERROR("channel eq failed\n");
  782.                 return -1;
  783.         } else {
  784.                 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
  785.                           dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
  786.                           (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
  787.                           >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
  788.                 return 0;
  789.         }
  790. }
  791.  
  792. void radeon_dp_link_train(struct drm_encoder *encoder,
  793.                           struct drm_connector *connector)
  794. {
  795.         struct drm_device *dev = encoder->dev;
  796.         struct radeon_device *rdev = dev->dev_private;
  797.         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  798.         struct radeon_encoder_atom_dig *dig;
  799.         struct radeon_connector *radeon_connector;
  800.         struct radeon_connector_atom_dig *dig_connector;
  801.         struct radeon_dp_link_train_info dp_info;
  802.         int index;
  803.         u8 tmp, frev, crev;
  804.  
  805.         if (!radeon_encoder->enc_priv)
  806.                 return;
  807.         dig = radeon_encoder->enc_priv;
  808.  
  809.         radeon_connector = to_radeon_connector(connector);
  810.         if (!radeon_connector->con_priv)
  811.                 return;
  812.         dig_connector = radeon_connector->con_priv;
  813.  
  814.         if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
  815.             (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
  816.                 return;
  817.  
  818.         /* DPEncoderService newer than 1.1 can't program properly the
  819.          * training pattern. When facing such version use the
  820.          * DIGXEncoderControl (X== 1 | 2)
  821.          */
  822.         dp_info.use_dpencoder = true;
  823.         index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
  824.         if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
  825.                 if (crev > 1) {
  826.                         dp_info.use_dpencoder = false;
  827.                 }
  828.         }
  829.  
  830.         dp_info.enc_id = 0;
  831.         if (dig->dig_encoder)
  832.                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
  833.         else
  834.                 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
  835.         if (dig->linkb)
  836.                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
  837.         else
  838.                 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
  839.  
  840.         if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
  841.             == 1) {
  842.         if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
  843.                 dp_info.tp3_supported = true;
  844.         else
  845.                 dp_info.tp3_supported = false;
  846.         } else {
  847.                 dp_info.tp3_supported = false;
  848.         }
  849.  
  850.         memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
  851.         dp_info.rdev = rdev;
  852.         dp_info.encoder = encoder;
  853.         dp_info.connector = connector;
  854.         dp_info.dp_lane_count = dig_connector->dp_lane_count;
  855.         dp_info.dp_clock = dig_connector->dp_clock;
  856.         dp_info.aux = &radeon_connector->ddc_bus->aux;
  857.  
  858.         if (radeon_dp_link_train_init(&dp_info))
  859.                 goto done;
  860.         if (radeon_dp_link_train_cr(&dp_info))
  861.                 goto done;
  862.         if (radeon_dp_link_train_ce(&dp_info))
  863.                 goto done;
  864. done:
  865.         if (radeon_dp_link_train_finish(&dp_info))
  866.                 return;
  867. }
  868.