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  1. /*
  2.  * Copyright 2006-2007 Advanced Micro Devices, Inc.
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice shall be included in
  12.  * all copies or substantial portions of the Software.
  13.  *
  14.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17.  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18.  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19.  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20.  * OTHER DEALINGS IN THE SOFTWARE.
  21.  */
  22.  
  23.  
  24. /****************************************************************************/
  25. /*Portion I: Definitions  shared between VBIOS and Driver                   */
  26. /****************************************************************************/
  27.  
  28.  
  29. #ifndef _ATOMBIOS_H
  30. #define _ATOMBIOS_H
  31.  
  32. #define ATOM_VERSION_MAJOR                   0x00020000
  33. #define ATOM_VERSION_MINOR                   0x00000002
  34.  
  35. #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
  36.  
  37. /* Endianness should be specified before inclusion,
  38.  * default to little endian
  39.  */
  40. #ifndef ATOM_BIG_ENDIAN
  41. #error Endian not specified
  42. #endif
  43.  
  44. #ifdef _H2INC
  45.   #ifndef ULONG
  46.     typedef unsigned long ULONG;
  47.   #endif
  48.  
  49.   #ifndef UCHAR
  50.     typedef unsigned char UCHAR;
  51.   #endif
  52.  
  53.   #ifndef USHORT
  54.     typedef unsigned short USHORT;
  55.   #endif
  56. #endif
  57.  
  58. #define ATOM_DAC_A            0
  59. #define ATOM_DAC_B            1
  60. #define ATOM_EXT_DAC          2
  61.  
  62. #define ATOM_CRTC1            0
  63. #define ATOM_CRTC2            1
  64. #define ATOM_CRTC3            2
  65. #define ATOM_CRTC4            3
  66. #define ATOM_CRTC5            4
  67. #define ATOM_CRTC6            5
  68. #define ATOM_CRTC_INVALID     0xFF
  69.  
  70. #define ATOM_DIGA             0
  71. #define ATOM_DIGB             1
  72.  
  73. #define ATOM_PPLL1            0
  74. #define ATOM_PPLL2            1
  75. #define ATOM_DCPLL            2
  76. #define ATOM_PPLL0            2
  77. #define ATOM_EXT_PLL1         8
  78. #define ATOM_EXT_PLL2         9
  79. #define ATOM_EXT_CLOCK        10
  80. #define ATOM_PPLL_INVALID     0xFF
  81.  
  82. #define ENCODER_REFCLK_SRC_P1PLL       0      
  83. #define ENCODER_REFCLK_SRC_P2PLL       1
  84. #define ENCODER_REFCLK_SRC_DCPLL       2
  85. #define ENCODER_REFCLK_SRC_EXTCLK      3
  86. #define ENCODER_REFCLK_SRC_INVALID     0xFF
  87.  
  88. #define ATOM_SCALER1          0
  89. #define ATOM_SCALER2          1
  90.  
  91. #define ATOM_SCALER_DISABLE   0
  92. #define ATOM_SCALER_CENTER    1
  93. #define ATOM_SCALER_EXPANSION 2
  94. #define ATOM_SCALER_MULTI_EX  3
  95.  
  96. #define ATOM_DISABLE          0
  97. #define ATOM_ENABLE           1
  98. #define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)
  99. #define ATOM_LCD_BLON                           (ATOM_ENABLE+2)
  100. #define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)
  101. #define ATOM_LCD_SELFTEST_START                                                                 (ATOM_DISABLE+5)
  102. #define ATOM_LCD_SELFTEST_STOP                                                                  (ATOM_ENABLE+5)
  103. #define ATOM_ENCODER_INIT                                         (ATOM_DISABLE+7)
  104. #define ATOM_GET_STATUS                         (ATOM_DISABLE+8)
  105.  
  106. #define ATOM_BLANKING         1
  107. #define ATOM_BLANKING_OFF     0
  108.  
  109. #define ATOM_CURSOR1          0
  110. #define ATOM_CURSOR2          1
  111.  
  112. #define ATOM_ICON1            0
  113. #define ATOM_ICON2            1
  114.  
  115. #define ATOM_CRT1             0
  116. #define ATOM_CRT2             1
  117.  
  118. #define ATOM_TV_NTSC          1
  119. #define ATOM_TV_NTSCJ         2
  120. #define ATOM_TV_PAL           3
  121. #define ATOM_TV_PALM          4
  122. #define ATOM_TV_PALCN         5
  123. #define ATOM_TV_PALN          6
  124. #define ATOM_TV_PAL60         7
  125. #define ATOM_TV_SECAM         8
  126. #define ATOM_TV_CV            16
  127.  
  128. #define ATOM_DAC1_PS2         1
  129. #define ATOM_DAC1_CV          2
  130. #define ATOM_DAC1_NTSC        3
  131. #define ATOM_DAC1_PAL         4
  132.  
  133. #define ATOM_DAC2_PS2         ATOM_DAC1_PS2
  134. #define ATOM_DAC2_CV          ATOM_DAC1_CV
  135. #define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC
  136. #define ATOM_DAC2_PAL         ATOM_DAC1_PAL
  137.  
  138. #define ATOM_PM_ON            0
  139. #define ATOM_PM_STANDBY       1
  140. #define ATOM_PM_SUSPEND       2
  141. #define ATOM_PM_OFF           3
  142.  
  143. /* Bit0:{=0:single, =1:dual},
  144.    Bit1 {=0:666RGB, =1:888RGB},
  145.    Bit2:3:{Grey level}
  146.    Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/
  147.  
  148. #define ATOM_PANEL_MISC_DUAL               0x00000001
  149. #define ATOM_PANEL_MISC_888RGB             0x00000002
  150. #define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C
  151. #define ATOM_PANEL_MISC_FPDI               0x00000010
  152. #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
  153. #define ATOM_PANEL_MISC_SPATIAL            0x00000020
  154. #define ATOM_PANEL_MISC_TEMPORAL           0x00000040
  155. #define ATOM_PANEL_MISC_API_ENABLED        0x00000080
  156.  
  157.  
  158. #define MEMTYPE_DDR1              "DDR1"
  159. #define MEMTYPE_DDR2              "DDR2"
  160. #define MEMTYPE_DDR3              "DDR3"
  161. #define MEMTYPE_DDR4              "DDR4"
  162.  
  163. #define ASIC_BUS_TYPE_PCI         "PCI"
  164. #define ASIC_BUS_TYPE_AGP         "AGP"
  165. #define ASIC_BUS_TYPE_PCIE        "PCI_EXPRESS"
  166.  
  167. /* Maximum size of that FireGL flag string */
  168.  
  169. #define ATOM_FIREGL_FLAG_STRING     "FGL"             //Flag used to enable FireGL Support
  170. #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING  3        //sizeof( ATOM_FIREGL_FLAG_STRING )
  171.  
  172. #define ATOM_FAKE_DESKTOP_STRING    "DSK"             //Flag used to enable mobile ASIC on Desktop
  173. #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING  ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
  174.  
  175. #define ATOM_M54T_FLAG_STRING       "M54T"            //Flag used to enable M54T Support
  176. #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING    4        //sizeof( ATOM_M54T_FLAG_STRING )
  177.  
  178. #define HW_ASSISTED_I2C_STATUS_FAILURE          2
  179. #define HW_ASSISTED_I2C_STATUS_SUCCESS          1
  180.  
  181. #pragma pack(1)                 /* BIOS data must use byte aligment */
  182.  
  183. /*  Define offset to location of ROM header. */
  184.  
  185. #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER            0x00000048L
  186. #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE                               0x00000002L
  187.  
  188. #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE    0x94
  189. #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE   20      /* including the terminator 0x0! */
  190. #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER           0x002f
  191. #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START            0x006e
  192.  
  193. /* Common header for all ROM Data tables.
  194.   Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header.
  195.   And the pointer actually points to this header. */
  196.  
  197. typedef struct _ATOM_COMMON_TABLE_HEADER
  198. {
  199.         USHORT usStructureSize;
  200.         UCHAR ucTableFormatRevision;    /*Change it when the Parser is not backward compatible */
  201.         UCHAR ucTableContentRevision;   /*Change it only when the table needs to change but the firmware */
  202.         /*Image can't be updated, while Driver needs to carry the new table! */
  203. }ATOM_COMMON_TABLE_HEADER;
  204.  
  205. /****************************************************************************/ 
  206. // Structure stores the ROM header.
  207. /****************************************************************************/ 
  208. typedef struct _ATOM_ROM_HEADER
  209. {
  210.         ATOM_COMMON_TABLE_HEADER sHeader;
  211.         UCHAR uaFirmWareSignature[4];   /*Signature to distinguish between Atombios and non-atombios,
  212.                                            atombios should init it as "ATOM", don't change the position */
  213.         USHORT usBiosRuntimeSegmentAddress;
  214.         USHORT usProtectedModeInfoOffset;
  215.         USHORT usConfigFilenameOffset;
  216.         USHORT usCRC_BlockOffset;
  217.         USHORT usBIOS_BootupMessageOffset;
  218.         USHORT usInt10Offset;
  219.         USHORT usPciBusDevInitCode;
  220.         USHORT usIoBaseAddress;
  221.         USHORT usSubsystemVendorID;
  222.         USHORT usSubsystemID;
  223.         USHORT usPCI_InfoOffset;
  224.         USHORT usMasterCommandTableOffset;      /*Offset for SW to get all command table offsets, Don't change the position */
  225.         USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */
  226.         UCHAR ucExtendedFunctionCode;
  227.         UCHAR ucReserved;
  228. }ATOM_ROM_HEADER;
  229.  
  230. /*==============================Command Table Portion==================================== */
  231.  
  232. #ifdef  UEFI_BUILD
  233.         #define UTEMP   USHORT
  234.         #define USHORT  void*
  235. #endif
  236.  
  237. /****************************************************************************/ 
  238. // Structures used in Command.mtb
  239. /****************************************************************************/ 
  240. typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
  241.   USHORT ASIC_Init;                              //Function Table, used by various SW components,latest version 1.1
  242.   USHORT GetDisplaySurfaceSize;                  //Atomic Table,  Used by Bios when enabling HW ICON
  243.   USHORT ASIC_RegistersInit;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
  244.   USHORT VRAM_BlockVenderDetection;              //Atomic Table,  used only by Bios
  245.   USHORT DIGxEncoderControl;                                                                             //Only used by Bios
  246.   USHORT MemoryControllerInit;                   //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
  247.   USHORT EnableCRTCMemReq;                       //Function Table,directly used by various SW components,latest version 2.1
  248.   USHORT MemoryParamAdjust;                                                                              //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed
  249.   USHORT DVOEncoderControl;                      //Function Table,directly used by various SW components,latest version 1.2
  250.   USHORT GPIOPinControl;                                                                                                 //Atomic Table,  only used by Bios
  251.   USHORT SetEngineClock;                         //Function Table,directly used by various SW components,latest version 1.1
  252.   USHORT SetMemoryClock;                         //Function Table,directly used by various SW components,latest version 1.1
  253.   USHORT SetPixelClock;                          //Function Table,directly used by various SW components,latest version 1.2  
  254.   USHORT DynamicClockGating;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
  255.   USHORT ResetMemoryDLL;                         //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
  256.   USHORT ResetMemoryDevice;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
  257.         USHORT MemoryPLLInit;
  258.   USHORT AdjustDisplayPll;                                                                                              //only used by Bios
  259.   USHORT AdjustMemoryController;                 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock                
  260.   USHORT EnableASIC_StaticPwrMgt;                //Atomic Table,  only used by Bios
  261.   USHORT ASIC_StaticPwrMgtStatusChange;          //Obsolete ,     only used by Bios  
  262.   USHORT DAC_LoadDetection;                      //Atomic Table,  directly used by various SW components,latest version 1.2  
  263.   USHORT LVTMAEncoderControl;                    //Atomic Table,directly used by various SW components,latest version 1.3
  264.   USHORT LCD1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
  265.   USHORT DAC1EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1  
  266.   USHORT DAC2EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
  267.   USHORT DVOOutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1
  268.   USHORT CV1OutputControl;                       //Atomic Table,  Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead
  269.   USHORT GetConditionalGoldenSetting;            //only used by Bios
  270.   USHORT TVEncoderControl;                       //Function Table,directly used by various SW components,latest version 1.1
  271.   USHORT TMDSAEncoderControl;                    //Atomic Table,  directly used by various SW components,latest version 1.3
  272.   USHORT LVDSEncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.3
  273.   USHORT TV1OutputControl;                       //Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead
  274.   USHORT EnableScaler;                           //Atomic Table,  used only by Bios
  275.   USHORT BlankCRTC;                              //Atomic Table,  directly used by various SW components,latest version 1.1
  276.   USHORT EnableCRTC;                             //Atomic Table,  directly used by various SW components,latest version 1.1
  277.   USHORT GetPixelClock;                          //Atomic Table,  directly used by various SW components,latest version 1.1
  278.   USHORT EnableVGA_Render;                       //Function Table,directly used by various SW components,latest version 1.1
  279.   USHORT GetSCLKOverMCLKRatio;                   //Atomic Table,  only used by Bios
  280.   USHORT SetCRTC_Timing;                         //Atomic Table,  directly used by various SW components,latest version 1.1
  281.   USHORT SetCRTC_OverScan;                       //Atomic Table,  used by various SW components,latest version 1.1
  282.   USHORT SetCRTC_Replication;                    //Atomic Table,  used only by Bios
  283.   USHORT SelectCRTC_Source;                      //Atomic Table,  directly used by various SW components,latest version 1.1
  284.   USHORT EnableGraphSurfaces;                    //Atomic Table,  used only by Bios
  285.         USHORT UpdateCRTC_DoubleBufferRegisters;
  286.   USHORT LUT_AutoFill;                           //Atomic Table,  only used by Bios
  287.   USHORT EnableHW_IconCursor;                    //Atomic Table,  only used by Bios
  288.   USHORT GetMemoryClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
  289.   USHORT GetEngineClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
  290.   USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
  291.   USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
  292.   USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
  293.   USHORT VRAM_BlockDetectionByStrap;             //Atomic Table,  used only by Bios
  294.   USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios    
  295.   USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
  296.   USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components
  297.   USHORT ReadHWAssistedI2CStatus;                //Atomic Table,  indirectly used by various SW components
  298.   USHORT SpeedFanControl;                        //Function Table,indirectly used by various SW components,called from ASIC_Init
  299.   USHORT PowerConnectorDetection;                //Atomic Table,  directly used by various SW components,latest version 1.1
  300.   USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
  301.   USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
  302.   USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
  303.   USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
  304.   USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
  305.   USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
  306.   USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
  307.   USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
  308.   USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
  309.   USHORT DAC1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
  310.   USHORT DAC2OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
  311.   USHORT SetupHWAssistedI2CStatus;               //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
  312.   USHORT ClockSource;                            //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
  313.   USHORT MemoryDeviceInit;                       //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
  314.   USHORT EnableYUV;                              //Atomic Table,  indirectly used by various SW components,called from EnableVGARender
  315.   USHORT DIG1EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
  316.   USHORT DIG2EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
  317.   USHORT DIG1TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
  318.   USHORT DIG2TransmitterControl;                       //Atomic Table,directly used by various SW components,latest version 1.1
  319.   USHORT ProcessAuxChannelTransaction;                                   //Function Table,only used by Bios
  320.   USHORT DPEncoderService;                                                                                       //Function Table,only used by Bios
  321. }ATOM_MASTER_LIST_OF_COMMAND_TABLES;  
  322.  
  323. // For backward compatible
  324. #define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
  325. #define UNIPHYTransmitterControl                                                     DIG1TransmitterControl
  326. #define LVTMATransmitterControl                                                      DIG2TransmitterControl
  327. #define SetCRTC_DPM_State                        GetConditionalGoldenSetting
  328. #define SetUniphyInstance                        ASIC_StaticPwrMgtStatusChange
  329. #define HPDInterruptService                      ReadHWAssistedI2CStatus
  330. #define EnableVGA_Access                         GetSCLKOverMCLKRatio
  331. #define GetDispObjectInfo                        EnableYUV
  332.  
  333. typedef struct _ATOM_MASTER_COMMAND_TABLE
  334. {
  335.         ATOM_COMMON_TABLE_HEADER sHeader;
  336.         ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
  337. }ATOM_MASTER_COMMAND_TABLE;
  338.  
  339. /****************************************************************************/
  340. // Structures used in every command table
  341. /****************************************************************************/
  342. typedef struct _ATOM_TABLE_ATTRIBUTE
  343. {
  344. #if ATOM_BIG_ENDIAN
  345.   USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
  346.   USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword),
  347.   USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword),
  348. #else
  349.   USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword),
  350.   USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword),
  351.   USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
  352. #endif
  353. }ATOM_TABLE_ATTRIBUTE;
  354.  
  355. typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
  356. {
  357.         ATOM_TABLE_ATTRIBUTE sbfAccess;
  358.         USHORT susAccess;
  359. }ATOM_TABLE_ATTRIBUTE_ACCESS;
  360.  
  361. /****************************************************************************/
  362. // Common header for all command tables.
  363. // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
  364. // And the pointer actually points to this header.
  365. /****************************************************************************/
  366. typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
  367. {
  368.         ATOM_COMMON_TABLE_HEADER CommonHeader;
  369.         ATOM_TABLE_ATTRIBUTE TableAttribute;
  370. }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
  371.  
  372. /****************************************************************************/
  373. // Structures used by ComputeMemoryEnginePLLTable
  374. /****************************************************************************/
  375. #define COMPUTE_MEMORY_PLL_PARAM        1
  376. #define COMPUTE_ENGINE_PLL_PARAM        2
  377. #define ADJUST_MC_SETTING_PARAM         3
  378.  
  379. /****************************************************************************/ 
  380. // Structures used by AdjustMemoryControllerTable
  381. /****************************************************************************/ 
  382. typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
  383. {
  384. #if ATOM_BIG_ENDIAN
  385.   ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
  386.   ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
  387.   ULONG ulClockFreq:24;
  388. #else
  389.   ULONG ulClockFreq:24;
  390.   ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
  391.   ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
  392. #endif
  393. }ATOM_ADJUST_MEMORY_CLOCK_FREQ;
  394. #define POINTER_RETURN_FLAG             0x80
  395.  
  396. typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
  397. {
  398.   ULONG   ulClock;        //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
  399.   UCHAR   ucAction;       //0:reserved //1:Memory //2:Engine  
  400.   UCHAR   ucReserved;     //may expand to return larger Fbdiv later
  401.   UCHAR   ucFbDiv;        //return value
  402.   UCHAR   ucPostDiv;      //return value
  403. }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
  404.  
  405. typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
  406. {
  407.   ULONG   ulClock;        //When return, [23:0] return real clock
  408.   UCHAR   ucAction;       //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
  409.   USHORT  usFbDiv;                  //return Feedback value to be written to register
  410.   UCHAR   ucPostDiv;      //return post div to be written to register
  411. }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
  412. #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
  413.  
  414.  
  415. #define SET_CLOCK_FREQ_MASK                     0x00FFFFFF  //Clock change tables only take bit [23:0] as the requested clock value
  416. #define USE_NON_BUS_CLOCK_MASK                  0x01000000  //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
  417. #define USE_MEMORY_SELF_REFRESH_MASK            0x02000000      //Only applicable to memory clock change, when set, using memory self refresh during clock transition
  418. #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04000000  //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
  419. #define FIRST_TIME_CHANGE_CLOCK                                                                 0x08000000      //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
  420. #define SKIP_SW_PROGRAM_PLL                                                                                     0x10000000      //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
  421. #define USE_SS_ENABLED_PIXEL_CLOCK  USE_NON_BUS_CLOCK_MASK
  422.  
  423. #define b3USE_NON_BUS_CLOCK_MASK                  0x01       //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
  424. #define b3USE_MEMORY_SELF_REFRESH                 0x02       //Only applicable to memory clock change, when set, using memory self refresh during clock transition
  425. #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04       //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
  426. #define b3FIRST_TIME_CHANGE_CLOCK                                                                       0x08       //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
  427. #define b3SKIP_SW_PROGRAM_PLL                                                                                   0x10                     //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
  428.  
  429. typedef struct _ATOM_COMPUTE_CLOCK_FREQ
  430. {
  431. #if ATOM_BIG_ENDIAN
  432.   ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
  433.   ULONG ulClockFreq:24;                       // in unit of 10kHz
  434. #else
  435.   ULONG ulClockFreq:24;                       // in unit of 10kHz
  436.   ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
  437. #endif
  438. }ATOM_COMPUTE_CLOCK_FREQ;
  439.  
  440. typedef struct _ATOM_S_MPLL_FB_DIVIDER
  441. {
  442.         USHORT usFbDivFrac;
  443.         USHORT usFbDiv;
  444. }ATOM_S_MPLL_FB_DIVIDER;
  445.  
  446. typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
  447. {
  448.   union
  449.   {
  450.     ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
  451.     ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
  452.         };
  453.   UCHAR   ucRefDiv;                           //Output Parameter      
  454.   UCHAR   ucPostDiv;                          //Output Parameter      
  455.   UCHAR   ucCntlFlag;                         //Output Parameter      
  456.         UCHAR ucReserved;
  457. }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
  458.  
  459. // ucCntlFlag
  460. #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN          1
  461. #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE            2
  462. #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE         4
  463. #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9                                                8
  464.  
  465.  
  466. // V4 are only used for APU which PLL outside GPU
  467. typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
  468. {
  469. #if ATOM_BIG_ENDIAN
  470.   ULONG  ucPostDiv;          //return parameter: post divider which is used to program to register directly
  471.   ULONG  ulClock:24;         //Input= target clock, output = actual clock
  472. #else
  473.   ULONG  ulClock:24;         //Input= target clock, output = actual clock
  474.   ULONG  ucPostDiv;          //return parameter: post divider which is used to program to register directly
  475. #endif
  476. }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
  477.  
  478. typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
  479. {
  480.   union
  481.   {
  482.     ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
  483.     ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
  484.   };
  485.   UCHAR   ucRefDiv;                           //Output Parameter      
  486.   UCHAR   ucPostDiv;                          //Output Parameter      
  487.   union
  488.   {
  489.     UCHAR   ucCntlFlag;                       //Output Flags
  490.     UCHAR   ucInputFlag;                      //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
  491.   };
  492.   UCHAR   ucReserved;                      
  493. }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
  494.  
  495. // ucInputFlag
  496. #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN  1   // 1-StrobeMode, 0-PerformanceMode
  497.  
  498. typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
  499. {
  500.         ATOM_COMPUTE_CLOCK_FREQ ulClock;
  501.         ULONG ulReserved[2];
  502. }DYNAMICE_MEMORY_SETTINGS_PARAMETER;
  503.  
  504. typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
  505. {
  506.         ATOM_COMPUTE_CLOCK_FREQ ulClock;
  507.         ULONG ulMemoryClock;
  508.         ULONG ulReserved;
  509. }DYNAMICE_ENGINE_SETTINGS_PARAMETER;
  510.  
  511. /****************************************************************************/
  512. // Structures used by SetEngineClockTable
  513. /****************************************************************************/
  514. typedef struct _SET_ENGINE_CLOCK_PARAMETERS
  515. {
  516.   ULONG ulTargetEngineClock;          //In 10Khz unit
  517. }SET_ENGINE_CLOCK_PARAMETERS;
  518.  
  519. typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
  520. {
  521.   ULONG ulTargetEngineClock;          //In 10Khz unit
  522.         COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
  523. }SET_ENGINE_CLOCK_PS_ALLOCATION;
  524.  
  525. /****************************************************************************/
  526. // Structures used by SetMemoryClockTable
  527. /****************************************************************************/
  528. typedef struct _SET_MEMORY_CLOCK_PARAMETERS
  529. {
  530.   ULONG ulTargetMemoryClock;          //In 10Khz unit
  531. }SET_MEMORY_CLOCK_PARAMETERS;
  532.  
  533. typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
  534. {
  535.   ULONG ulTargetMemoryClock;          //In 10Khz unit
  536.         COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
  537. }SET_MEMORY_CLOCK_PS_ALLOCATION;
  538.  
  539. /****************************************************************************/
  540. // Structures used by ASIC_Init.ctb
  541. /****************************************************************************/
  542. typedef struct _ASIC_INIT_PARAMETERS
  543. {
  544.   ULONG ulDefaultEngineClock;         //In 10Khz unit
  545.   ULONG ulDefaultMemoryClock;         //In 10Khz unit
  546. }ASIC_INIT_PARAMETERS;
  547.  
  548. typedef struct _ASIC_INIT_PS_ALLOCATION
  549. {
  550.         ASIC_INIT_PARAMETERS sASICInitClocks;
  551.   SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
  552. }ASIC_INIT_PS_ALLOCATION;
  553.  
  554. /****************************************************************************/
  555. // Structure used by DynamicClockGatingTable.ctb
  556. /****************************************************************************/
  557. typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
  558. {
  559.   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
  560.         UCHAR ucPadding[3];
  561. }DYNAMIC_CLOCK_GATING_PARAMETERS;
  562. #define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS
  563.  
  564. /****************************************************************************/
  565. // Structure used by EnableASIC_StaticPwrMgtTable.ctb
  566. /****************************************************************************/
  567. typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
  568. {
  569.   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
  570.         UCHAR ucPadding[3];
  571. }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
  572. #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
  573.  
  574. /****************************************************************************/
  575. // Structures used by DAC_LoadDetectionTable.ctb
  576. /****************************************************************************/
  577. typedef struct _DAC_LOAD_DETECTION_PARAMETERS
  578. {
  579.   USHORT usDeviceID;                  //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
  580.   UCHAR  ucDacType;                   //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
  581.   UCHAR  ucMisc;                                                                                        //Valid only when table revision =1.3 and above
  582. }DAC_LOAD_DETECTION_PARAMETERS;
  583.  
  584. // DAC_LOAD_DETECTION_PARAMETERS.ucMisc
  585. #define DAC_LOAD_MISC_YPrPb                                             0x01
  586.  
  587. typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
  588. {
  589.         DAC_LOAD_DETECTION_PARAMETERS sDacload;
  590.   ULONG                                    Reserved[2];// Don't set this one, allocation for EXT DAC
  591. }DAC_LOAD_DETECTION_PS_ALLOCATION;
  592.  
  593. /****************************************************************************/
  594. // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
  595. /****************************************************************************/
  596. typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
  597. {
  598.   USHORT usPixelClock;                // in 10KHz; for bios convenient
  599.   UCHAR  ucDacStandard;               // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
  600.   UCHAR  ucAction;                    // 0: turn off encoder
  601.                                       // 1: setup and turn on encoder
  602.                                       // 7: ATOM_ENCODER_INIT Initialize DAC
  603. }DAC_ENCODER_CONTROL_PARAMETERS;
  604.  
  605. #define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS
  606.  
  607. /****************************************************************************/
  608. // Structures used by DIG1EncoderControlTable
  609. //                    DIG2EncoderControlTable
  610. //                    ExternalEncoderControlTable
  611. /****************************************************************************/
  612. typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
  613. {
  614.   USHORT usPixelClock;          // in 10KHz; for bios convenient
  615.         UCHAR ucConfig;
  616.                             // [2] Link Select:
  617.                             // =0: PHY linkA if bfLane<3
  618.                             // =1: PHY linkB if bfLanes<3
  619.                             // =0: PHY linkA+B if bfLanes=3
  620.                             // [3] Transmitter Sel
  621.                             // =0: UNIPHY or PCIEPHY
  622.                             // =1: LVTMA                                       
  623.   UCHAR ucAction;           // =0: turn off encoder                                    
  624.                             // =1: turn on encoder                     
  625.         UCHAR ucEncoderMode;
  626.                             // =0: DP   encoder      
  627.                             // =1: LVDS encoder          
  628.                             // =2: DVI  encoder  
  629.                             // =3: HDMI encoder
  630.                             // =4: SDVO encoder
  631.   UCHAR ucLaneNum;          // how many lanes to enable
  632.         UCHAR ucReserved[2];
  633. }DIG_ENCODER_CONTROL_PARAMETERS;
  634. #define DIG_ENCODER_CONTROL_PS_ALLOCATION                         DIG_ENCODER_CONTROL_PARAMETERS
  635. #define EXTERNAL_ENCODER_CONTROL_PARAMETER                      DIG_ENCODER_CONTROL_PARAMETERS
  636.  
  637. //ucConfig
  638. #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK                             0x01
  639. #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ          0x00
  640. #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ          0x01
  641. #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ          0x02
  642. #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK                                 0x04
  643. #define ATOM_ENCODER_CONFIG_LINKA                                                                 0x00
  644. #define ATOM_ENCODER_CONFIG_LINKB                                                                 0x04
  645. #define ATOM_ENCODER_CONFIG_LINKA_B                                                       ATOM_TRANSMITTER_CONFIG_LINKA
  646. #define ATOM_ENCODER_CONFIG_LINKB_A                                                       ATOM_ENCODER_CONFIG_LINKB
  647. #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK        0x08
  648. #define ATOM_ENCODER_CONFIG_UNIPHY                                                        0x00
  649. #define ATOM_ENCODER_CONFIG_LVTMA                                                                 0x08
  650. #define ATOM_ENCODER_CONFIG_TRANSMITTER1                                  0x00
  651. #define ATOM_ENCODER_CONFIG_TRANSMITTER2                                  0x08
  652. #define ATOM_ENCODER_CONFIG_DIGB                                                                  0x80                  // VBIOS Internal use, outside SW should set this bit=0
  653. // ucAction
  654. // ATOM_ENABLE:  Enable Encoder
  655. // ATOM_DISABLE: Disable Encoder
  656.  
  657. //ucEncoderMode
  658. #define ATOM_ENCODER_MODE_DP                                                                                    0
  659. #define ATOM_ENCODER_MODE_LVDS                                                                          1
  660. #define ATOM_ENCODER_MODE_DVI                                                                                   2
  661. #define ATOM_ENCODER_MODE_HDMI                                                                          3
  662. #define ATOM_ENCODER_MODE_SDVO                                                                          4
  663. #define ATOM_ENCODER_MODE_DP_AUDIO                5
  664. #define ATOM_ENCODER_MODE_TV                                                                                    13
  665. #define ATOM_ENCODER_MODE_CV                                                                                    14
  666. #define ATOM_ENCODER_MODE_CRT                                                                                   15
  667. #define ATOM_ENCODER_MODE_DVO                                                                                   16
  668. #define ATOM_ENCODER_MODE_DP_SST                  ATOM_ENCODER_MODE_DP    // For DP1.2
  669. #define ATOM_ENCODER_MODE_DP_MST                  5                       // For DP1.2
  670.  
  671. typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
  672. {
  673. #if ATOM_BIG_ENDIAN
  674.         UCHAR ucReserved1:2;
  675.     UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
  676.     UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
  677.         UCHAR ucReserved:1;
  678.     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
  679. #else
  680.     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
  681.         UCHAR ucReserved:1;
  682.     UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
  683.     UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
  684.         UCHAR ucReserved1:2;
  685. #endif
  686. }ATOM_DIG_ENCODER_CONFIG_V2;
  687.  
  688.  
  689. typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
  690. {
  691.   USHORT usPixelClock;      // in 10KHz; for bios convenient
  692.         ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
  693.         UCHAR ucAction;
  694.         UCHAR ucEncoderMode;
  695.                             // =0: DP   encoder      
  696.                             // =1: LVDS encoder          
  697.                             // =2: DVI  encoder  
  698.                             // =3: HDMI encoder
  699.                             // =4: SDVO encoder
  700.   UCHAR ucLaneNum;          // how many lanes to enable
  701.   UCHAR ucStatus;           // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
  702.   UCHAR ucReserved;
  703. }DIG_ENCODER_CONTROL_PARAMETERS_V2;
  704.  
  705. //ucConfig
  706. #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK                          0x01
  707. #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ                 0x00
  708. #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ                 0x01
  709. #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK                              0x04
  710. #define ATOM_ENCODER_CONFIG_V2_LINKA                                                              0x00
  711. #define ATOM_ENCODER_CONFIG_V2_LINKB                                                              0x04
  712. #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK       0x18
  713. #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1                                 0x00
  714. #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2                                 0x08
  715. #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3                                 0x10
  716.  
  717. // ucAction:
  718. // ATOM_DISABLE
  719. // ATOM_ENABLE
  720. #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       0x08
  721. #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    0x09
  722. #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    0x0a
  723. #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3    0x13
  724. #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    0x0b
  725. #define ATOM_ENCODER_CMD_DP_VIDEO_OFF                 0x0c
  726. #define ATOM_ENCODER_CMD_DP_VIDEO_ON                  0x0d
  727. #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS    0x0e
  728. #define ATOM_ENCODER_CMD_SETUP                        0x0f
  729. #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE             0x10
  730.  
  731. // ucStatus
  732. #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE    0x10
  733. #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE  0x00
  734.  
  735. //ucTableFormatRevision=1
  736. //ucTableContentRevision=3
  737. // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
  738. typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
  739. {
  740. #if ATOM_BIG_ENDIAN
  741.     UCHAR ucReserved1:1;
  742.     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
  743.     UCHAR ucReserved:3;
  744.     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
  745. #else
  746.     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
  747.     UCHAR ucReserved:3;
  748.     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
  749.     UCHAR ucReserved1:1;
  750. #endif
  751. }ATOM_DIG_ENCODER_CONFIG_V3;
  752.  
  753. #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK                          0x03
  754. #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ                 0x00
  755. #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ                 0x01
  756. #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL                                        0x70
  757. #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER                                       0x00
  758. #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER                                       0x10
  759. #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER                                       0x20
  760. #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER                                       0x30
  761. #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER                                       0x40
  762. #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER                                       0x50
  763.  
  764. typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
  765. {
  766.   USHORT usPixelClock;      // in 10KHz; for bios convenient
  767.   ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
  768.   UCHAR ucAction;                              
  769.   union {
  770.   UCHAR ucEncoderMode;
  771.                             // =0: DP   encoder      
  772.                             // =1: LVDS encoder          
  773.                             // =2: DVI  encoder  
  774.                             // =3: HDMI encoder
  775.                             // =4: SDVO encoder
  776.                             // =5: DP audio
  777.     UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
  778.                             // =0:     external DP
  779.                             // =1:     internal DP2
  780.                             // =0x11:  internal DP1 for NutMeg/Travis DP translator
  781.   };
  782.   UCHAR ucLaneNum;          // how many lanes to enable
  783.   UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
  784.   UCHAR ucReserved;
  785. }DIG_ENCODER_CONTROL_PARAMETERS_V3;
  786.  
  787. //ucTableFormatRevision=1
  788. //ucTableContentRevision=4
  789. // start from NI          
  790. // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
  791. typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
  792. {
  793. #if ATOM_BIG_ENDIAN
  794.     UCHAR ucReserved1:1;
  795.     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
  796.     UCHAR ucReserved:2;
  797.     UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
  798. #else
  799.     UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
  800.     UCHAR ucReserved:2;
  801.     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
  802.     UCHAR ucReserved1:1;
  803. #endif
  804. }ATOM_DIG_ENCODER_CONFIG_V4;
  805.  
  806. #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK                          0x03
  807. #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ                 0x00
  808. #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ                 0x01
  809. #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ                 0x02
  810. #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL                                        0x70
  811. #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER                                       0x00
  812. #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER                                       0x10
  813. #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER                                       0x20
  814. #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER                                       0x30
  815. #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER                                       0x40
  816. #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER                                       0x50
  817.  
  818. typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
  819. {
  820.   USHORT usPixelClock;      // in 10KHz; for bios convenient
  821.   union{
  822.   ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
  823.   UCHAR ucConfig;
  824.   };
  825.   UCHAR ucAction;                              
  826.   union {
  827.   UCHAR ucEncoderMode;
  828.                             // =0: DP   encoder      
  829.                             // =1: LVDS encoder          
  830.                             // =2: DVI  encoder  
  831.                             // =3: HDMI encoder
  832.                             // =4: SDVO encoder
  833.                             // =5: DP audio
  834.     UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
  835.                             // =0:     external DP
  836.                             // =1:     internal DP2
  837.                             // =0x11:  internal DP1 for NutMeg/Travis DP translator
  838.   };
  839.   UCHAR ucLaneNum;          // how many lanes to enable
  840.   UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
  841.   UCHAR ucHPD_ID;           // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
  842. }DIG_ENCODER_CONTROL_PARAMETERS_V4;
  843.  
  844. // define ucBitPerColor:
  845. #define PANEL_BPC_UNDEFINE                               0x00
  846. #define PANEL_6BIT_PER_COLOR                             0x01
  847. #define PANEL_8BIT_PER_COLOR                             0x02
  848. #define PANEL_10BIT_PER_COLOR                            0x03
  849. #define PANEL_12BIT_PER_COLOR                            0x04
  850. #define PANEL_16BIT_PER_COLOR                            0x05
  851.  
  852. //define ucPanelMode
  853. #define DP_PANEL_MODE_EXTERNAL_DP_MODE                   0x00
  854. #define DP_PANEL_MODE_INTERNAL_DP2_MODE                  0x01
  855. #define DP_PANEL_MODE_INTERNAL_DP1_MODE                  0x11
  856.  
  857. /****************************************************************************/
  858. // Structures used by UNIPHYTransmitterControlTable
  859. //                    LVTMATransmitterControlTable
  860. //                    DVOOutputControlTable
  861. /****************************************************************************/
  862. typedef struct _ATOM_DP_VS_MODE
  863. {
  864.         UCHAR ucLaneSel;
  865.         UCHAR ucLaneSet;
  866. }ATOM_DP_VS_MODE;
  867.  
  868. typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
  869. {
  870.         union
  871.         {
  872.   USHORT usPixelClock;          // in 10KHz; for bios convenient
  873.         USHORT usInitInfo;                      // when init uniphy,lower 8bit is used for connector type defined in objectid.h
  874.   ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
  875.         };
  876.         UCHAR ucConfig;
  877.                                                                                                         // [0]=0: 4 lane Link,      
  878.                                                                                                         //    =1: 8 lane Link ( Dual Links TMDS )
  879.                           // [1]=0: InCoherent mode  
  880.                                                                                                         //    =1: Coherent Mode                                                                        
  881.                                                                                                         // [2] Link Select:
  882.                                                                                                 // =0: PHY linkA   if bfLane<3
  883.                                                                                                         // =1: PHY linkB   if bfLanes<3
  884.                                                                                                 // =0: PHY linkA+B if bfLanes=3        
  885.                           // [5:4]PCIE lane Sel
  886.                           // =0: lane 0~3 or 0~7
  887.                           // =1: lane 4~7
  888.                           // =2: lane 8~11 or 8~15
  889.                           // =3: lane 12~15
  890.         UCHAR ucAction;                           // =0: turn off encoder                                      
  891.                                 // =1: turn on encoder                 
  892.         UCHAR ucReserved[4];
  893. }DIG_TRANSMITTER_CONTROL_PARAMETERS;
  894.  
  895. #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION           DIG_TRANSMITTER_CONTROL_PARAMETERS
  896.  
  897. //ucInitInfo
  898. #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK  0x00ff
  899.  
  900. //ucConfig
  901. #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK                      0x01
  902. #define ATOM_TRANSMITTER_CONFIG_COHERENT                                0x02
  903. #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK           0x04
  904. #define ATOM_TRANSMITTER_CONFIG_LINKA                                           0x00
  905. #define ATOM_TRANSMITTER_CONFIG_LINKB                                           0x04
  906. #define ATOM_TRANSMITTER_CONFIG_LINKA_B                                 0x00
  907. #define ATOM_TRANSMITTER_CONFIG_LINKB_A                                 0x04
  908.  
  909. #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK        0x08                    // only used when ATOM_TRANSMITTER_ACTION_ENABLE
  910. #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER            0x00                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
  911. #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER            0x08                            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
  912.  
  913. #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK                     0x30
  914. #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL                     0x00
  915. #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE                     0x20
  916. #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN           0x30
  917. #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK           0xc0
  918. #define ATOM_TRANSMITTER_CONFIG_LANE_0_3                                0x00
  919. #define ATOM_TRANSMITTER_CONFIG_LANE_0_7                                0x00
  920. #define ATOM_TRANSMITTER_CONFIG_LANE_4_7                                0x40
  921. #define ATOM_TRANSMITTER_CONFIG_LANE_8_11                               0x80
  922. #define ATOM_TRANSMITTER_CONFIG_LANE_8_15                               0x80
  923. #define ATOM_TRANSMITTER_CONFIG_LANE_12_15                      0xc0
  924.  
  925. //ucAction
  926. #define ATOM_TRANSMITTER_ACTION_DISABLE                                        0
  927. #define ATOM_TRANSMITTER_ACTION_ENABLE                                         1
  928. #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF                                      2
  929. #define ATOM_TRANSMITTER_ACTION_LCD_BLON                                       3
  930. #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4
  931. #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START               5
  932. #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP                        6
  933. #define ATOM_TRANSMITTER_ACTION_INIT                                                   7
  934. #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT         8
  935. #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT                  9
  936. #define ATOM_TRANSMITTER_ACTION_SETUP                                                  10
  937. #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11
  938. #define ATOM_TRANSMITTER_ACTION_POWER_ON               12
  939. #define ATOM_TRANSMITTER_ACTION_POWER_OFF              13
  940.  
  941. // Following are used for DigTransmitterControlTable ver1.2
  942. typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
  943. {
  944. #if ATOM_BIG_ENDIAN
  945.   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
  946.                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
  947.                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
  948.         UCHAR ucReserved:1;
  949.   UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
  950.   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
  951.   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
  952.                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
  953.  
  954.   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
  955.   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
  956. #else
  957.   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
  958.   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
  959.   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
  960.                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
  961.   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
  962.   UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
  963.         UCHAR ucReserved:1;
  964.   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
  965.                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
  966.                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
  967. #endif
  968. }ATOM_DIG_TRANSMITTER_CONFIG_V2;
  969.  
  970. //ucConfig
  971. //Bit0
  972. #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR                  0x01
  973.  
  974. //Bit1
  975. #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT                                       0x02
  976.  
  977. //Bit2
  978. #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK                        0x04
  979. #define ATOM_TRANSMITTER_CONFIG_V2_LINKA                                    0x00
  980. #define ATOM_TRANSMITTER_CONFIG_V2_LINKB                                            0x04
  981.  
  982. // Bit3
  983. #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK             0x08
  984. #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER                   0x00                          // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
  985. #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER                   0x08                          // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
  986.  
  987. // Bit4
  988. #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR                          0x10
  989.  
  990. // Bit7:6
  991. #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK     0xC0
  992. #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1                 0x00    //AB
  993. #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2                 0x40    //CD
  994. #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3                 0x80    //EF
  995.  
  996. typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
  997. {
  998.         union
  999.         {
  1000.   USHORT usPixelClock;          // in 10KHz; for bios convenient
  1001.         USHORT usInitInfo;                      // when init uniphy,lower 8bit is used for connector type defined in objectid.h
  1002.   ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
  1003.         };
  1004.         ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
  1005.         UCHAR ucAction;                           // define as ATOM_TRANSMITER_ACTION_XXX
  1006.         UCHAR ucReserved[4];
  1007. }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
  1008.  
  1009. typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
  1010. {
  1011. #if ATOM_BIG_ENDIAN
  1012.   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
  1013.                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
  1014.                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
  1015.   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
  1016.   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
  1017.   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
  1018.                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
  1019.   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
  1020.   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
  1021. #else
  1022.   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
  1023.   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
  1024.   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
  1025.                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
  1026.   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
  1027.   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
  1028.   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
  1029.                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
  1030.                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
  1031. #endif
  1032. }ATOM_DIG_TRANSMITTER_CONFIG_V3;
  1033.  
  1034.  
  1035. typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
  1036. {
  1037.         union
  1038.         {
  1039.     USHORT usPixelClock;                // in 10KHz; for bios convenient
  1040.           USHORT usInitInfo;                    // when init uniphy,lower 8bit is used for connector type defined in objectid.h
  1041.     ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
  1042.         };
  1043.   ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
  1044.         UCHAR ucAction;                             // define as ATOM_TRANSMITER_ACTION_XXX
  1045.   UCHAR ucLaneNum;
  1046.   UCHAR ucReserved[3];
  1047. }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
  1048.  
  1049. //ucConfig
  1050. //Bit0
  1051. #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR                  0x01
  1052.  
  1053. //Bit1
  1054. #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT                                       0x02
  1055.  
  1056. //Bit2
  1057. #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK                        0x04
  1058. #define ATOM_TRANSMITTER_CONFIG_V3_LINKA                                    0x00
  1059. #define ATOM_TRANSMITTER_CONFIG_V3_LINKB                                            0x04
  1060.  
  1061. // Bit3
  1062. #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK             0x08
  1063. #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER                   0x00
  1064. #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER                   0x08
  1065.  
  1066. // Bit5:4
  1067. #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK               0x30
  1068. #define ATOM_TRASMITTER_CONFIG_V3_P1PLL                                 0x00
  1069. #define ATOM_TRASMITTER_CONFIG_V3_P2PLL                           0x10
  1070. #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT            0x20
  1071.  
  1072. // Bit7:6
  1073. #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK     0xC0
  1074. #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1                 0x00    //AB
  1075. #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2                 0x40    //CD
  1076. #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3                 0x80    //EF
  1077.  
  1078.  
  1079. /****************************************************************************/ 
  1080. // Structures used by UNIPHYTransmitterControlTable V1.4
  1081. // ASIC Families: NI
  1082. // ucTableFormatRevision=1
  1083. // ucTableContentRevision=4
  1084. /****************************************************************************/ 
  1085. typedef struct _ATOM_DP_VS_MODE_V4
  1086. {
  1087.   UCHAR ucLaneSel;
  1088.         union
  1089.         {  
  1090.           UCHAR ucLaneSet;
  1091.           struct {
  1092. #if ATOM_BIG_ENDIAN
  1093.                   UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
  1094.                   UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
  1095.                   UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
  1096. #else
  1097.                   UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
  1098.                   UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
  1099.                   UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
  1100. #endif
  1101.                 };
  1102.         };
  1103. }ATOM_DP_VS_MODE_V4;
  1104.  
  1105. typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
  1106. {
  1107. #if ATOM_BIG_ENDIAN
  1108.   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
  1109.                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
  1110.                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
  1111.   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
  1112.   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
  1113.   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
  1114.                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
  1115.   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
  1116.   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
  1117. #else
  1118.   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
  1119.   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
  1120.   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
  1121.                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
  1122.   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
  1123.   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
  1124.   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
  1125.                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
  1126.                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
  1127. #endif
  1128. }ATOM_DIG_TRANSMITTER_CONFIG_V4;
  1129.  
  1130. typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
  1131. {
  1132.   union
  1133.   {
  1134.     USHORT usPixelClock;                // in 10KHz; for bios convenient
  1135.     USHORT usInitInfo;                  // when init uniphy,lower 8bit is used for connector type defined in objectid.h
  1136.     ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode     Redefined comparing to previous version
  1137.   };
  1138.   union
  1139.   {
  1140.   ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
  1141.   UCHAR ucConfig;
  1142.   };
  1143.   UCHAR ucAction;                                   // define as ATOM_TRANSMITER_ACTION_XXX                            
  1144.   UCHAR ucLaneNum;
  1145.   UCHAR ucReserved[3];
  1146. }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
  1147.  
  1148. //ucConfig
  1149. //Bit0
  1150. #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR                  0x01
  1151. //Bit1
  1152. #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT                                       0x02
  1153. //Bit2
  1154. #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK                        0x04
  1155. #define ATOM_TRANSMITTER_CONFIG_V4_LINKA                                    0x00                       
  1156. #define ATOM_TRANSMITTER_CONFIG_V4_LINKB                                            0x04
  1157. // Bit3
  1158. #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK             0x08
  1159. #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER                   0x00                           
  1160. #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER                   0x08                         
  1161. // Bit5:4
  1162. #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK              0x30
  1163. #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL                                0x00
  1164. #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL                                0x10
  1165. #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL                                0x20   // New in _V4
  1166. #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT           0x30   // Changed comparing to V3
  1167. // Bit7:6
  1168. #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK     0xC0
  1169. #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1                 0x00    //AB
  1170. #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2                 0x40    //CD
  1171. #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3                 0x80    //EF
  1172.  
  1173.  
  1174. /****************************************************************************/ 
  1175. // Structures used by ExternalEncoderControlTable V1.3
  1176. // ASIC Families: Evergreen, Llano, NI
  1177. // ucTableFormatRevision=1
  1178. // ucTableContentRevision=3
  1179. /****************************************************************************/ 
  1180.  
  1181. typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
  1182. {
  1183.   union{
  1184.   USHORT usPixelClock;      // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
  1185.   USHORT usConnectorId;     // connector id, valid when ucAction = INIT
  1186.   };
  1187.   UCHAR  ucConfig;          // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT  
  1188.   UCHAR  ucAction;          //
  1189.   UCHAR  ucEncoderMode;     // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
  1190.   UCHAR  ucLaneNum;         // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT  
  1191.   UCHAR  ucBitPerColor;     // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
  1192.   UCHAR  ucReserved;        
  1193. }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
  1194.  
  1195. // ucAction
  1196. #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT         0x00
  1197. #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT          0x01
  1198. #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT           0x07
  1199. #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP          0x0f
  1200. #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF   0x10
  1201. #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING       0x11
  1202. #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION      0x12
  1203. #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP              0x14
  1204.  
  1205. // ucConfig
  1206. #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK                              0x03
  1207. #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ             0x00
  1208. #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ             0x01
  1209. #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ             0x02
  1210. #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK                 0x70
  1211. #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1                         0x00
  1212. #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2                         0x10
  1213. #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3                         0x20
  1214.  
  1215. typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
  1216. {
  1217.   EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
  1218.   ULONG ulReserved[2];
  1219. }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
  1220.  
  1221.  
  1222. /****************************************************************************/ 
  1223. // Structures used by DAC1OuputControlTable
  1224. //                    DAC2OuputControlTable
  1225. //                    LVTMAOutputControlTable  (Before DEC30)
  1226. //                    TMDSAOutputControlTable  (Before DEC30)
  1227. /****************************************************************************/
  1228. typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  1229. {
  1230.   UCHAR  ucAction;                    // Possible input:ATOM_ENABLE||ATOMDISABLE
  1231.                                       // When the display is LCD, in addition to above:
  1232.                                       // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
  1233.                                       // ATOM_LCD_SELFTEST_STOP
  1234.  
  1235.   UCHAR  aucPadding[3];               // padding to DWORD aligned
  1236. }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
  1237.  
  1238. #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  1239.  
  1240.  
  1241. #define CRT1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  1242. #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  1243.  
  1244. #define CRT2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  1245. #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  1246.  
  1247. #define CV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  1248. #define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  1249.  
  1250. #define TV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  1251. #define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  1252.  
  1253. #define DFP1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  1254. #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  1255.  
  1256. #define DFP2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  1257. #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  1258.  
  1259. #define LCD1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  1260. #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
  1261.  
  1262. #define DVO_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
  1263. #define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
  1264. #define DVO_OUTPUT_CONTROL_PARAMETERS_V3         DIG_TRANSMITTER_CONTROL_PARAMETERS
  1265.  
  1266. /****************************************************************************/
  1267. // Structures used by BlankCRTCTable
  1268. /****************************************************************************/
  1269. typedef struct _BLANK_CRTC_PARAMETERS
  1270. {
  1271.   UCHAR  ucCRTC;                        // ATOM_CRTC1 or ATOM_CRTC2
  1272.   UCHAR  ucBlanking;                  // ATOM_BLANKING or ATOM_BLANKINGOFF
  1273.         USHORT usBlackColorRCr;
  1274.         USHORT usBlackColorGY;
  1275.         USHORT usBlackColorBCb;
  1276. }BLANK_CRTC_PARAMETERS;
  1277. #define BLANK_CRTC_PS_ALLOCATION    BLANK_CRTC_PARAMETERS
  1278.  
  1279. /****************************************************************************/
  1280. // Structures used by EnableCRTCTable
  1281. //                    EnableCRTCMemReqTable
  1282. //                    UpdateCRTC_DoubleBufferRegistersTable
  1283. /****************************************************************************/ 
  1284. typedef struct _ENABLE_CRTC_PARAMETERS
  1285. {
  1286.   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
  1287.   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
  1288.         UCHAR ucPadding[2];
  1289. }ENABLE_CRTC_PARAMETERS;
  1290. #define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS
  1291.  
  1292. /****************************************************************************/
  1293. // Structures used by SetCRTC_OverScanTable
  1294. /****************************************************************************/
  1295. typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
  1296. {
  1297.   USHORT usOverscanRight;             // right
  1298.   USHORT usOverscanLeft;              // left
  1299.   USHORT usOverscanBottom;            // bottom
  1300.   USHORT usOverscanTop;               // top
  1301.   UCHAR  ucCRTC;                      // ATOM_CRTC1 or ATOM_CRTC2
  1302.         UCHAR ucPadding[3];
  1303. }SET_CRTC_OVERSCAN_PARAMETERS;
  1304. #define SET_CRTC_OVERSCAN_PS_ALLOCATION  SET_CRTC_OVERSCAN_PARAMETERS
  1305.  
  1306. /****************************************************************************/
  1307. // Structures used by SetCRTC_ReplicationTable
  1308. /****************************************************************************/
  1309. typedef struct _SET_CRTC_REPLICATION_PARAMETERS
  1310. {
  1311.   UCHAR ucH_Replication;              // horizontal replication
  1312.   UCHAR ucV_Replication;              // vertical replication
  1313.   UCHAR usCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
  1314.         UCHAR ucPadding;
  1315. }SET_CRTC_REPLICATION_PARAMETERS;
  1316. #define SET_CRTC_REPLICATION_PS_ALLOCATION  SET_CRTC_REPLICATION_PARAMETERS
  1317.  
  1318. /****************************************************************************/
  1319. // Structures used by SelectCRTC_SourceTable
  1320. /****************************************************************************/
  1321. typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
  1322. {
  1323.   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
  1324.   UCHAR ucDevice;                     // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
  1325.         UCHAR ucPadding[2];
  1326. }SELECT_CRTC_SOURCE_PARAMETERS;
  1327. #define SELECT_CRTC_SOURCE_PS_ALLOCATION  SELECT_CRTC_SOURCE_PARAMETERS
  1328.  
  1329. typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
  1330. {
  1331.   UCHAR ucCRTC;                           // ATOM_CRTC1 or ATOM_CRTC2
  1332.   UCHAR ucEncoderID;                  // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
  1333.   UCHAR ucEncodeMode;                                                                   // Encoding mode, only valid when using DIG1/DIG2/DVO
  1334.         UCHAR ucPadding;
  1335. }SELECT_CRTC_SOURCE_PARAMETERS_V2;
  1336.  
  1337. //ucEncoderID
  1338. //#define ASIC_INT_DAC1_ENCODER_ID                                              0x00
  1339. //#define ASIC_INT_TV_ENCODER_ID                                                                        0x02
  1340. //#define ASIC_INT_DIG1_ENCODER_ID                                                              0x03
  1341. //#define ASIC_INT_DAC2_ENCODER_ID                                                              0x04
  1342. //#define ASIC_EXT_TV_ENCODER_ID                                                                        0x06
  1343. //#define ASIC_INT_DVO_ENCODER_ID                                                                       0x07
  1344. //#define ASIC_INT_DIG2_ENCODER_ID                                                              0x09
  1345. //#define ASIC_EXT_DIG_ENCODER_ID                                                                       0x05
  1346.  
  1347. //ucEncodeMode
  1348. //#define ATOM_ENCODER_MODE_DP                                                                          0
  1349. //#define ATOM_ENCODER_MODE_LVDS                                                                        1
  1350. //#define ATOM_ENCODER_MODE_DVI                                                                         2
  1351. //#define ATOM_ENCODER_MODE_HDMI                                                                        3
  1352. //#define ATOM_ENCODER_MODE_SDVO                                                                        4
  1353. //#define ATOM_ENCODER_MODE_TV                                                                          13
  1354. //#define ATOM_ENCODER_MODE_CV                                                                          14
  1355. //#define ATOM_ENCODER_MODE_CRT                                                                         15
  1356.  
  1357. /****************************************************************************/ 
  1358. // Structures used by SetPixelClockTable
  1359. //                    GetPixelClockTable
  1360. /****************************************************************************/ 
  1361. //Major revision=1., Minor revision=1
  1362. typedef struct _PIXEL_CLOCK_PARAMETERS
  1363. {
  1364.   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
  1365.                                       // 0 means disable PPLL
  1366.   USHORT usRefDiv;                    // Reference divider
  1367.   USHORT usFbDiv;                     // feedback divider
  1368.   UCHAR  ucPostDiv;                   // post divider  
  1369.   UCHAR  ucFracFbDiv;                 // fractional feedback divider
  1370.   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
  1371.   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
  1372.   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
  1373.         UCHAR ucPadding;
  1374. }PIXEL_CLOCK_PARAMETERS;
  1375.  
  1376. //Major revision=1., Minor revision=2, add ucMiscIfno
  1377. //ucMiscInfo:
  1378. #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
  1379. #define MISC_DEVICE_INDEX_MASK        0xF0
  1380. #define MISC_DEVICE_INDEX_SHIFT       4
  1381.  
  1382. typedef struct _PIXEL_CLOCK_PARAMETERS_V2
  1383. {
  1384.   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
  1385.                                       // 0 means disable PPLL
  1386.   USHORT usRefDiv;                    // Reference divider
  1387.   USHORT usFbDiv;                     // feedback divider
  1388.   UCHAR  ucPostDiv;                   // post divider  
  1389.   UCHAR  ucFracFbDiv;                 // fractional feedback divider
  1390.   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
  1391.   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
  1392.   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
  1393.   UCHAR  ucMiscInfo;                  // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
  1394. }PIXEL_CLOCK_PARAMETERS_V2;
  1395.  
  1396. //Major revision=1., Minor revision=3, structure/definition change
  1397. //ucEncoderMode:
  1398. //ATOM_ENCODER_MODE_DP
  1399. //ATOM_ENOCDER_MODE_LVDS
  1400. //ATOM_ENOCDER_MODE_DVI
  1401. //ATOM_ENOCDER_MODE_HDMI
  1402. //ATOM_ENOCDER_MODE_SDVO
  1403. //ATOM_ENCODER_MODE_TV                                                                          13
  1404. //ATOM_ENCODER_MODE_CV                                                                          14
  1405. //ATOM_ENCODER_MODE_CRT                                                                         15
  1406.  
  1407. //ucDVOConfig
  1408. //#define DVO_ENCODER_CONFIG_RATE_SEL                                                   0x01
  1409. //#define DVO_ENCODER_CONFIG_DDR_SPEED                                          0x00
  1410. //#define DVO_ENCODER_CONFIG_SDR_SPEED                                          0x01
  1411. //#define DVO_ENCODER_CONFIG_OUTPUT_SEL                                         0x0c
  1412. //#define DVO_ENCODER_CONFIG_LOW12BIT                                                   0x00
  1413. //#define DVO_ENCODER_CONFIG_UPPER12BIT                                         0x04
  1414. //#define DVO_ENCODER_CONFIG_24BIT                                                              0x08
  1415.  
  1416. //ucMiscInfo: also changed, see below
  1417. #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL                                                0x01
  1418. #define PIXEL_CLOCK_MISC_VGA_MODE                                                                               0x02
  1419. #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK                                                  0x04
  1420. #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1                                                 0x00
  1421. #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2                                                 0x04
  1422. #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK                 0x08
  1423. #define PIXEL_CLOCK_MISC_REF_DIV_SRC                    0x10
  1424. // V1.4 for RoadRunner
  1425. #define PIXEL_CLOCK_V4_MISC_SS_ENABLE               0x10
  1426. #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE           0x20
  1427.  
  1428.  
  1429. typedef struct _PIXEL_CLOCK_PARAMETERS_V3
  1430. {
  1431.   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
  1432.                                       // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
  1433.   USHORT usRefDiv;                    // Reference divider
  1434.   USHORT usFbDiv;                     // feedback divider
  1435.   UCHAR  ucPostDiv;                   // post divider  
  1436.   UCHAR  ucFracFbDiv;                 // fractional feedback divider
  1437.   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
  1438.   UCHAR  ucTransmitterId;             // graphic encoder id defined in objectId.h
  1439.         union
  1440.         {
  1441.   UCHAR  ucEncoderMode;               // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
  1442.         UCHAR  ucDVOConfig;                                                                     // when use DVO, need to know SDR/DDR, 12bit or 24bit
  1443.         };
  1444.   UCHAR  ucMiscInfo;                  // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
  1445.                                       // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
  1446.                                       // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
  1447. }PIXEL_CLOCK_PARAMETERS_V3;
  1448.  
  1449. #define PIXEL_CLOCK_PARAMETERS_LAST                     PIXEL_CLOCK_PARAMETERS_V2
  1450. #define GET_PIXEL_CLOCK_PS_ALLOCATION           PIXEL_CLOCK_PARAMETERS_LAST
  1451.  
  1452. typedef struct _PIXEL_CLOCK_PARAMETERS_V5
  1453. {
  1454.   UCHAR  ucCRTC;             // ATOM_CRTC1~6, indicate the CRTC controller to
  1455.                              // drive the pixel clock. not used for DCPLL case.
  1456.   union{
  1457.   UCHAR  ucReserved;
  1458.   UCHAR  ucFracFbDiv;        // [gphan] temporary to prevent build problem.  remove it after driver code is changed.
  1459.   };
  1460.   USHORT usPixelClock;       // target the pixel clock to drive the CRTC timing
  1461.                              // 0 means disable PPLL/DCPLL.
  1462.   USHORT usFbDiv;            // feedback divider integer part.
  1463.   UCHAR  ucPostDiv;          // post divider.
  1464.   UCHAR  ucRefDiv;           // Reference divider
  1465.   UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
  1466.   UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h,
  1467.                              // indicate which graphic encoder will be used.
  1468.   UCHAR  ucEncoderMode;      // Encoder mode:
  1469.   UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL
  1470.                              // bit[1]= when VGA timing is used.
  1471.                              // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
  1472.                              // bit[4]= RefClock source for PPLL.
  1473.                              // =0: XTLAIN( default mode )
  1474.                                    // =1: other external clock source, which is pre-defined
  1475.                              //     by VBIOS depend on the feature required.
  1476.                              // bit[7:5]: reserved.
  1477.   ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
  1478.  
  1479. }PIXEL_CLOCK_PARAMETERS_V5;
  1480.  
  1481. #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL                                     0x01
  1482. #define PIXEL_CLOCK_V5_MISC_VGA_MODE                                                            0x02
  1483. #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK           0x0c
  1484. #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP              0x00
  1485. #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP              0x04
  1486. #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP              0x08
  1487. #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC             0x10
  1488.  
  1489. typedef struct _CRTC_PIXEL_CLOCK_FREQ
  1490. {
  1491. #if ATOM_BIG_ENDIAN
  1492.   ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to
  1493.                               // drive the pixel clock. not used for DCPLL case.
  1494.   ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing.
  1495.                               // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
  1496. #else
  1497.   ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing.
  1498.                               // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
  1499.   ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to
  1500.                               // drive the pixel clock. not used for DCPLL case.
  1501. #endif
  1502. }CRTC_PIXEL_CLOCK_FREQ;
  1503.  
  1504. typedef struct _PIXEL_CLOCK_PARAMETERS_V6
  1505. {
  1506.   union{
  1507.     CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;    // pixel clock and CRTC id frequency
  1508.     ULONG ulDispEngClkFreq;                  // dispclk frequency
  1509.   };
  1510.   USHORT usFbDiv;            // feedback divider integer part.
  1511.   UCHAR  ucPostDiv;          // post divider.
  1512.   UCHAR  ucRefDiv;           // Reference divider
  1513.   UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
  1514.   UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h,
  1515.                              // indicate which graphic encoder will be used.
  1516.   UCHAR  ucEncoderMode;      // Encoder mode:
  1517.   UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL
  1518.                              // bit[1]= when VGA timing is used.
  1519.                              // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
  1520.                              // bit[4]= RefClock source for PPLL.
  1521.                              // =0: XTLAIN( default mode )
  1522.                                    // =1: other external clock source, which is pre-defined                                            
  1523.                              //     by VBIOS depend on the feature required.
  1524.                              // bit[7:5]: reserved.
  1525.   ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
  1526.  
  1527. }PIXEL_CLOCK_PARAMETERS_V6;
  1528.  
  1529. #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL                                     0x01
  1530. #define PIXEL_CLOCK_V6_MISC_VGA_MODE                                                            0x02
  1531. #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK           0x0c
  1532. #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP              0x00
  1533. #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP              0x04
  1534. #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP              0x08
  1535. #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP              0x0c
  1536. #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC             0x10
  1537.  
  1538. typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
  1539. {
  1540.   PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
  1541. }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
  1542.  
  1543. typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
  1544. {
  1545.   UCHAR  ucStatus;
  1546.   UCHAR  ucRefDivSrc;                 // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
  1547.   UCHAR  ucReserved[2];
  1548. }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
  1549.  
  1550. typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
  1551. {
  1552.   PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
  1553. }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
  1554.  
  1555. /****************************************************************************/
  1556. // Structures used by AdjustDisplayPllTable
  1557. /****************************************************************************/
  1558. typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
  1559. {
  1560.         USHORT usPixelClock;
  1561.         UCHAR ucTransmitterID;
  1562.         UCHAR ucEncodeMode;
  1563.         union
  1564.         {
  1565.                 UCHAR ucDVOConfig;                                                                      //if DVO, need passing link rate and output 12bitlow or 24bit
  1566.                 UCHAR ucConfig;                                                                                 //if none DVO, not defined yet
  1567.         };
  1568.         UCHAR ucReserved[3];
  1569. }ADJUST_DISPLAY_PLL_PARAMETERS;
  1570.  
  1571. #define ADJUST_DISPLAY_CONFIG_SS_ENABLE       0x10
  1572. #define ADJUST_DISPLAY_PLL_PS_ALLOCATION                        ADJUST_DISPLAY_PLL_PARAMETERS
  1573.  
  1574. typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
  1575. {
  1576.         USHORT usPixelClock;                    // target pixel clock
  1577.         UCHAR ucTransmitterID;                  // GPU transmitter id defined in objectid.h
  1578.         UCHAR ucEncodeMode;                     // encoder mode: CRT, LVDS, DP, TMDS or HDMI
  1579.   UCHAR ucDispPllConfig;                 // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
  1580.   UCHAR ucExtTransmitterID;               // external encoder id.
  1581.         UCHAR ucReserved[2];
  1582. }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
  1583.  
  1584. // usDispPllConfig v1.2 for RoadRunner
  1585. #define DISPPLL_CONFIG_DVO_RATE_SEL                0x0001     // need only when ucTransmitterID = DVO
  1586. #define DISPPLL_CONFIG_DVO_DDR_SPEED               0x0000     // need only when ucTransmitterID = DVO
  1587. #define DISPPLL_CONFIG_DVO_SDR_SPEED               0x0001     // need only when ucTransmitterID = DVO
  1588. #define DISPPLL_CONFIG_DVO_OUTPUT_SEL              0x000c     // need only when ucTransmitterID = DVO
  1589. #define DISPPLL_CONFIG_DVO_LOW12BIT                0x0000     // need only when ucTransmitterID = DVO
  1590. #define DISPPLL_CONFIG_DVO_UPPER12BIT              0x0004     // need only when ucTransmitterID = DVO
  1591. #define DISPPLL_CONFIG_DVO_24BIT                   0x0008     // need only when ucTransmitterID = DVO
  1592. #define DISPPLL_CONFIG_SS_ENABLE                   0x0010     // Only used when ucEncoderMode = DP or LVDS
  1593. #define DISPPLL_CONFIG_COHERENT_MODE               0x0020     // Only used when ucEncoderMode = TMDS or HDMI
  1594. #define DISPPLL_CONFIG_DUAL_LINK                   0x0040     // Only used when ucEncoderMode = TMDS or LVDS
  1595.  
  1596.  
  1597. typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
  1598. {
  1599.   ULONG ulDispPllFreq;                 // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
  1600.   UCHAR ucRefDiv;                      // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
  1601.   UCHAR ucPostDiv;                     // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
  1602.   UCHAR ucReserved[2];  
  1603. }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
  1604.  
  1605. typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
  1606. {
  1607.   union
  1608.   {
  1609.     ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3  sInput;
  1610.     ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
  1611.   };
  1612. } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
  1613.  
  1614. /****************************************************************************/
  1615. // Structures used by EnableYUVTable
  1616. /****************************************************************************/
  1617. typedef struct _ENABLE_YUV_PARAMETERS
  1618. {
  1619.   UCHAR ucEnable;                     // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
  1620.   UCHAR ucCRTC;                       // Which CRTC needs this YUV or RGB format
  1621.         UCHAR ucPadding[2];
  1622. }ENABLE_YUV_PARAMETERS;
  1623. #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
  1624.  
  1625. /****************************************************************************/
  1626. // Structures used by GetMemoryClockTable
  1627. /****************************************************************************/
  1628. typedef struct _GET_MEMORY_CLOCK_PARAMETERS
  1629. {
  1630.   ULONG ulReturnMemoryClock;          // current memory speed in 10KHz unit
  1631. } GET_MEMORY_CLOCK_PARAMETERS;
  1632. #define GET_MEMORY_CLOCK_PS_ALLOCATION  GET_MEMORY_CLOCK_PARAMETERS
  1633.  
  1634. /****************************************************************************/
  1635. // Structures used by GetEngineClockTable
  1636. /****************************************************************************/
  1637. typedef struct _GET_ENGINE_CLOCK_PARAMETERS
  1638. {
  1639.   ULONG ulReturnEngineClock;          // current engine speed in 10KHz unit
  1640. } GET_ENGINE_CLOCK_PARAMETERS;
  1641. #define GET_ENGINE_CLOCK_PS_ALLOCATION  GET_ENGINE_CLOCK_PARAMETERS
  1642.  
  1643. /****************************************************************************/
  1644. // Following Structures and constant may be obsolete
  1645. /****************************************************************************/
  1646. //Maxium 8 bytes,the data read in will be placed in the parameter space.
  1647. //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
  1648. typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
  1649. {
  1650.   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
  1651.   USHORT    usVRAMAddress;      //Address in Frame Buffer where to pace raw EDID
  1652.   USHORT    usStatus;           //When use output: lower byte EDID checksum, high byte hardware status
  1653.                                 //WHen use input:  lower byte as 'byte to read':currently limited to 128byte or 1byte
  1654.   UCHAR     ucSlaveAddr;        //Read from which slave
  1655.   UCHAR     ucLineNumber;       //Read from which HW assisted line
  1656. }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
  1657. #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION  READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
  1658.  
  1659.  
  1660. #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE                  0
  1661. #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES              1
  1662. #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK       2
  1663. #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK  3
  1664. #define  ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK       4
  1665.  
  1666. typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
  1667. {
  1668.   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
  1669.   USHORT    usByteOffset;       //Write to which byte
  1670.                                 //Upper portion of usByteOffset is Format of data
  1671.                                 //1bytePS+offsetPS
  1672.                                 //2bytesPS+offsetPS
  1673.                                 //blockID+offsetPS
  1674.                                 //blockID+offsetID
  1675.                                 //blockID+counterID+offsetID
  1676.   UCHAR     ucData;             //PS data1
  1677.   UCHAR     ucStatus;           //Status byte 1=success, 2=failure, Also is used as PS data2
  1678.   UCHAR     ucSlaveAddr;        //Write to which slave
  1679.   UCHAR     ucLineNumber;       //Write from which HW assisted line
  1680. }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
  1681.  
  1682. #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION  WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
  1683.  
  1684. typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
  1685. {
  1686.   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
  1687.   UCHAR     ucSlaveAddr;        //Write to which slave
  1688.   UCHAR     ucLineNumber;       //Write from which HW assisted line
  1689. }SET_UP_HW_I2C_DATA_PARAMETERS;
  1690.  
  1691.  
  1692. /**************************************************************************/
  1693. #define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
  1694.  
  1695.  
  1696. /****************************************************************************/
  1697. // Structures used by PowerConnectorDetectionTable
  1698. /****************************************************************************/
  1699. typedef struct  _POWER_CONNECTOR_DETECTION_PARAMETERS
  1700. {
  1701.   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
  1702.         UCHAR ucPwrBehaviorId;
  1703.         USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
  1704. }POWER_CONNECTOR_DETECTION_PARAMETERS;
  1705.  
  1706. typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
  1707. {                              
  1708.   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
  1709.         UCHAR ucReserved;
  1710.         USHORT  usPwrBudget;                                                             //how much power currently boot to in unit of watt
  1711.         WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
  1712. }POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
  1713.  
  1714. /****************************LVDS SS Command Table Definitions**********************/
  1715.  
  1716. /****************************************************************************/
  1717. // Structures used by EnableSpreadSpectrumOnPPLLTable
  1718. /****************************************************************************/
  1719. typedef struct  _ENABLE_LVDS_SS_PARAMETERS
  1720. {
  1721.         USHORT usSpreadSpectrumPercentage;
  1722.   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
  1723.   UCHAR   ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
  1724.   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
  1725.         UCHAR ucPadding[3];
  1726. }ENABLE_LVDS_SS_PARAMETERS;
  1727.  
  1728. //ucTableFormatRevision=1,ucTableContentRevision=2
  1729. typedef struct  _ENABLE_LVDS_SS_PARAMETERS_V2
  1730. {
  1731.         USHORT usSpreadSpectrumPercentage;
  1732.   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
  1733.   UCHAR   ucSpreadSpectrumStep;           //
  1734.   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
  1735.         UCHAR ucSpreadSpectrumDelay;
  1736.         UCHAR ucSpreadSpectrumRange;
  1737.         UCHAR ucPadding;
  1738. }ENABLE_LVDS_SS_PARAMETERS_V2;
  1739.  
  1740. //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
  1741. typedef struct  _ENABLE_SPREAD_SPECTRUM_ON_PPLL
  1742. {
  1743.         USHORT usSpreadSpectrumPercentage;
  1744.   UCHAR   ucSpreadSpectrumType;           // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
  1745.   UCHAR   ucSpreadSpectrumStep;           //
  1746.   UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
  1747.         UCHAR ucSpreadSpectrumDelay;
  1748.         UCHAR ucSpreadSpectrumRange;
  1749.   UCHAR   ucPpll;                                                                                                 // ATOM_PPLL1/ATOM_PPLL2
  1750. }ENABLE_SPREAD_SPECTRUM_ON_PPLL;
  1751.  
  1752. typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
  1753. {
  1754.   USHORT  usSpreadSpectrumPercentage;
  1755.   UCHAR   ucSpreadSpectrumType;         // Bit[0]: 0-Down Spread,1-Center Spread.
  1756.                                         // Bit[1]: 1-Ext. 0-Int.
  1757.                                         // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
  1758.                                         // Bits[7:4] reserved
  1759.   UCHAR   ucEnable;                         // ATOM_ENABLE or ATOM_DISABLE
  1760.   USHORT  usSpreadSpectrumAmount;       // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]    
  1761.   USHORT  usSpreadSpectrumStep;         // SS_STEP_SIZE_DSFRAC
  1762. }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
  1763.  
  1764. #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD      0x00
  1765. #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD    0x01
  1766. #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD       0x02
  1767. #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK    0x0c
  1768. #define ATOM_PPLL_SS_TYPE_V2_P1PLL            0x00
  1769. #define ATOM_PPLL_SS_TYPE_V2_P2PLL            0x04
  1770. #define ATOM_PPLL_SS_TYPE_V2_DCPLL            0x08
  1771. #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK     0x00FF
  1772. #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT    0
  1773. #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK     0x0F00
  1774. #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT    8
  1775.  
  1776. // Used by DCE5.0
  1777.  typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
  1778. {
  1779.   USHORT  usSpreadSpectrumAmountFrac;   // SS_AMOUNT_DSFRAC New in DCE5.0
  1780.   UCHAR   ucSpreadSpectrumType;         // Bit[0]: 0-Down Spread,1-Center Spread.
  1781.                                         // Bit[1]: 1-Ext. 0-Int.
  1782.                                         // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
  1783.                                         // Bits[7:4] reserved
  1784.   UCHAR   ucEnable;                         // ATOM_ENABLE or ATOM_DISABLE
  1785.   USHORT  usSpreadSpectrumAmount;       // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]    
  1786.   USHORT  usSpreadSpectrumStep;         // SS_STEP_SIZE_DSFRAC
  1787. }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
  1788.    
  1789. #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD      0x00
  1790. #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD    0x01
  1791. #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD       0x02
  1792. #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK    0x0c
  1793. #define ATOM_PPLL_SS_TYPE_V3_P1PLL            0x00
  1794. #define ATOM_PPLL_SS_TYPE_V3_P2PLL            0x04
  1795. #define ATOM_PPLL_SS_TYPE_V3_DCPLL            0x08
  1796. #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK     0x00FF
  1797. #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT    0
  1798. #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK     0x0F00
  1799. #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT    8
  1800.  
  1801. #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION  ENABLE_SPREAD_SPECTRUM_ON_PPLL
  1802.  
  1803. /**************************************************************************/
  1804.  
  1805. typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
  1806. {
  1807.         PIXEL_CLOCK_PARAMETERS sPCLKInput;
  1808.   ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
  1809. }SET_PIXEL_CLOCK_PS_ALLOCATION;
  1810.  
  1811. #define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION
  1812.  
  1813. /****************************************************************************/
  1814. // Structures used by ###
  1815. /****************************************************************************/
  1816. typedef struct  _MEMORY_TRAINING_PARAMETERS
  1817. {
  1818.   ULONG ulTargetMemoryClock;          //In 10Khz unit
  1819. }MEMORY_TRAINING_PARAMETERS;
  1820. #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
  1821.  
  1822.  
  1823. /****************************LVDS and other encoder command table definitions **********************/
  1824.  
  1825.  
  1826. /****************************************************************************/ 
  1827. // Structures used by LVDSEncoderControlTable   (Before DCE30)
  1828. //                    LVTMAEncoderControlTable  (Before DCE30)
  1829. //                    TMDSAEncoderControlTable  (Before DCE30)
  1830. /****************************************************************************/
  1831. typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
  1832. {
  1833.   USHORT usPixelClock;  // in 10KHz; for bios convenient
  1834.   UCHAR  ucMisc;        // bit0=0: Enable single link
  1835.                         //     =1: Enable dual link
  1836.                         // Bit1=0: 666RGB
  1837.                         //     =1: 888RGB
  1838.   UCHAR  ucAction;      // 0: turn off encoder
  1839.                         // 1: setup and turn on encoder
  1840. }LVDS_ENCODER_CONTROL_PARAMETERS;
  1841.  
  1842. #define LVDS_ENCODER_CONTROL_PS_ALLOCATION  LVDS_ENCODER_CONTROL_PARAMETERS
  1843.  
  1844. #define TMDS1_ENCODER_CONTROL_PARAMETERS    LVDS_ENCODER_CONTROL_PARAMETERS
  1845. #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
  1846.  
  1847. #define TMDS2_ENCODER_CONTROL_PARAMETERS    TMDS1_ENCODER_CONTROL_PARAMETERS
  1848. #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
  1849.  
  1850.  
  1851. //ucTableFormatRevision=1,ucTableContentRevision=2
  1852. typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
  1853. {
  1854.   USHORT usPixelClock;  // in 10KHz; for bios convenient
  1855.   UCHAR  ucMisc;        // see PANEL_ENCODER_MISC_xx defintions below
  1856.   UCHAR  ucAction;      // 0: turn off encoder
  1857.                         // 1: setup and turn on encoder
  1858.   UCHAR  ucTruncate;    // bit0=0: Disable truncate
  1859.                         //     =1: Enable truncate
  1860.                         // bit4=0: 666RGB
  1861.                         //     =1: 888RGB
  1862.   UCHAR  ucSpatial;     // bit0=0: Disable spatial dithering
  1863.                         //     =1: Enable spatial dithering
  1864.                         // bit4=0: 666RGB
  1865.                         //     =1: 888RGB
  1866.   UCHAR  ucTemporal;    // bit0=0: Disable temporal dithering
  1867.                         //     =1: Enable temporal dithering
  1868.                         // bit4=0: 666RGB
  1869.                         //     =1: 888RGB
  1870.                         // bit5=0: Gray level 2
  1871.                         //     =1: Gray level 4
  1872.   UCHAR  ucFRC;         // bit4=0: 25FRC_SEL pattern E
  1873.                         //     =1: 25FRC_SEL pattern F
  1874.                         // bit6:5=0: 50FRC_SEL pattern A
  1875.                         //       =1: 50FRC_SEL pattern B
  1876.                         //       =2: 50FRC_SEL pattern C
  1877.                         //       =3: 50FRC_SEL pattern D
  1878.                         // bit7=0: 75FRC_SEL pattern E
  1879.                         //     =1: 75FRC_SEL pattern F
  1880. }LVDS_ENCODER_CONTROL_PARAMETERS_V2;
  1881.  
  1882. #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
  1883.  
  1884. #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2    LVDS_ENCODER_CONTROL_PARAMETERS_V2
  1885. #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
  1886.  
  1887. #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2    TMDS1_ENCODER_CONTROL_PARAMETERS_V2
  1888. #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
  1889.  
  1890. #define LVDS_ENCODER_CONTROL_PARAMETERS_V3     LVDS_ENCODER_CONTROL_PARAMETERS_V2
  1891. #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3  LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1892.  
  1893. #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1894. #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
  1895.  
  1896. #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1897. #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
  1898.  
  1899. /****************************************************************************/
  1900. // Structures used by ###
  1901. /****************************************************************************/
  1902. typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
  1903. {                              
  1904.   UCHAR    ucEnable;            // Enable or Disable External TMDS encoder
  1905.   UCHAR    ucMisc;              // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
  1906.         UCHAR ucPadding[2];
  1907. }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
  1908.  
  1909. typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
  1910. {                              
  1911.         ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
  1912.   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION   sReserved;     //Caller doesn't need to init this portion
  1913. }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
  1914.  
  1915. #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
  1916.  
  1917. typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
  1918. {                              
  1919.         ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
  1920.   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
  1921. }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
  1922.  
  1923. typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
  1924. {
  1925.         DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;
  1926.         WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
  1927. }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
  1928.  
  1929. /****************************************************************************/
  1930. // Structures used by DVOEncoderControlTable
  1931. /****************************************************************************/
  1932. //ucTableFormatRevision=1,ucTableContentRevision=3
  1933.  
  1934. //ucDVOConfig:
  1935. #define DVO_ENCODER_CONFIG_RATE_SEL                                                     0x01
  1936. #define DVO_ENCODER_CONFIG_DDR_SPEED                                            0x00
  1937. #define DVO_ENCODER_CONFIG_SDR_SPEED                                            0x01
  1938. #define DVO_ENCODER_CONFIG_OUTPUT_SEL                                           0x0c
  1939. #define DVO_ENCODER_CONFIG_LOW12BIT                                                     0x00
  1940. #define DVO_ENCODER_CONFIG_UPPER12BIT                                           0x04
  1941. #define DVO_ENCODER_CONFIG_24BIT                                                                0x08
  1942.  
  1943. typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
  1944. {
  1945.         USHORT usPixelClock;
  1946.         UCHAR ucDVOConfig;
  1947.   UCHAR  ucAction;                                                                                                              //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
  1948.         UCHAR ucReseved[4];
  1949. }DVO_ENCODER_CONTROL_PARAMETERS_V3;
  1950. #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3    DVO_ENCODER_CONTROL_PARAMETERS_V3
  1951.  
  1952. //ucTableFormatRevision=1
  1953. //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
  1954. // bit1=0: non-coherent mode
  1955. //     =1: coherent mode
  1956.  
  1957. //==========================================================================================
  1958. //Only change is here next time when changing encoder parameter definitions again!
  1959. #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST     LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1960. #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST  LVDS_ENCODER_CONTROL_PARAMETERS_LAST
  1961.  
  1962. #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1963. #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
  1964.  
  1965. #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
  1966. #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
  1967.  
  1968. #define DVO_ENCODER_CONTROL_PARAMETERS_LAST      DVO_ENCODER_CONTROL_PARAMETERS
  1969. #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION
  1970.  
  1971. //==========================================================================================
  1972. #define PANEL_ENCODER_MISC_DUAL                0x01
  1973. #define PANEL_ENCODER_MISC_COHERENT            0x02
  1974. #define PANEL_ENCODER_MISC_TMDS_LINKB                                    0x04
  1975. #define PANEL_ENCODER_MISC_HDMI_TYPE                                     0x08
  1976.  
  1977. #define PANEL_ENCODER_ACTION_DISABLE           ATOM_DISABLE
  1978. #define PANEL_ENCODER_ACTION_ENABLE            ATOM_ENABLE
  1979. #define PANEL_ENCODER_ACTION_COHERENTSEQ       (ATOM_ENABLE+1)
  1980.  
  1981. #define PANEL_ENCODER_TRUNCATE_EN              0x01
  1982. #define PANEL_ENCODER_TRUNCATE_DEPTH           0x10
  1983. #define PANEL_ENCODER_SPATIAL_DITHER_EN        0x01
  1984. #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH     0x10
  1985. #define PANEL_ENCODER_TEMPORAL_DITHER_EN       0x01
  1986. #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH    0x10
  1987. #define PANEL_ENCODER_TEMPORAL_LEVEL_4         0x20
  1988. #define PANEL_ENCODER_25FRC_MASK               0x10
  1989. #define PANEL_ENCODER_25FRC_E                  0x00
  1990. #define PANEL_ENCODER_25FRC_F                  0x10
  1991. #define PANEL_ENCODER_50FRC_MASK               0x60
  1992. #define PANEL_ENCODER_50FRC_A                  0x00
  1993. #define PANEL_ENCODER_50FRC_B                  0x20
  1994. #define PANEL_ENCODER_50FRC_C                  0x40
  1995. #define PANEL_ENCODER_50FRC_D                  0x60
  1996. #define PANEL_ENCODER_75FRC_MASK               0x80
  1997. #define PANEL_ENCODER_75FRC_E                  0x00
  1998. #define PANEL_ENCODER_75FRC_F                  0x80
  1999.  
  2000. /****************************************************************************/
  2001. // Structures used by SetVoltageTable
  2002. /****************************************************************************/
  2003. #define SET_VOLTAGE_TYPE_ASIC_VDDC             1
  2004. #define SET_VOLTAGE_TYPE_ASIC_MVDDC            2
  2005. #define SET_VOLTAGE_TYPE_ASIC_MVDDQ            3
  2006. #define SET_VOLTAGE_TYPE_ASIC_VDDCI            4
  2007. #define SET_VOLTAGE_INIT_MODE                  5
  2008. #define SET_VOLTAGE_GET_MAX_VOLTAGE            6                                        //Gets the Max. voltage for the soldered Asic
  2009.  
  2010. #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE       0x1
  2011. #define SET_ASIC_VOLTAGE_MODE_SOURCE_A         0x2
  2012. #define SET_ASIC_VOLTAGE_MODE_SOURCE_B         0x4
  2013.  
  2014. #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE      0x0
  2015. #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL      0x1
  2016. #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK     0x2
  2017.  
  2018. typedef struct  _SET_VOLTAGE_PARAMETERS
  2019. {
  2020.   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
  2021.   UCHAR    ucVoltageMode;               // To set all, to set source A or source B or ...
  2022.   UCHAR    ucVoltageIndex;              // An index to tell which voltage level
  2023.         UCHAR ucReserved;
  2024. }SET_VOLTAGE_PARAMETERS;
  2025.  
  2026. typedef struct  _SET_VOLTAGE_PARAMETERS_V2
  2027. {
  2028.   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
  2029.   UCHAR    ucVoltageMode;               // Not used, maybe use for state machine for differen power mode
  2030.   USHORT   usVoltageLevel;              // real voltage level
  2031. }SET_VOLTAGE_PARAMETERS_V2;
  2032.  
  2033. typedef struct _SET_VOLTAGE_PS_ALLOCATION
  2034. {
  2035.         SET_VOLTAGE_PARAMETERS sASICSetVoltage;
  2036.         WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
  2037. }SET_VOLTAGE_PS_ALLOCATION;
  2038.  
  2039. /****************************************************************************/
  2040. // Structures used by TVEncoderControlTable
  2041. /****************************************************************************/
  2042. typedef struct _TV_ENCODER_CONTROL_PARAMETERS
  2043. {
  2044.   USHORT usPixelClock;                // in 10KHz; for bios convenient
  2045.   UCHAR  ucTvStandard;                // See definition "ATOM_TV_NTSC ..."
  2046.   UCHAR  ucAction;                    // 0: turn off encoder
  2047.                                       // 1: setup and turn on encoder
  2048. }TV_ENCODER_CONTROL_PARAMETERS;
  2049.  
  2050. typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
  2051. {
  2052.         TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
  2053.   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved; // Don't set this one
  2054. }TV_ENCODER_CONTROL_PS_ALLOCATION;
  2055.  
  2056. //==============================Data Table Portion====================================
  2057.  
  2058. /****************************************************************************/
  2059. // Structure used in Data.mtb
  2060. /****************************************************************************/
  2061. typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
  2062. {
  2063.   USHORT        UtilityPipeLine;                // Offest for the utility to get parser info,Don't change this position!
  2064.   USHORT        MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
  2065.   USHORT        MultimediaConfigInfo;     // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
  2066.   USHORT        StandardVESA_Timing;      // Only used by Bios
  2067.   USHORT        FirmwareInfo;             // Shared by various SW components,latest version 1.4
  2068.   USHORT        DAC_Info;                 // Will be obsolete from R600
  2069.   USHORT        LCD_Info;                 // Shared by various SW components,latest version 1.3, was called LVDS_Info
  2070.   USHORT        TMDS_Info;                // Will be obsolete from R600
  2071.   USHORT        AnalogTV_Info;            // Shared by various SW components,latest version 1.1
  2072.   USHORT        SupportedDevicesInfo;     // Will be obsolete from R600
  2073.   USHORT        GPIO_I2C_Info;            // Shared by various SW components,latest version 1.2 will be used from R600          
  2074.   USHORT        VRAM_UsageByFirmware;     // Shared by various SW components,latest version 1.3 will be used from R600
  2075.   USHORT        GPIO_Pin_LUT;             // Shared by various SW components,latest version 1.1
  2076.   USHORT        VESA_ToInternalModeLUT;   // Only used by Bios
  2077.   USHORT        ComponentVideoInfo;       // Shared by various SW components,latest version 2.1 will be used from R600
  2078.   USHORT        PowerPlayInfo;            // Shared by various SW components,latest version 2.1,new design from R600
  2079.   USHORT        CompassionateData;        // Will be obsolete from R600
  2080.   USHORT        SaveRestoreInfo;          // Only used by Bios
  2081.   USHORT        PPLL_SS_Info;             // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
  2082.   USHORT        OemInfo;                  // Defined and used by external SW, should be obsolete soon
  2083.   USHORT        XTMDS_Info;               // Will be obsolete from R600
  2084.   USHORT        MclkSS_Info;              // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
  2085.   USHORT        Object_Header;            // Shared by various SW components,latest version 1.1
  2086.   USHORT        IndirectIOAccess;         // Only used by Bios,this table position can't change at all!!
  2087.   USHORT        MC_InitParameter;         // Only used by command table
  2088.   USHORT        ASIC_VDDC_Info;                                         // Will be obsolete from R600
  2089.   USHORT        ASIC_InternalSS_Info;                   // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
  2090.   USHORT        TV_VideoMode;                                                   // Only used by command table
  2091.   USHORT        VRAM_Info;                                                              // Only used by command table, latest version 1.3
  2092.   USHORT        MemoryTrainingInfo;                             // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
  2093.   USHORT        IntegratedSystemInfo;                   // Shared by various SW components
  2094.   USHORT        ASIC_ProfilingInfo;                             // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
  2095.   USHORT        VoltageObjectInfo;                              // Shared by various SW components, latest version 1.1
  2096.         USHORT                          PowerSourceInfo;                                        // Shared by various SW components, latest versoin 1.1
  2097. }ATOM_MASTER_LIST_OF_DATA_TABLES;
  2098.  
  2099. // For backward compatible
  2100. #define LVDS_Info                LCD_Info
  2101.  
  2102. typedef struct _ATOM_MASTER_DATA_TABLE
  2103. {
  2104.         ATOM_COMMON_TABLE_HEADER sHeader;
  2105.         ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
  2106. }ATOM_MASTER_DATA_TABLE;
  2107.  
  2108.  
  2109. /****************************************************************************/
  2110. // Structure used in MultimediaCapabilityInfoTable
  2111. /****************************************************************************/
  2112. typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
  2113. {
  2114.         ATOM_COMMON_TABLE_HEADER sHeader;
  2115.   ULONG                    ulSignature;      // HW info table signature string "$ATI"
  2116.   UCHAR                    ucI2C_Type;       // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
  2117.   UCHAR                    ucTV_OutInfo;     // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
  2118.   UCHAR                    ucVideoPortInfo;  // Provides the video port capabilities
  2119.   UCHAR                    ucHostPortInfo;   // Provides host port configuration information
  2120. }ATOM_MULTIMEDIA_CAPABILITY_INFO;
  2121.  
  2122. /****************************************************************************/
  2123. // Structure used in MultimediaConfigInfoTable
  2124. /****************************************************************************/
  2125. typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
  2126. {
  2127.         ATOM_COMMON_TABLE_HEADER sHeader;
  2128.   ULONG                    ulSignature;      // MM info table signature sting "$MMT"
  2129.   UCHAR                    ucTunerInfo;      // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
  2130.   UCHAR                    ucAudioChipInfo;  // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
  2131.   UCHAR                    ucProductID;      // Defines as OEM ID or ATI board ID dependent on product type setting
  2132.   UCHAR                    ucMiscInfo1;      // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
  2133.   UCHAR                    ucMiscInfo2;      // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
  2134.   UCHAR                    ucMiscInfo3;      // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
  2135.   UCHAR                    ucMiscInfo4;      // Video Decoder Host Config (2:0) reserved (7:3)
  2136.   UCHAR                    ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
  2137.   UCHAR                    ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
  2138.   UCHAR                    ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
  2139.   UCHAR                    ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
  2140.   UCHAR                    ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
  2141. }ATOM_MULTIMEDIA_CONFIG_INFO;
  2142.  
  2143.  
  2144. /****************************************************************************/ 
  2145. // Structures used in FirmwareInfoTable
  2146. /****************************************************************************/ 
  2147.  
  2148. // usBIOSCapability Definition:
  2149. // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
  2150. // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
  2151. // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
  2152. // Others: Reserved
  2153. #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED         0x0001
  2154. #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT            0x0002
  2155. #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT     0x0004
  2156. #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT      0x0008              // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
  2157. #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT      0x0010              // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
  2158. #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU         0x0020
  2159. #define ATOM_BIOS_INFO_WMI_SUPPORT                  0x0040
  2160. #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080
  2161. #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT          0x0100
  2162. #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK        0x1E00
  2163. #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
  2164. #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE  0x4000
  2165. #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT  0x0008              // (valid from v2.1 ): =1: memclk ss enable with external ss chip
  2166. #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT  0x0010              // (valid from v2.1 ): =1: engclk ss enable with external ss chip
  2167.  
  2168. #ifndef _H2INC
  2169.  
  2170. //Please don't add or expand this bitfield structure below, this one will retire soon.!
  2171. typedef struct _ATOM_FIRMWARE_CAPABILITY
  2172. {
  2173. #if ATOM_BIG_ENDIAN
  2174.         USHORT Reserved:3;
  2175.         USHORT HyperMemory_Size:4;
  2176.         USHORT HyperMemory_Support:1;
  2177.         USHORT PPMode_Assigned:1;
  2178.         USHORT WMI_SUPPORT:1;
  2179.         USHORT GPUControlsBL:1;
  2180.         USHORT EngineClockSS_Support:1;
  2181.         USHORT MemoryClockSS_Support:1;
  2182.         USHORT ExtendedDesktopSupport:1;
  2183.         USHORT DualCRTC_Support:1;
  2184.         USHORT FirmwarePosted:1;
  2185. #else
  2186.         USHORT FirmwarePosted:1;
  2187.         USHORT DualCRTC_Support:1;
  2188.         USHORT ExtendedDesktopSupport:1;
  2189.         USHORT MemoryClockSS_Support:1;
  2190.         USHORT EngineClockSS_Support:1;
  2191.         USHORT GPUControlsBL:1;
  2192.         USHORT WMI_SUPPORT:1;
  2193.         USHORT PPMode_Assigned:1;
  2194.         USHORT HyperMemory_Support:1;
  2195.         USHORT HyperMemory_Size:4;
  2196.         USHORT Reserved:3;
  2197. #endif
  2198. }ATOM_FIRMWARE_CAPABILITY;
  2199.  
  2200. typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
  2201. {
  2202.         ATOM_FIRMWARE_CAPABILITY sbfAccess;
  2203.         USHORT susAccess;
  2204. }ATOM_FIRMWARE_CAPABILITY_ACCESS;
  2205.  
  2206. #else
  2207.  
  2208. typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
  2209. {
  2210.         USHORT susAccess;
  2211. }ATOM_FIRMWARE_CAPABILITY_ACCESS;
  2212.  
  2213. #endif
  2214.  
  2215. typedef struct _ATOM_FIRMWARE_INFO
  2216. {
  2217.         ATOM_COMMON_TABLE_HEADER sHeader;
  2218.         ULONG ulFirmwareRevision;
  2219.   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
  2220.   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
  2221.   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
  2222.   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
  2223.   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
  2224.   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
  2225.   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
  2226.   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
  2227.   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
  2228.         UCHAR ucASICMaxTemperature;
  2229.   UCHAR                           ucPadding[3];               //Don't use them
  2230.   ULONG                           aulReservedForBIOS[3];      //Don't use them
  2231.   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
  2232.   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
  2233.   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
  2234.   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
  2235.   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
  2236.   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
  2237.   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
  2238.   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
  2239.   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
  2240.   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit, the definitions above can't change!!!
  2241.         ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
  2242.   USHORT                          usReferenceClock;           //In 10Khz unit  
  2243.   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
  2244.   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
  2245.   UCHAR                           ucDesign_ID;                //Indicate what is the board design
  2246.   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
  2247. }ATOM_FIRMWARE_INFO;
  2248.  
  2249. typedef struct _ATOM_FIRMWARE_INFO_V1_2
  2250. {
  2251.         ATOM_COMMON_TABLE_HEADER sHeader;
  2252.         ULONG ulFirmwareRevision;
  2253.   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
  2254.   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
  2255.   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
  2256.   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
  2257.   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
  2258.   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
  2259.   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
  2260.   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
  2261.   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
  2262.         UCHAR ucASICMaxTemperature;
  2263.         UCHAR ucMinAllowedBL_Level;
  2264.   UCHAR                           ucPadding[2];               //Don't use them
  2265.   ULONG                           aulReservedForBIOS[2];      //Don't use them
  2266.   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
  2267.   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
  2268.   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
  2269.   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
  2270.   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
  2271.   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
  2272.   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
  2273.   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
  2274.   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
  2275.   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
  2276.   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
  2277.         ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
  2278.   USHORT                          usReferenceClock;           //In 10Khz unit  
  2279.   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
  2280.   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
  2281.   UCHAR                           ucDesign_ID;                //Indicate what is the board design
  2282.   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
  2283. }ATOM_FIRMWARE_INFO_V1_2;
  2284.  
  2285. typedef struct _ATOM_FIRMWARE_INFO_V1_3
  2286. {
  2287.         ATOM_COMMON_TABLE_HEADER sHeader;
  2288.         ULONG ulFirmwareRevision;
  2289.   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
  2290.   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
  2291.   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
  2292.   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
  2293.   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
  2294.   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
  2295.   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
  2296.   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
  2297.   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
  2298.         UCHAR ucASICMaxTemperature;
  2299.         UCHAR ucMinAllowedBL_Level;
  2300.   UCHAR                           ucPadding[2];               //Don't use them
  2301.   ULONG                           aulReservedForBIOS;         //Don't use them
  2302.   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
  2303.   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
  2304.   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
  2305.   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
  2306.   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
  2307.   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
  2308.   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
  2309.   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
  2310.   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
  2311.   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
  2312.   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
  2313.   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
  2314.         ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
  2315.   USHORT                          usReferenceClock;           //In 10Khz unit  
  2316.   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
  2317.   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
  2318.   UCHAR                           ucDesign_ID;                //Indicate what is the board design
  2319.   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
  2320. }ATOM_FIRMWARE_INFO_V1_3;
  2321.  
  2322. typedef struct _ATOM_FIRMWARE_INFO_V1_4
  2323. {
  2324.         ATOM_COMMON_TABLE_HEADER sHeader;
  2325.         ULONG ulFirmwareRevision;
  2326.   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
  2327.   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
  2328.   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
  2329.   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
  2330.   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
  2331.   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
  2332.   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
  2333.   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
  2334.   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
  2335.         UCHAR ucASICMaxTemperature;
  2336.         UCHAR ucMinAllowedBL_Level;
  2337.   USHORT                          usBootUpVDDCVoltage;        //In MV unit
  2338.   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
  2339.   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
  2340.   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
  2341.   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
  2342.   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
  2343.   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
  2344.   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
  2345.   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
  2346.   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
  2347.   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
  2348.   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
  2349.   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
  2350.   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
  2351.   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
  2352.   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
  2353.   USHORT                          usReferenceClock;           //In 10Khz unit  
  2354.   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
  2355.   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
  2356.   UCHAR                           ucDesign_ID;                //Indicate what is the board design
  2357.   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
  2358. }ATOM_FIRMWARE_INFO_V1_4;
  2359.  
  2360. //the structure below to be used from Cypress
  2361. typedef struct _ATOM_FIRMWARE_INFO_V2_1
  2362. {
  2363.   ATOM_COMMON_TABLE_HEADER        sHeader;
  2364.   ULONG                           ulFirmwareRevision;
  2365.   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
  2366.   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
  2367.   ULONG                           ulReserved1;
  2368.   ULONG                           ulReserved2;
  2369.   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
  2370.   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
  2371.   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
  2372.   ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock
  2373.   ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit
  2374.   UCHAR                           ucReserved1;                //Was ucASICMaxTemperature;
  2375.   UCHAR                           ucMinAllowedBL_Level;
  2376.   USHORT                          usBootUpVDDCVoltage;        //In MV unit
  2377.   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
  2378.   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
  2379.   ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
  2380.   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
  2381.   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
  2382.   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
  2383.   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
  2384.   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
  2385.   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
  2386.   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
  2387.   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
  2388.   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
  2389.   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
  2390.   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
  2391.         ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
  2392.   USHORT                          usCoreReferenceClock;       //In 10Khz unit  
  2393.   USHORT                          usMemoryReferenceClock;     //In 10Khz unit  
  2394.   USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
  2395.   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
  2396.   UCHAR                           ucReserved4[3];
  2397. }ATOM_FIRMWARE_INFO_V2_1;
  2398.  
  2399. //the structure below to be used from NI
  2400. //ucTableFormatRevision=2
  2401. //ucTableContentRevision=2
  2402. typedef struct _ATOM_FIRMWARE_INFO_V2_2
  2403. {
  2404.   ATOM_COMMON_TABLE_HEADER        sHeader;
  2405.   ULONG                           ulFirmwareRevision;
  2406.   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
  2407.   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
  2408.   ULONG                           ulReserved[2];
  2409.   ULONG                           ulReserved1;                //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
  2410.   ULONG                           ulReserved2;                //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
  2411.   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
  2412.   ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock  ?
  2413.   ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.          
  2414.   UCHAR                           ucReserved3;                //Was ucASICMaxTemperature;
  2415.   UCHAR                           ucMinAllowedBL_Level;
  2416.   USHORT                          usBootUpVDDCVoltage;        //In MV unit
  2417.   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
  2418.   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
  2419.   ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
  2420.   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
  2421.   ULONG                           ulReserved5;                //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
  2422.   ULONG                           ulReserved6;                //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
  2423.   ULONG                           ulReserved7;                //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
  2424.   USHORT                          usReserved11;               //Was usMaxPixelClock;  //In 10Khz unit, Max.  Pclk used only for DAC
  2425.   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
  2426.   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
  2427.   USHORT                          usBootUpVDDCIVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
  2428.   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
  2429.   USHORT                          usCoreReferenceClock;       //In 10Khz unit  
  2430.   USHORT                          usMemoryReferenceClock;     //In 10Khz unit  
  2431.   USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
  2432.   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
  2433.   UCHAR                           ucReserved9[3];
  2434.   USHORT                          usBootUpMVDDCVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
  2435.   USHORT                          usReserved12;
  2436.   ULONG                           ulReserved10[3];            // New added comparing to previous version
  2437. }ATOM_FIRMWARE_INFO_V2_2;
  2438.  
  2439. #define ATOM_FIRMWARE_INFO_LAST  ATOM_FIRMWARE_INFO_V2_2
  2440.  
  2441. /****************************************************************************/
  2442. // Structures used in IntegratedSystemInfoTable
  2443. /****************************************************************************/
  2444. #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN      0x2
  2445. #define IGP_CAP_FLAG_AC_CARD               0x4
  2446. #define IGP_CAP_FLAG_SDVO_CARD             0x8
  2447. #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE     0x10
  2448.  
  2449. typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
  2450. {
  2451.         ATOM_COMMON_TABLE_HEADER sHeader;
  2452.   ULONG                           ulBootUpEngineClock;              //in 10kHz unit
  2453.   ULONG                           ulBootUpMemoryClock;              //in 10kHz unit
  2454.   ULONG                           ulMaxSystemMemoryClock;           //in 10kHz unit
  2455.   ULONG                           ulMinSystemMemoryClock;           //in 10kHz unit
  2456.         UCHAR ucNumberOfCyclesInPeriodHi;
  2457.   UCHAR                           ucLCDTimingSel;             //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
  2458.         USHORT usReserved1;
  2459.   USHORT                          usInterNBVoltageLow;        //An intermidiate PMW value to set the voltage
  2460.   USHORT                          usInterNBVoltageHigh;       //Another intermidiate PMW value to set the voltage
  2461.         ULONG ulReserved[2];
  2462.  
  2463.   USHORT                                usFSBClock;                                 //In MHz unit
  2464.   USHORT                          usCapabilityFlag;                     //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
  2465.                                                                                                                                                               //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
  2466.                                                               //Bit[4]==1: P/2 mode, ==0: P/1 mode
  2467.   USHORT                                usPCIENBCfgReg7;                                    //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
  2468.   USHORT                                usK8MemoryClock;            //in MHz unit
  2469.   USHORT                                usK8SyncStartDelay;         //in 0.01 us unit
  2470.   USHORT                                usK8DataReturnTime;         //in 0.01 us unit
  2471.         UCHAR ucMaxNBVoltage;
  2472.         UCHAR ucMinNBVoltage;
  2473.   UCHAR                           ucMemoryType;                                       //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
  2474.   UCHAR                           ucNumberOfCyclesInPeriod;             //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
  2475.   UCHAR                           ucStartingPWM_HighTime;     //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
  2476.   UCHAR                           ucHTLinkWidth;              //16 bit vs. 8 bit
  2477.         UCHAR ucMaxNBVoltageHigh;
  2478.         UCHAR ucMinNBVoltageHigh;
  2479. }ATOM_INTEGRATED_SYSTEM_INFO;
  2480.  
  2481. /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
  2482. ulBootUpMemoryClock:    For Intel IGP,it's the UMA system memory clock
  2483.                         For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
  2484. ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
  2485.                         For AMD IGP,for now this can be 0
  2486. ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
  2487.                         For AMD IGP,for now this can be 0
  2488.  
  2489. usFSBClock:             For Intel IGP,it's FSB Freq
  2490.                         For AMD IGP,it's HT Link Speed
  2491.  
  2492. usK8MemoryClock:        For AMD IGP only. For RevF CPU, set it to 200
  2493. usK8SyncStartDelay:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
  2494. usK8DataReturnTime:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
  2495.  
  2496. VC:Voltage Control
  2497. ucMaxNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
  2498. ucMinNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
  2499.  
  2500. ucNumberOfCyclesInPeriod:   Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
  2501. ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
  2502.  
  2503. ucMaxNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of  the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
  2504. ucMinNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
  2505.  
  2506.  
  2507. usInterNBVoltageLow:    Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
  2508. usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
  2509. */
  2510.  
  2511.  
  2512. /*
  2513. The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
  2514. Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
  2515. The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
  2516.  
  2517. SW components can access the IGP system infor structure in the same way as before
  2518. */
  2519.  
  2520.  
  2521. typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
  2522. {
  2523.         ATOM_COMMON_TABLE_HEADER sHeader;
  2524.   ULONG                      ulBootUpEngineClock;       //in 10kHz unit
  2525.   ULONG                      ulReserved1[2];            //must be 0x0 for the reserved
  2526.   ULONG                      ulBootUpUMAClock;          //in 10kHz unit
  2527.   ULONG                      ulBootUpSidePortClock;     //in 10kHz unit
  2528.   ULONG                      ulMinSidePortClock;        //in 10kHz unit
  2529.   ULONG                      ulReserved2[6];            //must be 0x0 for the reserved
  2530.   ULONG                      ulSystemConfig;            //see explanation below
  2531.         ULONG ulBootUpReqDisplayVector;
  2532.         ULONG ulOtherDisplayMisc;
  2533.         ULONG ulDDISlot1Config;
  2534.         ULONG ulDDISlot2Config;
  2535.   UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
  2536.         UCHAR ucUMAChannelNumber;
  2537.         UCHAR ucDockingPinBit;
  2538.         UCHAR ucDockingPinPolarity;
  2539.         ULONG ulDockingPinCFGInfo;
  2540.         ULONG ulCPUCapInfo;
  2541.         USHORT usNumberOfCyclesInPeriod;
  2542.         USHORT usMaxNBVoltage;
  2543.         USHORT usMinNBVoltage;
  2544.         USHORT usBootUpNBVoltage;
  2545.   ULONG                      ulHTLinkFreq;              //in 10Khz
  2546.         USHORT usMinHTLinkWidth;
  2547.         USHORT usMaxHTLinkWidth;
  2548.         USHORT usUMASyncStartDelay;
  2549.         USHORT usUMADataReturnTime;
  2550.         USHORT usLinkStatusZeroTime;
  2551.   USHORT                     usDACEfuse;                                //for storing badgap value (for RS880 only)
  2552.   ULONG                      ulHighVoltageHTLinkFreq;     // in 10Khz
  2553.   ULONG                      ulLowVoltageHTLinkFreq;      // in 10Khz
  2554.         USHORT usMaxUpStreamHTLinkWidth;
  2555.         USHORT usMaxDownStreamHTLinkWidth;
  2556.         USHORT usMinUpStreamHTLinkWidth;
  2557.         USHORT usMinDownStreamHTLinkWidth;
  2558.   USHORT                     usFirmwareVersion;         //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
  2559.   USHORT                     usFullT0Time;             // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
  2560.   ULONG                      ulReserved3[96];          //must be 0x0
  2561. }ATOM_INTEGRATED_SYSTEM_INFO_V2;  
  2562.  
  2563. /*
  2564. ulBootUpEngineClock:   Boot-up Engine Clock in 10Khz;
  2565. ulBootUpUMAClock:      Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
  2566. ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
  2567.  
  2568. ulSystemConfig:
  2569. Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
  2570. Bit[1]=1: system boots up at AMD overdrived state or user customized  mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
  2571.       =0: system boots up at driver control state. Power state depends on PowerPlay table.
  2572. Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
  2573. Bit[3]=1: Only one power state(Performance) will be supported.
  2574.       =0: Multiple power states supported from PowerPlay table.
  2575. Bit[4]=1: CLMC is supported and enabled on current system.
  2576.       =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
  2577. Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
  2578.       =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
  2579. Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
  2580.       =0: Voltage settings is determined by powerplay table.
  2581. Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
  2582.       =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
  2583. Bit[8]=1: CDLF is supported and enabled on current system.
  2584.       =0: CDLF is not supported or enabled on current system.
  2585. Bit[9]=1: DLL Shut Down feature is enabled on current system.
  2586.       =0: DLL Shut Down feature is not enabled or supported on current system.
  2587.  
  2588. ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
  2589.  
  2590. ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
  2591.                                       [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition;
  2592.  
  2593. ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
  2594.       [3:0]  - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
  2595.                         [7:4]  - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
  2596.       When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
  2597.       in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
  2598.       one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
  2599.  
  2600.                         [15:8] - Lane configuration attribute;
  2601.       [23:16]- Connector type, possible value:
  2602.                CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
  2603.                CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
  2604.                CONNECTOR_OBJECT_ID_HDMI_TYPE_A
  2605.                CONNECTOR_OBJECT_ID_DISPLAYPORT
  2606.                CONNECTOR_OBJECT_ID_eDP
  2607.                         [31:24]- Reserved
  2608.  
  2609. ulDDISlot2Config: Same as Slot1.
  2610. ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
  2611. For IGP, Hypermemory is the only memory type showed in CCC.
  2612.  
  2613. ucUMAChannelNumber:  how many channels for the UMA;
  2614.  
  2615. ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
  2616. ucDockingPinBit:     which bit in this register to read the pin status;
  2617. ucDockingPinPolarity:Polarity of the pin when docked;
  2618.  
  2619. ulCPUCapInfo:        [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
  2620.  
  2621. usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
  2622.  
  2623. usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
  2624. usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
  2625.                     GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
  2626.                     PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
  2627.                     GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
  2628.  
  2629. usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
  2630.  
  2631. ulHTLinkFreq:       Bootup HT link Frequency in 10Khz.
  2632. usMinHTLinkWidth:   Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
  2633.                     If CDLW enabled, both upstream and downstream width should be the same during bootup.
  2634. usMaxHTLinkWidth:   Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
  2635.                     If CDLW enabled, both upstream and downstream width should be the same during bootup.
  2636.  
  2637. usUMASyncStartDelay: Memory access latency, required for watermark calculation
  2638. usUMADataReturnTime: Memory access latency, required for watermark calculation
  2639. usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
  2640. for Griffin or Greyhound. SBIOS needs to convert to actual time by:
  2641.                      if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
  2642.                      if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
  2643.                      if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
  2644.                      if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
  2645.  
  2646. ulHighVoltageHTLinkFreq:     HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
  2647.                              This must be less than or equal to ulHTLinkFreq(bootup frequency).
  2648. ulLowVoltageHTLinkFreq:      HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
  2649.                              This must be less than or equal to ulHighVoltageHTLinkFreq.
  2650.  
  2651. usMaxUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
  2652. usMaxDownStreamHTLinkWidth:  same as above.
  2653. usMinUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
  2654. usMinDownStreamHTLinkWidth:  same as above.
  2655. */
  2656.  
  2657. // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo  - CPU type definition
  2658. #define    INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU             0
  2659. #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN        1
  2660. #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND      2
  2661. #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__K8             3
  2662. #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH        4
  2663.  
  2664. #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE       INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH    // this deff reflects max defined CPU code
  2665.  
  2666. #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE                 0x00000001
  2667. #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE             0x00000002
  2668. #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE                  0x00000004
  2669. #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY         0x00000008
  2670. #define SYSTEM_CONFIG_CLMC_ENABLED                        0x00000010
  2671. #define SYSTEM_CONFIG_CDLW_ENABLED                        0x00000020
  2672. #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED              0x00000040
  2673. #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED            0x00000080
  2674. #define SYSTEM_CONFIG_CDLF_ENABLED                        0x00000100
  2675. #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED                0x00000200
  2676.  
  2677. #define IGP_DDI_SLOT_LANE_CONFIG_MASK                     0x000000FF
  2678.  
  2679. #define b0IGP_DDI_SLOT_LANE_MAP_MASK                      0x0F
  2680. #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK              0xF0
  2681. #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3                    0x01
  2682. #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7                    0x02
  2683. #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11                   0x04
  2684. #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15                  0x08
  2685.  
  2686. #define IGP_DDI_SLOT_ATTRIBUTE_MASK                       0x0000FF00
  2687. #define IGP_DDI_SLOT_CONFIG_REVERSED                      0x00000100
  2688. #define b1IGP_DDI_SLOT_CONFIG_REVERSED                    0x01
  2689.  
  2690. #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK                  0x00FF0000
  2691.  
  2692. // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
  2693. typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
  2694. {
  2695.   ATOM_COMMON_TABLE_HEADER   sHeader;
  2696.   ULONG                      ulBootUpEngineClock;       //in 10kHz unit
  2697.   ULONG                      ulDentistVCOFreq;          //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
  2698.   ULONG                      ulLClockFreq;              //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
  2699.   ULONG                      ulBootUpUMAClock;          //in 10kHz unit
  2700.   ULONG                      ulReserved1[8];            //must be 0x0 for the reserved
  2701.   ULONG                      ulBootUpReqDisplayVector;
  2702.   ULONG                      ulOtherDisplayMisc;
  2703.   ULONG                      ulReserved2[4];            //must be 0x0 for the reserved
  2704.   ULONG                      ulSystemConfig;            //TBD
  2705.   ULONG                      ulCPUCapInfo;              //TBD
  2706.   USHORT                     usMaxNBVoltage;            //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
  2707.   USHORT                     usMinNBVoltage;            //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
  2708.   USHORT                     usBootUpNBVoltage;         //boot up NB voltage
  2709.   UCHAR                      ucHtcTmpLmt;               //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
  2710.   UCHAR                      ucTjOffset;                //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
  2711.   ULONG                      ulReserved3[4];            //must be 0x0 for the reserved
  2712.   ULONG                      ulDDISlot1Config;          //see above ulDDISlot1Config definition
  2713.   ULONG                      ulDDISlot2Config;
  2714.   ULONG                      ulDDISlot3Config;
  2715.   ULONG                      ulDDISlot4Config;
  2716.   ULONG                      ulReserved4[4];            //must be 0x0 for the reserved
  2717.   UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
  2718.   UCHAR                      ucUMAChannelNumber;
  2719.   USHORT                     usReserved;
  2720.   ULONG                      ulReserved5[4];            //must be 0x0 for the reserved
  2721.   ULONG                      ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
  2722.   ULONG                      ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
  2723.   ULONG                      ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
  2724.   ULONG                      ulReserved6[61];           //must be 0x0
  2725. }ATOM_INTEGRATED_SYSTEM_INFO_V5;  
  2726.  
  2727. #define ATOM_CRT_INT_ENCODER1_INDEX                       0x00000000
  2728. #define ATOM_LCD_INT_ENCODER1_INDEX                       0x00000001
  2729. #define ATOM_TV_INT_ENCODER1_INDEX                        0x00000002
  2730. #define ATOM_DFP_INT_ENCODER1_INDEX                       0x00000003
  2731. #define ATOM_CRT_INT_ENCODER2_INDEX                       0x00000004
  2732. #define ATOM_LCD_EXT_ENCODER1_INDEX                       0x00000005
  2733. #define ATOM_TV_EXT_ENCODER1_INDEX                        0x00000006
  2734. #define ATOM_DFP_EXT_ENCODER1_INDEX                       0x00000007
  2735. #define ATOM_CV_INT_ENCODER1_INDEX                        0x00000008
  2736. #define ATOM_DFP_INT_ENCODER2_INDEX                       0x00000009
  2737. #define ATOM_CRT_EXT_ENCODER1_INDEX                       0x0000000A
  2738. #define ATOM_CV_EXT_ENCODER1_INDEX                        0x0000000B
  2739. #define ATOM_DFP_INT_ENCODER3_INDEX                       0x0000000C
  2740. #define ATOM_DFP_INT_ENCODER4_INDEX                       0x0000000D
  2741.  
  2742. // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
  2743. #define ASIC_INT_DAC1_ENCODER_ID                                                                                        0x00
  2744. #define ASIC_INT_TV_ENCODER_ID                                                                                                          0x02
  2745. #define ASIC_INT_DIG1_ENCODER_ID                                                                                                        0x03
  2746. #define ASIC_INT_DAC2_ENCODER_ID                                                                                                        0x04
  2747. #define ASIC_EXT_TV_ENCODER_ID                                                                                                          0x06
  2748. #define ASIC_INT_DVO_ENCODER_ID                                                                                                         0x07
  2749. #define ASIC_INT_DIG2_ENCODER_ID                                                                                                        0x09
  2750. #define ASIC_EXT_DIG_ENCODER_ID                                                                                                         0x05
  2751. #define ASIC_EXT_DIG2_ENCODER_ID                                                                                                        0x08
  2752. #define ASIC_INT_DIG3_ENCODER_ID                                                                                                        0x0a
  2753. #define ASIC_INT_DIG4_ENCODER_ID                                                                                                        0x0b
  2754. #define ASIC_INT_DIG5_ENCODER_ID                                                                                                        0x0c
  2755. #define ASIC_INT_DIG6_ENCODER_ID                                                                                                        0x0d
  2756.  
  2757. //define Encoder attribute
  2758. #define ATOM_ANALOG_ENCODER                                                                                                                             0
  2759. #define ATOM_DIGITAL_ENCODER                                                                                                                    1
  2760. #define ATOM_DP_ENCODER                                                                                                                       2        
  2761.  
  2762. #define ATOM_ENCODER_ENUM_MASK                            0x70
  2763. #define ATOM_ENCODER_ENUM_ID1                             0x00
  2764. #define ATOM_ENCODER_ENUM_ID2                             0x10
  2765. #define ATOM_ENCODER_ENUM_ID3                             0x20
  2766. #define ATOM_ENCODER_ENUM_ID4                             0x30
  2767. #define ATOM_ENCODER_ENUM_ID5                             0x40
  2768. #define ATOM_ENCODER_ENUM_ID6                             0x50
  2769.  
  2770. #define ATOM_DEVICE_CRT1_INDEX                            0x00000000
  2771. #define ATOM_DEVICE_LCD1_INDEX                            0x00000001
  2772. #define ATOM_DEVICE_TV1_INDEX                             0x00000002
  2773. #define ATOM_DEVICE_DFP1_INDEX                            0x00000003
  2774. #define ATOM_DEVICE_CRT2_INDEX                            0x00000004
  2775. #define ATOM_DEVICE_LCD2_INDEX                            0x00000005
  2776. #define ATOM_DEVICE_DFP6_INDEX                            0x00000006
  2777. #define ATOM_DEVICE_DFP2_INDEX                            0x00000007
  2778. #define ATOM_DEVICE_CV_INDEX                              0x00000008
  2779. #define ATOM_DEVICE_DFP3_INDEX                                                                                                          0x00000009
  2780. #define ATOM_DEVICE_DFP4_INDEX                                                                                                          0x0000000A
  2781. #define ATOM_DEVICE_DFP5_INDEX                                                                                                          0x0000000B
  2782.  
  2783. #define ATOM_DEVICE_RESERVEDC_INDEX                       0x0000000C
  2784. #define ATOM_DEVICE_RESERVEDD_INDEX                       0x0000000D
  2785. #define ATOM_DEVICE_RESERVEDE_INDEX                       0x0000000E
  2786. #define ATOM_DEVICE_RESERVEDF_INDEX                       0x0000000F
  2787. #define ATOM_MAX_SUPPORTED_DEVICE_INFO                    (ATOM_DEVICE_DFP3_INDEX+1)
  2788. #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2                  ATOM_MAX_SUPPORTED_DEVICE_INFO
  2789. #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3                  (ATOM_DEVICE_DFP5_INDEX + 1 )
  2790.  
  2791. #define ATOM_MAX_SUPPORTED_DEVICE                         (ATOM_DEVICE_RESERVEDF_INDEX+1)
  2792.  
  2793. #define ATOM_DEVICE_CRT1_SUPPORT                          (0x1L << ATOM_DEVICE_CRT1_INDEX )
  2794. #define ATOM_DEVICE_LCD1_SUPPORT                          (0x1L << ATOM_DEVICE_LCD1_INDEX )
  2795. #define ATOM_DEVICE_TV1_SUPPORT                           (0x1L << ATOM_DEVICE_TV1_INDEX  )
  2796. #define ATOM_DEVICE_DFP1_SUPPORT                          (0x1L << ATOM_DEVICE_DFP1_INDEX )
  2797. #define ATOM_DEVICE_CRT2_SUPPORT                          (0x1L << ATOM_DEVICE_CRT2_INDEX )
  2798. #define ATOM_DEVICE_LCD2_SUPPORT                          (0x1L << ATOM_DEVICE_LCD2_INDEX )
  2799. #define ATOM_DEVICE_DFP6_SUPPORT                          (0x1L << ATOM_DEVICE_DFP6_INDEX )
  2800. #define ATOM_DEVICE_DFP2_SUPPORT                          (0x1L << ATOM_DEVICE_DFP2_INDEX )
  2801. #define ATOM_DEVICE_CV_SUPPORT                            (0x1L << ATOM_DEVICE_CV_INDEX   )
  2802. #define ATOM_DEVICE_DFP3_SUPPORT                          (0x1L << ATOM_DEVICE_DFP3_INDEX )
  2803. #define ATOM_DEVICE_DFP4_SUPPORT                                                                                                        (0x1L << ATOM_DEVICE_DFP4_INDEX )
  2804. #define ATOM_DEVICE_DFP5_SUPPORT                          (0x1L << ATOM_DEVICE_DFP5_INDEX )
  2805.  
  2806. #define ATOM_DEVICE_CRT_SUPPORT                           (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
  2807. #define ATOM_DEVICE_DFP_SUPPORT                           (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT |  ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
  2808. #define ATOM_DEVICE_TV_SUPPORT                            (ATOM_DEVICE_TV1_SUPPORT)
  2809. #define ATOM_DEVICE_LCD_SUPPORT                           (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
  2810.  
  2811. #define ATOM_DEVICE_CONNECTOR_TYPE_MASK                   0x000000F0
  2812. #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT                  0x00000004
  2813. #define ATOM_DEVICE_CONNECTOR_VGA                         0x00000001
  2814. #define ATOM_DEVICE_CONNECTOR_DVI_I                       0x00000002
  2815. #define ATOM_DEVICE_CONNECTOR_DVI_D                       0x00000003
  2816. #define ATOM_DEVICE_CONNECTOR_DVI_A                       0x00000004
  2817. #define ATOM_DEVICE_CONNECTOR_SVIDEO                      0x00000005
  2818. #define ATOM_DEVICE_CONNECTOR_COMPOSITE                   0x00000006
  2819. #define ATOM_DEVICE_CONNECTOR_LVDS                        0x00000007
  2820. #define ATOM_DEVICE_CONNECTOR_DIGI_LINK                   0x00000008
  2821. #define ATOM_DEVICE_CONNECTOR_SCART                       0x00000009
  2822. #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A                 0x0000000A
  2823. #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B                 0x0000000B
  2824. #define ATOM_DEVICE_CONNECTOR_CASE_1                      0x0000000E
  2825. #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT                 0x0000000F
  2826.  
  2827.  
  2828. #define ATOM_DEVICE_DAC_INFO_MASK                         0x0000000F
  2829. #define ATOM_DEVICE_DAC_INFO_SHIFT                        0x00000000
  2830. #define ATOM_DEVICE_DAC_INFO_NODAC                        0x00000000
  2831. #define ATOM_DEVICE_DAC_INFO_DACA                         0x00000001
  2832. #define ATOM_DEVICE_DAC_INFO_DACB                         0x00000002
  2833. #define ATOM_DEVICE_DAC_INFO_EXDAC                        0x00000003
  2834.  
  2835. #define ATOM_DEVICE_I2C_ID_NOI2C                          0x00000000
  2836.  
  2837. #define ATOM_DEVICE_I2C_LINEMUX_MASK                      0x0000000F
  2838. #define ATOM_DEVICE_I2C_LINEMUX_SHIFT                     0x00000000
  2839.  
  2840. #define ATOM_DEVICE_I2C_ID_MASK                           0x00000070
  2841. #define ATOM_DEVICE_I2C_ID_SHIFT                          0x00000004
  2842. #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE              0x00000001
  2843. #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE                  0x00000002
  2844. #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE                0x00000003    //For IGP RS600
  2845. #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL                 0x00000004    //For IGP RS690
  2846.  
  2847. #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK                 0x00000080
  2848. #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT                0x00000007
  2849. #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C            0x00000000
  2850. #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C            0x00000001
  2851.  
  2852. //  usDeviceSupport:
  2853. //  Bits0       = 0 - no CRT1 support= 1- CRT1 is supported
  2854. //  Bit 1       = 0 - no LCD1 support= 1- LCD1 is supported
  2855. //  Bit 2       = 0 - no TV1  support= 1- TV1  is supported
  2856. //  Bit 3       = 0 - no DFP1 support= 1- DFP1 is supported
  2857. //  Bit 4       = 0 - no CRT2 support= 1- CRT2 is supported
  2858. //  Bit 5       = 0 - no LCD2 support= 1- LCD2 is supported
  2859. //  Bit 6       = 0 - no DFP6 support= 1- DFP6 is supported
  2860. //  Bit 7       = 0 - no DFP2 support= 1- DFP2 is supported
  2861. //  Bit 8       = 0 - no CV   support= 1- CV   is supported
  2862. //  Bit 9       = 0 - no DFP3 support= 1- DFP3 is supported
  2863. //  Bit 10      = 0 - no DFP4 support= 1- DFP4 is supported
  2864. //  Bit 11      = 0 - no DFP5 support= 1- DFP5 is supported
  2865. //  
  2866. //  
  2867.  
  2868. /****************************************************************************/
  2869. /* Structure used in MclkSS_InfoTable                                       */
  2870. /****************************************************************************/
  2871. //              ucI2C_ConfigID
  2872. //    [7:0] - I2C LINE Associate ID
  2873. //          = 0   - no I2C
  2874. //    [7]               -       HW_Cap        = 1,  [6:0]=HW assisted I2C ID(HW line selection)
  2875. //                          =   0,  [6:0]=SW assisted I2C ID
  2876. //    [6-4]     - HW_ENGINE_ID  =       1,  HW engine for NON multimedia use
  2877. //                          =   2,      HW engine for Multimedia use
  2878. //                          =   3-7     Reserved for future I2C engines
  2879. //              [3-0] - I2C_LINE_MUX  = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
  2880.  
  2881. typedef struct _ATOM_I2C_ID_CONFIG
  2882. {
  2883. #if ATOM_BIG_ENDIAN
  2884.         UCHAR bfHW_Capable:1;
  2885.         UCHAR bfHW_EngineID:3;
  2886.         UCHAR bfI2C_LineMux:4;
  2887. #else
  2888.         UCHAR bfI2C_LineMux:4;
  2889.         UCHAR bfHW_EngineID:3;
  2890.         UCHAR bfHW_Capable:1;
  2891. #endif
  2892. }ATOM_I2C_ID_CONFIG;
  2893.  
  2894. typedef union _ATOM_I2C_ID_CONFIG_ACCESS
  2895. {
  2896.         ATOM_I2C_ID_CONFIG sbfAccess;
  2897.         UCHAR ucAccess;
  2898. }ATOM_I2C_ID_CONFIG_ACCESS;
  2899.    
  2900.  
  2901. /****************************************************************************/
  2902. // Structure used in GPIO_I2C_InfoTable
  2903. /****************************************************************************/
  2904. typedef struct _ATOM_GPIO_I2C_ASSIGMENT
  2905. {
  2906.         USHORT usClkMaskRegisterIndex;
  2907.         USHORT usClkEnRegisterIndex;
  2908.         USHORT usClkY_RegisterIndex;
  2909.         USHORT usClkA_RegisterIndex;
  2910.         USHORT usDataMaskRegisterIndex;
  2911.         USHORT usDataEnRegisterIndex;
  2912.         USHORT usDataY_RegisterIndex;
  2913.         USHORT usDataA_RegisterIndex;
  2914.         ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
  2915.         UCHAR ucClkMaskShift;
  2916.         UCHAR ucClkEnShift;
  2917.         UCHAR ucClkY_Shift;
  2918.         UCHAR ucClkA_Shift;
  2919.         UCHAR ucDataMaskShift;
  2920.         UCHAR ucDataEnShift;
  2921.         UCHAR ucDataY_Shift;
  2922.         UCHAR ucDataA_Shift;
  2923.         UCHAR ucReserved1;
  2924.         UCHAR ucReserved2;
  2925. }ATOM_GPIO_I2C_ASSIGMENT;
  2926.  
  2927. typedef struct _ATOM_GPIO_I2C_INFO
  2928. {
  2929.         ATOM_COMMON_TABLE_HEADER sHeader;
  2930.         ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
  2931. }ATOM_GPIO_I2C_INFO;
  2932.  
  2933. /****************************************************************************/
  2934. // Common Structure used in other structures
  2935. /****************************************************************************/
  2936.  
  2937. #ifndef _H2INC
  2938.  
  2939. //Please don't add or expand this bitfield structure below, this one will retire soon.!
  2940. typedef struct _ATOM_MODE_MISC_INFO
  2941. {
  2942. #if ATOM_BIG_ENDIAN
  2943.         USHORT Reserved:6;
  2944.         USHORT RGB888:1;
  2945.         USHORT DoubleClock:1;
  2946.         USHORT Interlace:1;
  2947.         USHORT CompositeSync:1;
  2948.         USHORT V_ReplicationBy2:1;
  2949.         USHORT H_ReplicationBy2:1;
  2950.         USHORT VerticalCutOff:1;
  2951.   USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
  2952.   USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
  2953.         USHORT HorizontalCutOff:1;
  2954. #else
  2955.         USHORT HorizontalCutOff:1;
  2956.   USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
  2957.   USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
  2958.         USHORT VerticalCutOff:1;
  2959.         USHORT H_ReplicationBy2:1;
  2960.         USHORT V_ReplicationBy2:1;
  2961.         USHORT CompositeSync:1;
  2962.         USHORT Interlace:1;
  2963.         USHORT DoubleClock:1;
  2964.         USHORT RGB888:1;
  2965.         USHORT Reserved:6;
  2966. #endif
  2967. }ATOM_MODE_MISC_INFO;
  2968.  
  2969. typedef union _ATOM_MODE_MISC_INFO_ACCESS
  2970. {
  2971.         ATOM_MODE_MISC_INFO sbfAccess;
  2972.         USHORT usAccess;
  2973. }ATOM_MODE_MISC_INFO_ACCESS;
  2974.  
  2975. #else
  2976.  
  2977. typedef union _ATOM_MODE_MISC_INFO_ACCESS
  2978. {
  2979.         USHORT usAccess;
  2980. }ATOM_MODE_MISC_INFO_ACCESS;
  2981.  
  2982. #endif
  2983.  
  2984. // usModeMiscInfo-
  2985. #define ATOM_H_CUTOFF           0x01
  2986. #define ATOM_HSYNC_POLARITY     0x02             //0=Active High, 1=Active Low
  2987. #define ATOM_VSYNC_POLARITY     0x04             //0=Active High, 1=Active Low
  2988. #define ATOM_V_CUTOFF           0x08
  2989. #define ATOM_H_REPLICATIONBY2   0x10
  2990. #define ATOM_V_REPLICATIONBY2   0x20
  2991. #define ATOM_COMPOSITESYNC      0x40
  2992. #define ATOM_INTERLACE          0x80
  2993. #define ATOM_DOUBLE_CLOCK_MODE  0x100
  2994. #define ATOM_RGB888_MODE        0x200
  2995.  
  2996. //usRefreshRate-
  2997. #define ATOM_REFRESH_43         43
  2998. #define ATOM_REFRESH_47         47
  2999. #define ATOM_REFRESH_56         56
  3000. #define ATOM_REFRESH_60         60
  3001. #define ATOM_REFRESH_65         65
  3002. #define ATOM_REFRESH_70         70
  3003. #define ATOM_REFRESH_72         72
  3004. #define ATOM_REFRESH_75         75
  3005. #define ATOM_REFRESH_85         85
  3006.  
  3007. // ATOM_MODE_TIMING data are exactly the same as VESA timing data.
  3008. // Translation from EDID to ATOM_MODE_TIMING, use the following formula.
  3009. //
  3010. //      VESA_HTOTAL                     =       VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
  3011. //                                              =       EDID_HA + EDID_HBL
  3012. //      VESA_HDISP                      =       VESA_ACTIVE     =       EDID_HA
  3013. //      VESA_HSYNC_START        =       VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
  3014. //                                              =       EDID_HA + EDID_HSO
  3015. //      VESA_HSYNC_WIDTH        =       VESA_HSYNC_TIME =       EDID_HSPW
  3016. //      VESA_BORDER                     =       EDID_BORDER
  3017.  
  3018. /****************************************************************************/
  3019. // Structure used in SetCRTC_UsingDTDTimingTable
  3020. /****************************************************************************/
  3021. typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
  3022. {
  3023.         USHORT usH_Size;
  3024.         USHORT usH_Blanking_Time;
  3025.         USHORT usV_Size;
  3026.         USHORT usV_Blanking_Time;
  3027.         USHORT usH_SyncOffset;
  3028.         USHORT usH_SyncWidth;
  3029.         USHORT usV_SyncOffset;
  3030.         USHORT usV_SyncWidth;
  3031.         ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
  3032.   UCHAR   ucH_Border;         // From DFP EDID
  3033.         UCHAR ucV_Border;
  3034.   UCHAR   ucCRTC;             // ATOM_CRTC1 or ATOM_CRTC2  
  3035.         UCHAR ucPadding[3];
  3036. }SET_CRTC_USING_DTD_TIMING_PARAMETERS;
  3037.  
  3038. /****************************************************************************/
  3039. // Structure used in SetCRTC_TimingTable
  3040. /****************************************************************************/
  3041. typedef struct _SET_CRTC_TIMING_PARAMETERS
  3042. {
  3043.   USHORT                      usH_Total;        // horizontal total
  3044.   USHORT                      usH_Disp;         // horizontal display
  3045.   USHORT                      usH_SyncStart;    // horozontal Sync start
  3046.   USHORT                      usH_SyncWidth;    // horizontal Sync width
  3047.   USHORT                      usV_Total;        // vertical total
  3048.   USHORT                      usV_Disp;         // vertical display
  3049.   USHORT                      usV_SyncStart;    // vertical Sync start
  3050.   USHORT                      usV_SyncWidth;    // vertical Sync width
  3051.         ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
  3052.   UCHAR                       ucCRTC;           // ATOM_CRTC1 or ATOM_CRTC2
  3053.   UCHAR                       ucOverscanRight;  // right
  3054.   UCHAR                       ucOverscanLeft;   // left
  3055.   UCHAR                       ucOverscanBottom; // bottom
  3056.   UCHAR                       ucOverscanTop;    // top
  3057.         UCHAR ucReserved;
  3058. }SET_CRTC_TIMING_PARAMETERS;
  3059. #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
  3060.  
  3061. /****************************************************************************/
  3062. // Structure used in StandardVESA_TimingTable
  3063. //                   AnalogTV_InfoTable
  3064. //                   ComponentVideoInfoTable
  3065. /****************************************************************************/
  3066. typedef struct _ATOM_MODE_TIMING
  3067. {
  3068.         USHORT usCRTC_H_Total;
  3069.         USHORT usCRTC_H_Disp;
  3070.         USHORT usCRTC_H_SyncStart;
  3071.         USHORT usCRTC_H_SyncWidth;
  3072.         USHORT usCRTC_V_Total;
  3073.         USHORT usCRTC_V_Disp;
  3074.         USHORT usCRTC_V_SyncStart;
  3075.         USHORT usCRTC_V_SyncWidth;
  3076.   USHORT  usPixelClock;                                                  //in 10Khz unit
  3077.         ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
  3078.         USHORT usCRTC_OverscanRight;
  3079.         USHORT usCRTC_OverscanLeft;
  3080.         USHORT usCRTC_OverscanBottom;
  3081.         USHORT usCRTC_OverscanTop;
  3082.         USHORT usReserve;
  3083.         UCHAR ucInternalModeNumber;
  3084.         UCHAR ucRefreshRate;
  3085. }ATOM_MODE_TIMING;
  3086.  
  3087. typedef struct _ATOM_DTD_FORMAT
  3088. {
  3089.         USHORT usPixClk;
  3090.         USHORT usHActive;
  3091.         USHORT usHBlanking_Time;
  3092.         USHORT usVActive;
  3093.         USHORT usVBlanking_Time;
  3094.         USHORT usHSyncOffset;
  3095.         USHORT usHSyncWidth;
  3096.         USHORT usVSyncOffset;
  3097.         USHORT usVSyncWidth;
  3098.         USHORT usImageHSize;
  3099.         USHORT usImageVSize;
  3100.         UCHAR ucHBorder;
  3101.         UCHAR ucVBorder;
  3102.         ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
  3103.         UCHAR ucInternalModeNumber;
  3104.         UCHAR ucRefreshRate;
  3105. }ATOM_DTD_FORMAT;
  3106.  
  3107. /****************************************************************************/
  3108. // Structure used in LVDS_InfoTable
  3109. //  * Need a document to describe this table
  3110. /****************************************************************************/
  3111. #define SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
  3112. #define SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
  3113. #define SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
  3114. #define SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
  3115.  
  3116. //ucTableFormatRevision=1
  3117. //ucTableContentRevision=1
  3118. typedef struct _ATOM_LVDS_INFO
  3119. {
  3120.         ATOM_COMMON_TABLE_HEADER sHeader;
  3121.         ATOM_DTD_FORMAT sLCDTiming;
  3122.         USHORT usModePatchTableOffset;
  3123.   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
  3124.         USHORT usOffDelayInMs;
  3125.         UCHAR ucPowerSequenceDigOntoDEin10Ms;
  3126.         UCHAR ucPowerSequenceDEtoBLOnin10Ms;
  3127.   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
  3128.                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
  3129.                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
  3130.                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
  3131.         UCHAR ucPanelDefaultRefreshRate;
  3132.         UCHAR ucPanelIdentification;
  3133.         UCHAR ucSS_Id;
  3134. }ATOM_LVDS_INFO;
  3135.  
  3136. //ucTableFormatRevision=1
  3137. //ucTableContentRevision=2
  3138. typedef struct _ATOM_LVDS_INFO_V12
  3139. {
  3140.         ATOM_COMMON_TABLE_HEADER sHeader;
  3141.         ATOM_DTD_FORMAT sLCDTiming;
  3142.         USHORT usExtInfoTableOffset;
  3143.   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
  3144.         USHORT usOffDelayInMs;
  3145.         UCHAR ucPowerSequenceDigOntoDEin10Ms;
  3146.         UCHAR ucPowerSequenceDEtoBLOnin10Ms;
  3147.   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
  3148.                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
  3149.                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
  3150.                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
  3151.         UCHAR ucPanelDefaultRefreshRate;
  3152.         UCHAR ucPanelIdentification;
  3153.         UCHAR ucSS_Id;
  3154.         USHORT usLCDVenderID;
  3155.         USHORT usLCDProductID;
  3156.         UCHAR ucLCDPanel_SpecialHandlingCap;
  3157.         UCHAR                                                           ucPanelInfoSize;                                        //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
  3158.         UCHAR ucReserved[2];
  3159. }ATOM_LVDS_INFO_V12;
  3160.  
  3161. //Definitions for ucLCDPanel_SpecialHandlingCap:
  3162.  
  3163. //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
  3164. //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
  3165. #define LCDPANEL_CAP_READ_EDID                  0x1
  3166.  
  3167. //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
  3168. //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
  3169. //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
  3170. #define LCDPANEL_CAP_DRR_SUPPORTED              0x2
  3171.  
  3172. //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
  3173. #define LCDPANEL_CAP_eDP                        0x4
  3174.  
  3175.  
  3176. //Color Bit Depth definition in EDID V1.4 @BYTE 14h
  3177. //Bit 6  5  4
  3178.                               //      0  0  0  -  Color bit depth is undefined
  3179.                               //      0  0  1  -  6 Bits per Primary Color
  3180.                               //      0  1  0  -  8 Bits per Primary Color
  3181.                               //      0  1  1  - 10 Bits per Primary Color
  3182.                               //      1  0  0  - 12 Bits per Primary Color
  3183.                               //      1  0  1  - 14 Bits per Primary Color
  3184.                               //      1  1  0  - 16 Bits per Primary Color
  3185.                               //      1  1  1  - Reserved
  3186.  
  3187. #define PANEL_COLOR_BIT_DEPTH_MASK    0x70
  3188.  
  3189. // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}  
  3190. #define PANEL_RANDOM_DITHER   0x80
  3191. #define PANEL_RANDOM_DITHER_MASK   0x80
  3192.  
  3193. #define ATOM_LVDS_INFO_LAST  ATOM_LVDS_INFO_V12   // no need to change this
  3194.  
  3195. /****************************************************************************/ 
  3196. // Structures used by LCD_InfoTable V1.3    Note: previous version was called ATOM_LVDS_INFO_V12
  3197. // ASIC Families:  NI
  3198. // ucTableFormatRevision=1
  3199. // ucTableContentRevision=3
  3200. /****************************************************************************/ 
  3201. typedef struct _ATOM_LCD_INFO_V13
  3202. {
  3203.   ATOM_COMMON_TABLE_HEADER sHeader;  
  3204.   ATOM_DTD_FORMAT     sLCDTiming;
  3205.   USHORT              usExtInfoTableOffset;
  3206.   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
  3207.   ULONG               ulReserved0;
  3208.   UCHAR               ucLCD_Misc;                // Reorganized in V13
  3209.                                                  // Bit0: {=0:single, =1:dual},
  3210.                                                  // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888}  // was {=0:666RGB, =1:888RGB},
  3211.                                                  // Bit3:2: {Grey level}
  3212.                                                  // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
  3213.                                                  // Bit7   Reserved.  was for ATOM_PANEL_MISC_API_ENABLED, still need it?  
  3214.   UCHAR               ucPanelDefaultRefreshRate;
  3215.   UCHAR               ucPanelIdentification;
  3216.   UCHAR               ucSS_Id;
  3217.   USHORT              usLCDVenderID;
  3218.   USHORT              usLCDProductID;
  3219.   UCHAR               ucLCDPanel_SpecialHandlingCap;  // Reorganized in V13
  3220.                                                  // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
  3221.                                                  // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
  3222.                                                  // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
  3223.                                                  // Bit7-3: Reserved
  3224.   UCHAR               ucPanelInfoSize;                                   //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
  3225.   USHORT              usBacklightPWM;            //  Backlight PWM in Hz. New in _V13
  3226.  
  3227.   UCHAR               ucPowerSequenceDIGONtoDE_in4Ms;
  3228.   UCHAR               ucPowerSequenceDEtoVARY_BL_in4Ms;
  3229.   UCHAR               ucPowerSequenceDEtoDIGON_in4Ms;
  3230.   UCHAR               ucPowerSequenceVARY_BLtoDE_in4Ms;
  3231.  
  3232.   UCHAR               ucOffDelay_in4Ms;
  3233.   UCHAR               ucPowerSequenceVARY_BLtoBLON_in4Ms;
  3234.   UCHAR               ucPowerSequenceBLONtoVARY_BL_in4Ms;
  3235.   UCHAR               ucReserved1;
  3236.  
  3237.   ULONG               ulReserved[4];
  3238. }ATOM_LCD_INFO_V13;  
  3239.  
  3240. #define ATOM_LCD_INFO_LAST  ATOM_LCD_INFO_V13    
  3241.  
  3242. //Definitions for ucLCD_Misc
  3243. #define ATOM_PANEL_MISC_V13_DUAL                   0x00000001
  3244. #define ATOM_PANEL_MISC_V13_FPDI                   0x00000002
  3245. #define ATOM_PANEL_MISC_V13_GREY_LEVEL             0x0000000C
  3246. #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT       2
  3247. #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK   0x70
  3248. #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR         0x10
  3249. #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR         0x20
  3250.  
  3251. //Color Bit Depth definition in EDID V1.4 @BYTE 14h
  3252. //Bit 6  5  4
  3253.                               //      0  0  0  -  Color bit depth is undefined
  3254.                               //      0  0  1  -  6 Bits per Primary Color
  3255.                               //      0  1  0  -  8 Bits per Primary Color
  3256.                               //      0  1  1  - 10 Bits per Primary Color
  3257.                               //      1  0  0  - 12 Bits per Primary Color
  3258.                               //      1  0  1  - 14 Bits per Primary Color
  3259.                               //      1  1  0  - 16 Bits per Primary Color
  3260.                               //      1  1  1  - Reserved
  3261.  
  3262. //Definitions for ucLCDPanel_SpecialHandlingCap:
  3263.  
  3264. //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
  3265. //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
  3266. #define LCDPANEL_CAP_V13_READ_EDID              0x1        // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
  3267.  
  3268. //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
  3269. //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
  3270. //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
  3271. #define LCDPANEL_CAP_V13_DRR_SUPPORTED          0x2        // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
  3272.  
  3273. //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
  3274. #define LCDPANEL_CAP_V13_eDP                    0x4        // = LCDPANEL_CAP_eDP no change comparing to previous version
  3275.  
  3276. typedef struct  _ATOM_PATCH_RECORD_MODE
  3277. {
  3278.         UCHAR ucRecordType;
  3279.         USHORT usHDisp;
  3280.         USHORT usVDisp;
  3281. }ATOM_PATCH_RECORD_MODE;
  3282.  
  3283. typedef struct  _ATOM_LCD_RTS_RECORD
  3284. {
  3285.         UCHAR ucRecordType;
  3286.         UCHAR ucRTSValue;
  3287. }ATOM_LCD_RTS_RECORD;
  3288.  
  3289. //!! If the record below exits, it shoud always be the first record for easy use in command table!!!
  3290. // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
  3291. typedef struct  _ATOM_LCD_MODE_CONTROL_CAP
  3292. {
  3293.         UCHAR ucRecordType;
  3294.         USHORT usLCDCap;
  3295. }ATOM_LCD_MODE_CONTROL_CAP;
  3296.  
  3297. #define LCD_MODE_CAP_BL_OFF                   1
  3298. #define LCD_MODE_CAP_CRTC_OFF                 2
  3299. #define LCD_MODE_CAP_PANEL_OFF                4
  3300.  
  3301. typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
  3302. {
  3303.         UCHAR ucRecordType;
  3304.         UCHAR ucFakeEDIDLength;
  3305.   UCHAR ucFakeEDIDString[1];    // This actually has ucFakeEdidLength elements.
  3306. } ATOM_FAKE_EDID_PATCH_RECORD;
  3307.  
  3308. typedef struct  _ATOM_PANEL_RESOLUTION_PATCH_RECORD
  3309. {
  3310.         UCHAR ucRecordType;
  3311.         USHORT usHSize;
  3312.         USHORT usVSize;
  3313. }ATOM_PANEL_RESOLUTION_PATCH_RECORD;
  3314.  
  3315. #define LCD_MODE_PATCH_RECORD_MODE_TYPE       1
  3316. #define LCD_RTS_RECORD_TYPE                   2
  3317. #define LCD_CAP_RECORD_TYPE                   3
  3318. #define LCD_FAKE_EDID_PATCH_RECORD_TYPE       4
  3319. #define LCD_PANEL_RESOLUTION_RECORD_TYPE      5
  3320. #define ATOM_RECORD_END_TYPE                  0xFF
  3321.  
  3322. /****************************Spread Spectrum Info Table Definitions **********************/
  3323.  
  3324. //ucTableFormatRevision=1
  3325. //ucTableContentRevision=2
  3326. typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
  3327. {
  3328.         USHORT usSpreadSpectrumPercentage;
  3329.   UCHAR               ucSpreadSpectrumType;         //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS  Others:TBD
  3330.         UCHAR ucSS_Step;
  3331.         UCHAR ucSS_Delay;
  3332.         UCHAR ucSS_Id;
  3333.         UCHAR ucRecommendedRef_Div;
  3334.   UCHAR               ucSS_Range;               //it was reserved for V11
  3335. }ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
  3336.  
  3337. #define ATOM_MAX_SS_ENTRY                      16
  3338. #define ATOM_DP_SS_ID1                                                                                           0x0f1                  // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
  3339. #define ATOM_DP_SS_ID2                                                                                           0x0f2                  // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
  3340. #define ATOM_LVLINK_2700MHz_SS_ID              0x0f3      // SS ID for LV link translator chip at 2.7Ghz
  3341. #define ATOM_LVLINK_1620MHz_SS_ID              0x0f4      // SS ID for LV link translator chip at 1.62Ghz
  3342.  
  3343.  
  3344. #define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
  3345. #define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
  3346. #define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
  3347. #define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
  3348. #define ATOM_INTERNAL_SS_MASK                  0x00000000
  3349. #define ATOM_EXTERNAL_SS_MASK                  0x00000002
  3350. #define EXEC_SS_STEP_SIZE_SHIFT                2
  3351. #define EXEC_SS_DELAY_SHIFT                    4
  3352. #define ACTIVEDATA_TO_BLON_DELAY_SHIFT         4
  3353.  
  3354. typedef struct _ATOM_SPREAD_SPECTRUM_INFO
  3355. {
  3356.         ATOM_COMMON_TABLE_HEADER sHeader;
  3357.         ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY];
  3358. }ATOM_SPREAD_SPECTRUM_INFO;
  3359.  
  3360. /****************************************************************************/
  3361. // Structure used in AnalogTV_InfoTable (Top level)
  3362. /****************************************************************************/
  3363. //ucTVBootUpDefaultStd definition:
  3364.  
  3365. //ATOM_TV_NTSC                1
  3366. //ATOM_TV_NTSCJ               2
  3367. //ATOM_TV_PAL                 3
  3368. //ATOM_TV_PALM                4
  3369. //ATOM_TV_PALCN               5
  3370. //ATOM_TV_PALN                6
  3371. //ATOM_TV_PAL60               7
  3372. //ATOM_TV_SECAM               8
  3373.  
  3374. //ucTVSupportedStd definition:
  3375. #define NTSC_SUPPORT          0x1
  3376. #define NTSCJ_SUPPORT         0x2
  3377.  
  3378. #define PAL_SUPPORT           0x4
  3379. #define PALM_SUPPORT          0x8
  3380. #define PALCN_SUPPORT         0x10
  3381. #define PALN_SUPPORT          0x20
  3382. #define PAL60_SUPPORT         0x40
  3383. #define SECAM_SUPPORT         0x80
  3384.  
  3385. #define MAX_SUPPORTED_TV_TIMING    2
  3386.  
  3387. typedef struct _ATOM_ANALOG_TV_INFO
  3388. {
  3389.         ATOM_COMMON_TABLE_HEADER sHeader;
  3390.         UCHAR ucTV_SupportedStandard;
  3391.         UCHAR ucTV_BootUpDefaultStandard;
  3392.         UCHAR ucExt_TV_ASIC_ID;
  3393.         UCHAR ucExt_TV_ASIC_SlaveAddr;
  3394.   /*ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING];*/
  3395.         ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING];
  3396. }ATOM_ANALOG_TV_INFO;
  3397.  
  3398. #define MAX_SUPPORTED_TV_TIMING_V1_2    3
  3399.  
  3400. typedef struct _ATOM_ANALOG_TV_INFO_V1_2
  3401. {
  3402.         ATOM_COMMON_TABLE_HEADER sHeader;
  3403.         UCHAR                    ucTV_SupportedStandard;
  3404.         UCHAR                    ucTV_BootUpDefaultStandard;
  3405.         UCHAR                    ucExt_TV_ASIC_ID;
  3406.         UCHAR                    ucExt_TV_ASIC_SlaveAddr;
  3407.   ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2];
  3408. }ATOM_ANALOG_TV_INFO_V1_2;
  3409.  
  3410. typedef struct _ATOM_DPCD_INFO
  3411. {
  3412.   UCHAR   ucRevisionNumber;        //10h : Revision 1.0; 11h : Revision 1.1  
  3413.   UCHAR   ucMaxLinkRate;           //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
  3414.   UCHAR   ucMaxLane;               //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
  3415.   UCHAR   ucMaxDownSpread;         //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
  3416. }ATOM_DPCD_INFO;
  3417.  
  3418. #define ATOM_DPCD_MAX_LANE_MASK    0x1F
  3419.  
  3420. /**************************************************************************/
  3421. // VRAM usage and their defintions
  3422.  
  3423. // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
  3424. // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
  3425. // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
  3426. // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
  3427. // To Bios:  ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
  3428.  
  3429. #ifndef VESA_MEMORY_IN_64K_BLOCK
  3430. #define VESA_MEMORY_IN_64K_BLOCK        0x100       //256*64K=16Mb (Max. VESA memory is 16Mb!)
  3431. #endif
  3432.  
  3433. #define ATOM_EDID_RAW_DATASIZE          256         //In Bytes
  3434. #define ATOM_HWICON_SURFACE_SIZE        4096        //In Bytes
  3435. #define ATOM_HWICON_INFOTABLE_SIZE      32
  3436. #define MAX_DTD_MODE_IN_VRAM            6
  3437. #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE  (MAX_DTD_MODE_IN_VRAM*28)    //28= (SIZEOF ATOM_DTD_FORMAT)
  3438. #define ATOM_STD_MODE_SUPPORT_TBL_SIZE  32*8                         //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
  3439. //20 bytes for Encoder Type and DPCD in STD EDID area
  3440. #define DFP_ENCODER_TYPE_OFFSET         (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)    
  3441. #define ATOM_DP_DPCD_OFFSET             (DFP_ENCODER_TYPE_OFFSET + 4 )        
  3442.  
  3443. #define ATOM_HWICON1_SURFACE_ADDR       0
  3444. #define ATOM_HWICON2_SURFACE_ADDR       (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
  3445. #define ATOM_HWICON_INFOTABLE_ADDR      (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
  3446. #define ATOM_CRT1_EDID_ADDR             (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
  3447. #define ATOM_CRT1_DTD_MODE_TBL_ADDR     (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  3448. #define ATOM_CRT1_STD_MODE_TBL_ADDR         (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3449.  
  3450. #define ATOM_LCD1_EDID_ADDR             (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  3451. #define ATOM_LCD1_DTD_MODE_TBL_ADDR     (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  3452. #define ATOM_LCD1_STD_MODE_TBL_ADDR     (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3453.  
  3454. #define ATOM_TV1_DTD_MODE_TBL_ADDR      (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  3455.  
  3456. #define ATOM_DFP1_EDID_ADDR             (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3457. #define ATOM_DFP1_DTD_MODE_TBL_ADDR     (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  3458. #define ATOM_DFP1_STD_MODE_TBL_ADDR         (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3459.  
  3460. #define ATOM_CRT2_EDID_ADDR             (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  3461. #define ATOM_CRT2_DTD_MODE_TBL_ADDR     (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  3462. #define ATOM_CRT2_STD_MODE_TBL_ADDR         (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3463.  
  3464. #define ATOM_LCD2_EDID_ADDR             (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  3465. #define ATOM_LCD2_DTD_MODE_TBL_ADDR     (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  3466. #define ATOM_LCD2_STD_MODE_TBL_ADDR     (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3467.  
  3468. #define ATOM_DFP6_EDID_ADDR             (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  3469. #define ATOM_DFP6_DTD_MODE_TBL_ADDR     (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  3470. #define ATOM_DFP6_STD_MODE_TBL_ADDR     (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3471.  
  3472. #define ATOM_DFP2_EDID_ADDR             (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  3473. #define ATOM_DFP2_DTD_MODE_TBL_ADDR     (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  3474. #define ATOM_DFP2_STD_MODE_TBL_ADDR     (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3475.  
  3476. #define ATOM_CV_EDID_ADDR               (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  3477. #define ATOM_CV_DTD_MODE_TBL_ADDR       (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  3478. #define ATOM_CV_STD_MODE_TBL_ADDR       (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3479.  
  3480. #define ATOM_DFP3_EDID_ADDR             (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  3481. #define ATOM_DFP3_DTD_MODE_TBL_ADDR     (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  3482. #define ATOM_DFP3_STD_MODE_TBL_ADDR     (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3483.  
  3484. #define ATOM_DFP4_EDID_ADDR             (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  3485. #define ATOM_DFP4_DTD_MODE_TBL_ADDR     (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  3486. #define ATOM_DFP4_STD_MODE_TBL_ADDR     (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3487.  
  3488. #define ATOM_DFP5_EDID_ADDR             (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  3489. #define ATOM_DFP5_DTD_MODE_TBL_ADDR     (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
  3490. #define ATOM_DFP5_STD_MODE_TBL_ADDR     (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
  3491.  
  3492. #define ATOM_DP_TRAINING_TBL_ADDR       (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
  3493.  
  3494. #define ATOM_STACK_STORAGE_START        (ATOM_DP_TRAINING_TBL_ADDR + 1024)      
  3495. #define ATOM_STACK_STORAGE_END          ATOM_STACK_STORAGE_START + 512        
  3496.  
  3497. //The size below is in Kb!
  3498. #define ATOM_VRAM_RESERVE_SIZE         ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
  3499.  
  3500. #define ATOM_VRAM_RESERVE_V2_SIZE      32
  3501.  
  3502. #define ATOM_VRAM_OPERATION_FLAGS_MASK         0xC0000000L
  3503. #define ATOM_VRAM_OPERATION_FLAGS_SHIFT        30
  3504. #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION   0x1
  3505. #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION      0x0
  3506.  
  3507. /***********************************************************************************/
  3508. // Structure used in VRAM_UsageByFirmwareTable
  3509. // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
  3510. //        at running time.  
  3511. // note2: From RV770, the memory is more than 32bit addressable, so we will change
  3512. //        ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
  3513. //        exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
  3514. //        (in offset to start of memory address) is KB aligned instead of byte aligend.
  3515. /***********************************************************************************/
  3516. // Note3:
  3517. /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter,
  3518. for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can  have:
  3519.  
  3520. If (ulStartAddrUsedByFirmware!=0)
  3521. FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
  3522. Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
  3523. else    //Non VGA case
  3524.  if (FB_Size<=2Gb)
  3525.     FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
  3526.  else
  3527.           FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
  3528.  
  3529. CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
  3530.  
  3531. #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO                       1
  3532.  
  3533. typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
  3534. {
  3535.         ULONG ulStartAddrUsedByFirmware;
  3536.         USHORT usFirmwareUseInKb;
  3537.         USHORT usReserved;
  3538. }ATOM_FIRMWARE_VRAM_RESERVE_INFO;
  3539.  
  3540. typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
  3541. {
  3542.   ATOM_COMMON_TABLE_HEADER sHeader;  
  3543.   ATOM_FIRMWARE_VRAM_RESERVE_INFO       asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
  3544. }ATOM_VRAM_USAGE_BY_FIRMWARE;
  3545.  
  3546. // change verion to 1.5, when allow driver to allocate the vram area for command table access.
  3547. typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
  3548. {
  3549.   ULONG   ulStartAddrUsedByFirmware;
  3550.   USHORT  usFirmwareUseInKb;
  3551.   USHORT  usFBUsedByDrvInKb;
  3552. }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
  3553.  
  3554. typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
  3555. {
  3556.         ATOM_COMMON_TABLE_HEADER sHeader;
  3557.   ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5  asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
  3558. }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
  3559.  
  3560. /****************************************************************************/
  3561. // Structure used in GPIO_Pin_LUTTable
  3562. /****************************************************************************/
  3563. typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
  3564. {
  3565.         USHORT usGpioPin_AIndex;
  3566.         UCHAR ucGpioPinBitShift;
  3567.         UCHAR ucGPIO_ID;
  3568. }ATOM_GPIO_PIN_ASSIGNMENT;
  3569.  
  3570. typedef struct _ATOM_GPIO_PIN_LUT
  3571. {
  3572.         ATOM_COMMON_TABLE_HEADER sHeader;
  3573.         ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1];
  3574. }ATOM_GPIO_PIN_LUT;
  3575.  
  3576. /****************************************************************************/
  3577. // Structure used in ComponentVideoInfoTable   
  3578. /****************************************************************************/
  3579. #define GPIO_PIN_ACTIVE_HIGH          0x1
  3580.  
  3581. #define MAX_SUPPORTED_CV_STANDARDS    5
  3582.  
  3583. // definitions for ATOM_D_INFO.ucSettings
  3584. #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK  0x1F    // [4:0]
  3585. #define ATOM_GPIO_SETTINGS_RESERVED_MASK  0x60    // [6:5] = must be zeroed out
  3586. #define ATOM_GPIO_SETTINGS_ACTIVE_MASK    0x80    // [7]
  3587.  
  3588. typedef struct _ATOM_GPIO_INFO
  3589. {
  3590.         USHORT usAOffset;
  3591.         UCHAR ucSettings;
  3592.         UCHAR ucReserved;
  3593. }ATOM_GPIO_INFO;
  3594.  
  3595. // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
  3596. #define ATOM_CV_RESTRICT_FORMAT_SELECTION           0x2
  3597.  
  3598. // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
  3599. #define ATOM_GPIO_DEFAULT_MODE_EN                   0x80 //[7];
  3600. #define ATOM_GPIO_SETTING_PERMODE_MASK              0x7F //[6:0]
  3601.  
  3602. // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
  3603. //Line 3 out put 5V.
  3604. #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A       0x01     //represent gpio 3 state for 16:9
  3605. #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B       0x02     //represent gpio 4 state for 16:9
  3606. #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT   0x0
  3607.  
  3608. //Line 3 out put 2.2V              
  3609. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04     //represent gpio 3 state for 4:3 Letter box
  3610. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08     //represent gpio 4 state for 4:3 Letter box
  3611. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
  3612.  
  3613. //Line 3 out put 0V
  3614. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A        0x10     //represent gpio 3 state for 4:3
  3615. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B        0x20     //represent gpio 4 state for 4:3
  3616. #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT    0x4
  3617.  
  3618. #define ATOM_CV_LINE3_ASPECTRATIO_MASK              0x3F     // bit [5:0]
  3619.  
  3620. #define ATOM_CV_LINE3_ASPECTRATIO_EXIST             0x80     //bit 7
  3621.  
  3622. //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
  3623. #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A   3   //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
  3624. #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B   4   //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
  3625.  
  3626.  
  3627. typedef struct _ATOM_COMPONENT_VIDEO_INFO
  3628. {
  3629.         ATOM_COMMON_TABLE_HEADER sHeader;
  3630.         USHORT usMask_PinRegisterIndex;
  3631.         USHORT usEN_PinRegisterIndex;
  3632.         USHORT usY_PinRegisterIndex;
  3633.         USHORT usA_PinRegisterIndex;
  3634.         UCHAR ucBitShift;
  3635.   UCHAR              ucPinActiveState;  //ucPinActiveState: Bit0=1 active high, =0 active low
  3636.   ATOM_DTD_FORMAT    sReserved;         // must be zeroed out
  3637.         UCHAR ucMiscInfo;
  3638.         UCHAR uc480i;
  3639.         UCHAR uc480p;
  3640.         UCHAR uc720p;
  3641.         UCHAR uc1080i;
  3642.         UCHAR ucLetterBoxMode;
  3643.         UCHAR ucReserved[3];
  3644.   UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
  3645.         ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
  3646.         ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
  3647. }ATOM_COMPONENT_VIDEO_INFO;
  3648.  
  3649. //ucTableFormatRevision=2
  3650. //ucTableContentRevision=1
  3651. typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
  3652. {
  3653.         ATOM_COMMON_TABLE_HEADER sHeader;
  3654.         UCHAR ucMiscInfo;
  3655.         UCHAR uc480i;
  3656.         UCHAR uc480p;
  3657.         UCHAR uc720p;
  3658.         UCHAR uc1080i;
  3659.         UCHAR ucReserved;
  3660.         UCHAR ucLetterBoxMode;
  3661.   UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
  3662.         ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
  3663.         ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
  3664. }ATOM_COMPONENT_VIDEO_INFO_V21;
  3665.  
  3666. #define ATOM_COMPONENT_VIDEO_INFO_LAST  ATOM_COMPONENT_VIDEO_INFO_V21
  3667.  
  3668. /****************************************************************************/
  3669. // Structure used in object_InfoTable
  3670. /****************************************************************************/
  3671. typedef struct _ATOM_OBJECT_HEADER
  3672. {
  3673.         ATOM_COMMON_TABLE_HEADER sHeader;
  3674.         USHORT usDeviceSupport;
  3675.         USHORT usConnectorObjectTableOffset;
  3676.         USHORT usRouterObjectTableOffset;
  3677.         USHORT usEncoderObjectTableOffset;
  3678.   USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
  3679.         USHORT usDisplayPathTableOffset;
  3680. }ATOM_OBJECT_HEADER;
  3681.  
  3682. typedef struct _ATOM_OBJECT_HEADER_V3
  3683. {
  3684.   ATOM_COMMON_TABLE_HEADER      sHeader;
  3685.   USHORT                    usDeviceSupport;
  3686.   USHORT                    usConnectorObjectTableOffset;
  3687.   USHORT                    usRouterObjectTableOffset;
  3688.   USHORT                    usEncoderObjectTableOffset;
  3689.   USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
  3690.   USHORT                    usDisplayPathTableOffset;
  3691.   USHORT                    usMiscObjectTableOffset;
  3692. }ATOM_OBJECT_HEADER_V3;
  3693.  
  3694. typedef struct  _ATOM_DISPLAY_OBJECT_PATH
  3695. {
  3696.   USHORT    usDeviceTag;                                   //supported device
  3697.   USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
  3698.   USHORT    usConnObjectId;                                //Connector Object ID
  3699.   USHORT    usGPUObjectId;                                 //GPU ID
  3700.   USHORT    usGraphicObjIds[1];                             //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
  3701. }ATOM_DISPLAY_OBJECT_PATH;
  3702.  
  3703. typedef struct  _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
  3704. {
  3705.   USHORT    usDeviceTag;                                   //supported device
  3706.   USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
  3707.   USHORT    usConnObjectId;                                //Connector Object ID
  3708.   USHORT    usGPUObjectId;                                 //GPU ID
  3709.   USHORT    usGraphicObjIds[2];                            //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
  3710. }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;
  3711.  
  3712. typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
  3713. {
  3714.         UCHAR ucNumOfDispPath;
  3715.         UCHAR ucVersion;
  3716.         UCHAR ucPadding[2];
  3717.         ATOM_DISPLAY_OBJECT_PATH asDispPath[1];
  3718. }ATOM_DISPLAY_OBJECT_PATH_TABLE;
  3719.  
  3720.  
  3721. typedef struct _ATOM_OBJECT                                //each object has this structure    
  3722. {
  3723.         USHORT usObjectID;
  3724.         USHORT usSrcDstTableOffset;
  3725.   USHORT              usRecordOffset;                     //this pointing to a bunch of records defined below
  3726.         USHORT usReserved;
  3727. }ATOM_OBJECT;
  3728.  
  3729. typedef struct _ATOM_OBJECT_TABLE                         //Above 4 object table offset pointing to a bunch of objects all have this structure    
  3730. {
  3731.         UCHAR ucNumberOfObjects;
  3732.         UCHAR ucPadding[3];
  3733.         ATOM_OBJECT asObjects[1];
  3734. }ATOM_OBJECT_TABLE;
  3735.  
  3736. typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT         //usSrcDstTableOffset pointing to this structure
  3737. {
  3738.         UCHAR ucNumberOfSrc;
  3739.         USHORT usSrcObjectID[1];
  3740.         UCHAR ucNumberOfDst;
  3741.         USHORT usDstObjectID[1];
  3742. }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
  3743.  
  3744.  
  3745. //Two definitions below are for OPM on MXM module designs
  3746.  
  3747. #define EXT_HPDPIN_LUTINDEX_0                   0
  3748. #define EXT_HPDPIN_LUTINDEX_1                   1
  3749. #define EXT_HPDPIN_LUTINDEX_2                   2
  3750. #define EXT_HPDPIN_LUTINDEX_3                   3
  3751. #define EXT_HPDPIN_LUTINDEX_4                   4
  3752. #define EXT_HPDPIN_LUTINDEX_5                   5
  3753. #define EXT_HPDPIN_LUTINDEX_6                   6
  3754. #define EXT_HPDPIN_LUTINDEX_7                   7
  3755. #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES   (EXT_HPDPIN_LUTINDEX_7+1)
  3756.  
  3757. #define EXT_AUXDDC_LUTINDEX_0                   0
  3758. #define EXT_AUXDDC_LUTINDEX_1                   1
  3759. #define EXT_AUXDDC_LUTINDEX_2                   2
  3760. #define EXT_AUXDDC_LUTINDEX_3                   3
  3761. #define EXT_AUXDDC_LUTINDEX_4                   4
  3762. #define EXT_AUXDDC_LUTINDEX_5                   5
  3763. #define EXT_AUXDDC_LUTINDEX_6                   6
  3764. #define EXT_AUXDDC_LUTINDEX_7                   7
  3765. #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES   (EXT_AUXDDC_LUTINDEX_7+1)
  3766.  
  3767. //ucChannelMapping are defined as following
  3768. //for DP connector, eDP, DP to VGA/LVDS
  3769. //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
  3770. //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
  3771. //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
  3772. //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
  3773. typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING
  3774. {
  3775. #if ATOM_BIG_ENDIAN
  3776.   UCHAR ucDP_Lane3_Source:2;
  3777.   UCHAR ucDP_Lane2_Source:2;
  3778.   UCHAR ucDP_Lane1_Source:2;
  3779.   UCHAR ucDP_Lane0_Source:2;
  3780. #else
  3781.   UCHAR ucDP_Lane0_Source:2;
  3782.   UCHAR ucDP_Lane1_Source:2;
  3783.   UCHAR ucDP_Lane2_Source:2;
  3784.   UCHAR ucDP_Lane3_Source:2;
  3785. #endif
  3786. }ATOM_DP_CONN_CHANNEL_MAPPING;
  3787.  
  3788. //for DVI/HDMI, in dual link case, both links have to have same mapping.
  3789. //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
  3790. //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
  3791. //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
  3792. //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
  3793. typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING
  3794. {
  3795. #if ATOM_BIG_ENDIAN
  3796.   UCHAR ucDVI_CLK_Source:2;
  3797.   UCHAR ucDVI_DATA0_Source:2;
  3798.   UCHAR ucDVI_DATA1_Source:2;
  3799.   UCHAR ucDVI_DATA2_Source:2;
  3800. #else
  3801.   UCHAR ucDVI_DATA2_Source:2;
  3802.   UCHAR ucDVI_DATA1_Source:2;
  3803.   UCHAR ucDVI_DATA0_Source:2;
  3804.   UCHAR ucDVI_CLK_Source:2;
  3805. #endif
  3806. }ATOM_DVI_CONN_CHANNEL_MAPPING;
  3807.  
  3808. typedef struct _EXT_DISPLAY_PATH
  3809. {
  3810.   USHORT  usDeviceTag;                    //A bit vector to show what devices are supported
  3811.   USHORT  usDeviceACPIEnum;               //16bit device ACPI id.
  3812.   USHORT  usDeviceConnector;              //A physical connector for displays to plug in, using object connector definitions
  3813.   UCHAR   ucExtAUXDDCLutIndex;            //An index into external AUX/DDC channel LUT
  3814.   UCHAR   ucExtHPDPINLutIndex;            //An index into external HPD pin LUT
  3815.   USHORT  usExtEncoderObjId;              //external encoder object id
  3816.   union{
  3817.     UCHAR   ucChannelMapping;                  // if ucChannelMapping=0, using default one to one mapping
  3818.     ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
  3819.     ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
  3820.   };
  3821.   UCHAR   ucReserved;
  3822.   USHORT  usReserved[2];
  3823. }EXT_DISPLAY_PATH;
  3824.    
  3825. #define NUMBER_OF_UCHAR_FOR_GUID          16
  3826. #define MAX_NUMBER_OF_EXT_DISPLAY_PATH    7
  3827.  
  3828. typedef  struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
  3829. {
  3830.   ATOM_COMMON_TABLE_HEADER sHeader;
  3831.   UCHAR                    ucGuid [NUMBER_OF_UCHAR_FOR_GUID];     // a GUID is a 16 byte long string
  3832.   EXT_DISPLAY_PATH         sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
  3833.   UCHAR                    ucChecksum;                            // a  simple Checksum of the sum of whole structure equal to 0x0.
  3834.   UCHAR                    uc3DStereoPinId;                       // use for eDP panel
  3835.   UCHAR                    Reserved [6];                          // for potential expansion
  3836. }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
  3837.  
  3838. //Related definitions, all records are different but they have a commond header
  3839. typedef struct _ATOM_COMMON_RECORD_HEADER
  3840. {
  3841.   UCHAR               ucRecordType;                      //An emun to indicate the record type
  3842.   UCHAR               ucRecordSize;                      //The size of the whole record in byte
  3843. }ATOM_COMMON_RECORD_HEADER;
  3844.  
  3845.  
  3846. #define ATOM_I2C_RECORD_TYPE                           1
  3847. #define ATOM_HPD_INT_RECORD_TYPE                       2
  3848. #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE             3
  3849. #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE          4
  3850. #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE             5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
  3851. #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE          6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
  3852. #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE      7
  3853. #define ATOM_JTAG_RECORD_TYPE                          8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
  3854. #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE              9
  3855. #define ATOM_ENCODER_DVO_CF_RECORD_TYPE               10
  3856. #define ATOM_CONNECTOR_CF_RECORD_TYPE                 11
  3857. #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE       12
  3858. #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE  13
  3859. #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE                         14
  3860. #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE                                  15
  3861. #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE          16 //This is for the case when connectors are not known to object table
  3862. #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE          17 //This is for the case when connectors are not known to object table
  3863. #define ATOM_OBJECT_LINK_RECORD_TYPE                   18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
  3864. #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE          19
  3865. #define ATOM_ENCODER_CAP_RECORD_TYPE                   20
  3866.  
  3867.  
  3868. //Must be updated when new record type is added,equal to that record definition!
  3869. #define ATOM_MAX_OBJECT_RECORD_NUMBER             ATOM_ENCODER_CAP_RECORD_TYPE
  3870.  
  3871. typedef struct  _ATOM_I2C_RECORD
  3872. {
  3873.         ATOM_COMMON_RECORD_HEADER sheader;
  3874.         ATOM_I2C_ID_CONFIG sucI2cId;
  3875.   UCHAR                       ucI2CAddr;              //The slave address, it's 0 when the record is attached to connector for DDC
  3876. }ATOM_I2C_RECORD;
  3877.  
  3878. typedef struct  _ATOM_HPD_INT_RECORD
  3879. {
  3880.         ATOM_COMMON_RECORD_HEADER sheader;
  3881.   UCHAR                       ucHPDIntGPIOID;         //Corresponding block in GPIO_PIN_INFO table gives the pin info          
  3882.         UCHAR ucPlugged_PinState;
  3883. }ATOM_HPD_INT_RECORD;
  3884.  
  3885.  
  3886. typedef struct  _ATOM_OUTPUT_PROTECTION_RECORD
  3887. {
  3888.         ATOM_COMMON_RECORD_HEADER sheader;
  3889.         UCHAR ucProtectionFlag;
  3890.         UCHAR ucReserved;
  3891. }ATOM_OUTPUT_PROTECTION_RECORD;
  3892.  
  3893. typedef struct  _ATOM_CONNECTOR_DEVICE_TAG
  3894. {
  3895.   ULONG                       ulACPIDeviceEnum;       //Reserved for now
  3896.   USHORT                      usDeviceID;             //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
  3897.         USHORT usPadding;
  3898. }ATOM_CONNECTOR_DEVICE_TAG;
  3899.  
  3900. typedef struct  _ATOM_CONNECTOR_DEVICE_TAG_RECORD
  3901. {
  3902.         ATOM_COMMON_RECORD_HEADER sheader;
  3903.         UCHAR ucNumberOfDevice;
  3904.         UCHAR ucReserved;
  3905.   ATOM_CONNECTOR_DEVICE_TAG   asDeviceTag[1];         //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
  3906. }ATOM_CONNECTOR_DEVICE_TAG_RECORD;
  3907.  
  3908.  
  3909. typedef struct  _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
  3910. {
  3911.         ATOM_COMMON_RECORD_HEADER sheader;
  3912.         UCHAR ucConfigGPIOID;
  3913.   UCHAR                                                     ucConfigGPIOState;      //Set to 1 when it's active high to enable external flow in
  3914.         UCHAR ucFlowinGPIPID;
  3915.         UCHAR ucExtInGPIPID;
  3916. }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
  3917.  
  3918. typedef struct  _ATOM_ENCODER_FPGA_CONTROL_RECORD
  3919. {
  3920.         ATOM_COMMON_RECORD_HEADER sheader;
  3921.         UCHAR ucCTL1GPIO_ID;
  3922.   UCHAR                       ucCTL1GPIOState;        //Set to 1 when it's active high
  3923.         UCHAR ucCTL2GPIO_ID;
  3924.   UCHAR                       ucCTL2GPIOState;        //Set to 1 when it's active high
  3925.         UCHAR ucCTL3GPIO_ID;
  3926.   UCHAR                       ucCTL3GPIOState;        //Set to 1 when it's active high
  3927.         UCHAR ucCTLFPGA_IN_ID;
  3928.         UCHAR ucPadding[3];
  3929. }ATOM_ENCODER_FPGA_CONTROL_RECORD;
  3930.  
  3931. typedef struct  _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
  3932. {
  3933.         ATOM_COMMON_RECORD_HEADER sheader;
  3934.   UCHAR                       ucGPIOID;               //Corresponding block in GPIO_PIN_INFO table gives the pin info
  3935.   UCHAR                       ucTVActiveState;        //Indicating when the pin==0 or 1 when TV is connected
  3936. }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
  3937.  
  3938. typedef struct  _ATOM_JTAG_RECORD
  3939. {
  3940.         ATOM_COMMON_RECORD_HEADER sheader;
  3941.         UCHAR ucTMSGPIO_ID;
  3942.   UCHAR                       ucTMSGPIOState;         //Set to 1 when it's active high
  3943.         UCHAR ucTCKGPIO_ID;
  3944.   UCHAR                       ucTCKGPIOState;         //Set to 1 when it's active high
  3945.         UCHAR ucTDOGPIO_ID;
  3946.   UCHAR                       ucTDOGPIOState;         //Set to 1 when it's active high
  3947.         UCHAR ucTDIGPIO_ID;
  3948.   UCHAR                       ucTDIGPIOState;         //Set to 1 when it's active high
  3949.         UCHAR ucPadding[2];
  3950. }ATOM_JTAG_RECORD;
  3951.  
  3952.  
  3953. //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
  3954. typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
  3955. {
  3956.   UCHAR                       ucGPIOID;               // GPIO_ID, find the corresponding ID in GPIO_LUT table
  3957.   UCHAR                       ucGPIO_PinState;        // Pin state showing how to set-up the pin
  3958. }ATOM_GPIO_PIN_CONTROL_PAIR;
  3959.  
  3960. typedef struct  _ATOM_OBJECT_GPIO_CNTL_RECORD
  3961. {
  3962.         ATOM_COMMON_RECORD_HEADER sheader;
  3963.   UCHAR                       ucFlags;                // Future expnadibility
  3964.   UCHAR                       ucNumberOfPins;         // Number of GPIO pins used to control the object
  3965.   ATOM_GPIO_PIN_CONTROL_PAIR  asGpio[1];              // the real gpio pin pair determined by number of pins ucNumberOfPins
  3966. }ATOM_OBJECT_GPIO_CNTL_RECORD;
  3967.  
  3968. //Definitions for GPIO pin state
  3969. #define GPIO_PIN_TYPE_INPUT             0x00
  3970. #define GPIO_PIN_TYPE_OUTPUT            0x10
  3971. #define GPIO_PIN_TYPE_HW_CONTROL        0x20
  3972.  
  3973. //For GPIO_PIN_TYPE_OUTPUT the following is defined
  3974. #define GPIO_PIN_OUTPUT_STATE_MASK      0x01
  3975. #define GPIO_PIN_OUTPUT_STATE_SHIFT     0
  3976. #define GPIO_PIN_STATE_ACTIVE_LOW       0x0
  3977. #define GPIO_PIN_STATE_ACTIVE_HIGH      0x1
  3978.  
  3979. // Indexes to GPIO array in GLSync record
  3980. #define ATOM_GPIO_INDEX_GLSYNC_REFCLK    0
  3981. #define ATOM_GPIO_INDEX_GLSYNC_HSYNC     1
  3982. #define ATOM_GPIO_INDEX_GLSYNC_VSYNC     2
  3983. #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ  3
  3984. #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT  4
  3985. #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
  3986. #define ATOM_GPIO_INDEX_GLSYNC_V_RESET   6
  3987. #define ATOM_GPIO_INDEX_GLSYNC_MAX       7
  3988.  
  3989. typedef struct  _ATOM_ENCODER_DVO_CF_RECORD
  3990. {
  3991.         ATOM_COMMON_RECORD_HEADER sheader;
  3992.   ULONG                       ulStrengthControl;      // DVOA strength control for CF
  3993.         UCHAR ucPadding[2];
  3994. }ATOM_ENCODER_DVO_CF_RECORD;
  3995.  
  3996. // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap
  3997. #define ATOM_ENCODER_CAP_RECORD_HBR2     0x01         // DP1.2 HBR2 is supported by this path
  3998.  
  3999. typedef struct  _ATOM_ENCODER_CAP_RECORD
  4000. {
  4001.   ATOM_COMMON_RECORD_HEADER   sheader;
  4002.   union {
  4003.     USHORT                    usEncoderCap;        
  4004.     struct {
  4005. #if ATOM_BIG_ENDIAN
  4006.       USHORT                  usReserved:15;        // Bit1-15 may be defined for other capability in future
  4007.       USHORT                  usHBR2Cap:1;          // Bit0 is for DP1.2 HBR2 capability.
  4008. #else
  4009.       USHORT                  usHBR2Cap:1;          // Bit0 is for DP1.2 HBR2 capability.
  4010.       USHORT                  usReserved:15;        // Bit1-15 may be defined for other capability in future
  4011. #endif
  4012.     };
  4013.   };
  4014. }ATOM_ENCODER_CAP_RECORD;                            
  4015.  
  4016. // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
  4017. #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA   1
  4018. #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB   2
  4019.  
  4020. typedef struct  _ATOM_CONNECTOR_CF_RECORD
  4021. {
  4022.         ATOM_COMMON_RECORD_HEADER sheader;
  4023.         USHORT usMaxPixClk;
  4024.         UCHAR ucFlowCntlGpioId;
  4025.         UCHAR ucSwapCntlGpioId;
  4026.         UCHAR ucConnectedDvoBundle;
  4027.         UCHAR ucPadding;
  4028. }ATOM_CONNECTOR_CF_RECORD;
  4029.  
  4030. typedef struct  _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
  4031. {
  4032.         ATOM_COMMON_RECORD_HEADER sheader;
  4033.         ATOM_DTD_FORMAT asTiming;
  4034. }ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
  4035.  
  4036. typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
  4037. {
  4038.   ATOM_COMMON_RECORD_HEADER   sheader;                //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
  4039.   UCHAR                       ucSubConnectorType;     //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
  4040.         UCHAR ucReserved;
  4041. }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
  4042.  
  4043.  
  4044. typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
  4045. {
  4046.         ATOM_COMMON_RECORD_HEADER sheader;
  4047.         UCHAR                                                                                           ucMuxType;                                                      //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
  4048.         UCHAR ucMuxControlPin;
  4049.         UCHAR                                                                                           ucMuxState[2];                                  //for alligment purpose
  4050. }ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
  4051.  
  4052. typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
  4053. {
  4054.         ATOM_COMMON_RECORD_HEADER sheader;
  4055.         UCHAR ucMuxType;
  4056.         UCHAR ucMuxControlPin;
  4057.         UCHAR                                                                                           ucMuxState[2];                                  //for alligment purpose
  4058. }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
  4059.  
  4060. // define ucMuxType
  4061. #define ATOM_ROUTER_MUX_PIN_STATE_MASK                                                          0x0f
  4062. #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT             0x01
  4063.  
  4064. typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD     //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
  4065. {
  4066.   ATOM_COMMON_RECORD_HEADER   sheader;
  4067.   UCHAR                       ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES];  //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
  4068. }ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
  4069.  
  4070. typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD  //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
  4071. {
  4072.   ATOM_COMMON_RECORD_HEADER   sheader;
  4073.   ATOM_I2C_ID_CONFIG          ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES];  //An fixed size array which maps external pins to internal DDC ID
  4074. }ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
  4075.  
  4076. typedef struct _ATOM_OBJECT_LINK_RECORD
  4077. {
  4078.   ATOM_COMMON_RECORD_HEADER   sheader;
  4079.   USHORT                      usObjectID;         //could be connector, encorder or other object in object.h
  4080. }ATOM_OBJECT_LINK_RECORD;
  4081.  
  4082. typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
  4083. {
  4084.   ATOM_COMMON_RECORD_HEADER   sheader;
  4085.   USHORT                      usReserved;
  4086. }ATOM_CONNECTOR_REMOTE_CAP_RECORD;
  4087.  
  4088. /****************************************************************************/
  4089. // ASIC voltage data table
  4090. /****************************************************************************/
  4091. typedef struct  _ATOM_VOLTAGE_INFO_HEADER
  4092. {
  4093.    USHORT   usVDDCBaseLevel;                //In number of 50mv unit
  4094.    USHORT   usReserved;                     //For possible extension table offset
  4095.         UCHAR ucNumOfVoltageEntries;
  4096.         UCHAR ucBytesPerVoltageEntry;
  4097.    UCHAR    ucVoltageStep;                  //Indicating in how many mv increament is one step, 0.5mv unit
  4098.         UCHAR ucDefaultVoltageEntry;
  4099.         UCHAR ucVoltageControlI2cLine;
  4100.         UCHAR ucVoltageControlAddress;
  4101.         UCHAR ucVoltageControlOffset;
  4102. }ATOM_VOLTAGE_INFO_HEADER;
  4103.  
  4104. typedef struct  _ATOM_VOLTAGE_INFO
  4105. {
  4106.         ATOM_COMMON_TABLE_HEADER sHeader;
  4107.         ATOM_VOLTAGE_INFO_HEADER viHeader;
  4108.    UCHAR    ucVoltageEntries[64];            //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
  4109. }ATOM_VOLTAGE_INFO;
  4110.  
  4111.  
  4112. typedef struct  _ATOM_VOLTAGE_FORMULA
  4113. {
  4114.    USHORT   usVoltageBaseLevel;             // In number of 1mv unit
  4115.    USHORT   usVoltageStep;                  // Indicating in how many mv increament is one step, 1mv unit
  4116.          UCHAR          ucNumOfVoltageEntries;                                  // Number of Voltage Entry, which indicate max Voltage
  4117.          UCHAR          ucFlag;                                                                                                 // bit0=0 :step is 1mv =1 0.5mv
  4118.          UCHAR          ucBaseVID;                                                                                      // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
  4119.         UCHAR ucReserved;
  4120.          UCHAR          ucVIDAdjustEntries[32];                                 // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
  4121. }ATOM_VOLTAGE_FORMULA;
  4122.  
  4123. typedef struct  _VOLTAGE_LUT_ENTRY
  4124. {
  4125.          USHORT         usVoltageCode;                                                                  // The Voltage ID, either GPIO or I2C code
  4126.          USHORT         usVoltageValue;                                                                 // The corresponding Voltage Value, in mV
  4127. }VOLTAGE_LUT_ENTRY;
  4128.  
  4129. typedef struct  _ATOM_VOLTAGE_FORMULA_V2
  4130. {
  4131.          UCHAR          ucNumOfVoltageEntries;                                  // Number of Voltage Entry, which indicate max Voltage
  4132.          UCHAR          ucReserved[3];
  4133.          VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
  4134. }ATOM_VOLTAGE_FORMULA_V2;
  4135.  
  4136. typedef struct _ATOM_VOLTAGE_CONTROL
  4137. {
  4138.         UCHAR            ucVoltageControlId;                                                    //Indicate it is controlled by I2C or GPIO or HW state machine         
  4139.         UCHAR ucVoltageControlI2cLine;
  4140.         UCHAR ucVoltageControlAddress;
  4141.         UCHAR ucVoltageControlOffset;
  4142.   USHORT   usGpioPin_AIndex;                                                            //GPIO_PAD register index
  4143.   UCHAR    ucGpioPinBitShift[9];                                                //at most 8 pin support 255 VIDs, termintate with 0xff
  4144.         UCHAR ucReserved;
  4145. }ATOM_VOLTAGE_CONTROL;
  4146.  
  4147. // Define ucVoltageControlId
  4148. #define VOLTAGE_CONTROLLED_BY_HW                                                        0x00
  4149. #define VOLTAGE_CONTROLLED_BY_I2C_MASK                          0x7F
  4150. #define VOLTAGE_CONTROLLED_BY_GPIO                                              0x80
  4151. #define VOLTAGE_CONTROL_ID_LM64                                                         0x01                                                                    //I2C control, used for R5xx Core Voltage
  4152. #define VOLTAGE_CONTROL_ID_DAC                                                          0x02                                                                    //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
  4153. #define VOLTAGE_CONTROL_ID_VT116xM                                              0x03                                                                    //I2C control, used for R6xx Core Voltage
  4154. #define VOLTAGE_CONTROL_ID_DS4402                                                       0x04
  4155. #define VOLTAGE_CONTROL_ID_UP6266                                               0x05                                                                   
  4156. #define VOLTAGE_CONTROL_ID_SCORPIO                                              0x06
  4157. #define VOLTAGE_CONTROL_ID_VT1556M                                              0x07                                                                   
  4158. #define VOLTAGE_CONTROL_ID_CHL822x                                              0x08                                                                   
  4159. #define VOLTAGE_CONTROL_ID_VT1586M                                              0x09
  4160.  
  4161. typedef struct  _ATOM_VOLTAGE_OBJECT
  4162. {
  4163.          UCHAR          ucVoltageType;                                                                  //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI  
  4164.          UCHAR          ucSize;                                                                                                 //Size of Object       
  4165.          ATOM_VOLTAGE_CONTROL                   asControl;                      //describ how to control        
  4166.          ATOM_VOLTAGE_FORMULA                   asFormula;                      //Indicate How to convert real Voltage to VID
  4167. }ATOM_VOLTAGE_OBJECT;
  4168.  
  4169. typedef struct  _ATOM_VOLTAGE_OBJECT_V2
  4170. {
  4171.          UCHAR          ucVoltageType;                                                                  //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI  
  4172.          UCHAR          ucSize;                                                                                                 //Size of Object       
  4173.          ATOM_VOLTAGE_CONTROL                   asControl;                      //describ how to control        
  4174.          ATOM_VOLTAGE_FORMULA_V2        asFormula;                      //Indicate How to convert real Voltage to VID
  4175. }ATOM_VOLTAGE_OBJECT_V2;
  4176.  
  4177. typedef struct  _ATOM_VOLTAGE_OBJECT_INFO
  4178. {
  4179.    ATOM_COMMON_TABLE_HEADER     sHeader;
  4180.          ATOM_VOLTAGE_OBJECT                    asVoltageObj[3];        //Info for Voltage control               
  4181. }ATOM_VOLTAGE_OBJECT_INFO;
  4182.  
  4183. typedef struct  _ATOM_VOLTAGE_OBJECT_INFO_V2
  4184. {
  4185.         ATOM_COMMON_TABLE_HEADER sHeader;
  4186.          ATOM_VOLTAGE_OBJECT_V2                 asVoltageObj[3];        //Info for Voltage control               
  4187. }ATOM_VOLTAGE_OBJECT_INFO_V2;
  4188.  
  4189. typedef struct  _ATOM_LEAKID_VOLTAGE
  4190. {
  4191.         UCHAR ucLeakageId;
  4192.         UCHAR ucReserved;
  4193.         USHORT usVoltage;
  4194. }ATOM_LEAKID_VOLTAGE;
  4195.  
  4196. typedef struct  _ATOM_ASIC_PROFILE_VOLTAGE
  4197. {
  4198.         UCHAR ucProfileId;
  4199.         UCHAR ucReserved;
  4200.         USHORT usSize;
  4201.         USHORT usEfuseSpareStartAddr;
  4202.         USHORT  usFuseIndex[8];                                                                                         //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
  4203.         ATOM_LEAKID_VOLTAGE                                     asLeakVol[2];                   //Leakid and relatd voltage
  4204. }ATOM_ASIC_PROFILE_VOLTAGE;
  4205.  
  4206. //ucProfileId
  4207. #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE                      1
  4208. #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE                  1
  4209. #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE                                      2
  4210.  
  4211. typedef struct  _ATOM_ASIC_PROFILING_INFO
  4212. {
  4213.         ATOM_COMMON_TABLE_HEADER asHeader;
  4214.         ATOM_ASIC_PROFILE_VOLTAGE asVoltage;
  4215. }ATOM_ASIC_PROFILING_INFO;
  4216.  
  4217. typedef struct _ATOM_POWER_SOURCE_OBJECT
  4218. {
  4219.         UCHAR   ucPwrSrcId;                                                                                                     // Power source
  4220.         UCHAR   ucPwrSensorType;                                                                                // GPIO, I2C or none
  4221.         UCHAR   ucPwrSensId;                                                                                      // if GPIO detect, it is GPIO id,  if I2C detect, it is I2C id
  4222.         UCHAR   ucPwrSensSlaveAddr;                                                                     // Slave address if I2C detect
  4223.         UCHAR ucPwrSensRegIndex;                                                                        // I2C register Index if I2C detect
  4224.         UCHAR ucPwrSensRegBitMask;                                                              // detect which bit is used if I2C detect
  4225.         UCHAR   ucPwrSensActiveState;                                                           // high active or low active
  4226.         UCHAR   ucReserve[3];                                                                                           // reserve             
  4227.         USHORT usSensPwr;                                                                                                       // in unit of watt
  4228. }ATOM_POWER_SOURCE_OBJECT;
  4229.  
  4230. typedef struct _ATOM_POWER_SOURCE_INFO
  4231. {
  4232.         ATOM_COMMON_TABLE_HEADER asHeader;
  4233.         UCHAR asPwrbehave[16];
  4234.         ATOM_POWER_SOURCE_OBJECT asPwrObj[1];
  4235. }ATOM_POWER_SOURCE_INFO;
  4236.  
  4237.  
  4238. //Define ucPwrSrcId
  4239. #define POWERSOURCE_PCIE_ID1                                            0x00
  4240. #define POWERSOURCE_6PIN_CONNECTOR_ID1  0x01
  4241. #define POWERSOURCE_8PIN_CONNECTOR_ID1  0x02
  4242. #define POWERSOURCE_6PIN_CONNECTOR_ID2  0x04
  4243. #define POWERSOURCE_8PIN_CONNECTOR_ID2  0x08
  4244.  
  4245. //define ucPwrSensorId
  4246. #define POWER_SENSOR_ALWAYS                                                     0x00
  4247. #define POWER_SENSOR_GPIO                                                               0x01
  4248. #define POWER_SENSOR_I2C                                                                0x02
  4249.  
  4250. typedef struct _ATOM_CLK_VOLT_CAPABILITY
  4251. {
  4252.   ULONG      ulVoltageIndex;                      // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table        
  4253.   ULONG      ulMaximumSupportedCLK;               // Maximum clock supported with specified voltage index, unit in 10kHz
  4254. }ATOM_CLK_VOLT_CAPABILITY;
  4255.  
  4256. typedef struct _ATOM_AVAILABLE_SCLK_LIST
  4257. {
  4258.   ULONG      ulSupportedSCLK;               // Maximum clock supported with specified voltage index,  unit in 10kHz
  4259.   USHORT     usVoltageIndex;                // The Voltage Index indicated by FUSE for specified SCLK  
  4260.   USHORT     usVoltageID;                   // The Voltage ID indicated by FUSE for specified SCLK
  4261. }ATOM_AVAILABLE_SCLK_LIST;
  4262.  
  4263. // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition
  4264. #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE             1       // refer to ulSystemConfig bit[0]
  4265.  
  4266. // this IntegrateSystemInfoTable is used for Liano/Ontario APU
  4267. typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
  4268. {
  4269.   ATOM_COMMON_TABLE_HEADER   sHeader;
  4270.   ULONG  ulBootUpEngineClock;
  4271.   ULONG  ulDentistVCOFreq;          
  4272.   ULONG  ulBootUpUMAClock;          
  4273.   ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];            
  4274.   ULONG  ulBootUpReqDisplayVector;
  4275.   ULONG  ulOtherDisplayMisc;
  4276.   ULONG  ulGPUCapInfo;
  4277.   ULONG  ulSB_MMIO_Base_Addr;
  4278.   USHORT usRequestedPWMFreqInHz;
  4279.   UCHAR  ucHtcTmpLmt;  
  4280.   UCHAR  ucHtcHystLmt;
  4281.   ULONG  ulMinEngineClock;          
  4282.   ULONG  ulSystemConfig;            
  4283.   ULONG  ulCPUCapInfo;              
  4284.   USHORT usNBP0Voltage;              
  4285.   USHORT usNBP1Voltage;
  4286.   USHORT usBootUpNBVoltage;        
  4287.   USHORT usExtDispConnInfoOffset;  
  4288.   USHORT usPanelRefreshRateRange;    
  4289.   UCHAR  ucMemoryType;  
  4290.   UCHAR  ucUMAChannelNumber;
  4291.   ULONG  ulCSR_M3_ARB_CNTL_DEFAULT[10];  
  4292.   ULONG  ulCSR_M3_ARB_CNTL_UVD[10];
  4293.   ULONG  ulCSR_M3_ARB_CNTL_FS3D[10];
  4294.   ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
  4295.   ULONG  ulGMCRestoreResetTime;
  4296.   ULONG  ulMinimumNClk;
  4297.   ULONG  ulIdleNClk;
  4298.   ULONG  ulDDR_DLL_PowerUpTime;
  4299.   ULONG  ulDDR_PLL_PowerUpTime;
  4300.   USHORT usPCIEClkSSPercentage;
  4301.   USHORT usPCIEClkSSType;
  4302.   USHORT usLvdsSSPercentage;
  4303.   USHORT usLvdsSSpreadRateIn10Hz;
  4304.   USHORT usHDMISSPercentage;
  4305.   USHORT usHDMISSpreadRateIn10Hz;
  4306.   USHORT usDVISSPercentage;
  4307.   USHORT usDVISSpreadRateIn10Hz;
  4308.   ULONG  ulReserved3[21];
  4309.   ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;  
  4310. }ATOM_INTEGRATED_SYSTEM_INFO_V6;  
  4311.  
  4312. // ulGPUCapInfo
  4313. #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE       0x01
  4314. #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION          0x08
  4315.  
  4316. // ulOtherDisplayMisc
  4317. #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT                       0x01
  4318.  
  4319.  
  4320. /**********************************************************************************************************************
  4321.   ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
  4322. ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
  4323. ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit.
  4324. ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit.
  4325. sDISPCLK_Voltage:                 Report Display clock voltage requirement.
  4326.  
  4327. ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
  4328.                                   ATOM_DEVICE_CRT1_SUPPORT                  0x0001
  4329.                                   ATOM_DEVICE_CRT2_SUPPORT                  0x0010
  4330.                                   ATOM_DEVICE_DFP1_SUPPORT                  0x0008
  4331.                                   ATOM_DEVICE_DFP6_SUPPORT                  0x0040
  4332.                                   ATOM_DEVICE_DFP2_SUPPORT                  0x0080      
  4333.                                   ATOM_DEVICE_DFP3_SUPPORT                  0x0200      
  4334.                                   ATOM_DEVICE_DFP4_SUPPORT                  0x0400        
  4335.                                   ATOM_DEVICE_DFP5_SUPPORT                  0x0800
  4336.                                   ATOM_DEVICE_LCD1_SUPPORT                  0x0002
  4337. ulOtherDisplayMisc:                     Other display related flags, not defined yet.
  4338. ulGPUCapInfo:                     bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
  4339.                                         =1: TMDS/HDMI Coherent Mode use signel PLL mode.
  4340.                                   bit[3]=0: Enable HW AUX mode detection logic
  4341.                                         =1: Disable HW AUX mode dettion logic
  4342. ulSB_MMIO_Base_Addr:              Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
  4343.  
  4344. usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
  4345.                                   Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
  4346.                                  
  4347.                                   When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
  4348.                                   1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
  4349.                                   VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
  4350.                                   Changing BL using VBIOS function is functional in both driver and non-driver present environment;
  4351.                                   and enabling VariBri under the driver environment from PP table is optional.
  4352.  
  4353.                                   2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
  4354.                                   that BL control from GPU is expected.
  4355.                                   VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
  4356.                                   Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
  4357.                                   it's per platform
  4358.                                   and enabling VariBri under the driver environment from PP table is optional.
  4359.  
  4360. ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt.
  4361.                                   Threshold on value to enter HTC_active state.
  4362. ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt.
  4363.                                   To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
  4364. ulMinEngineClock:                 Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
  4365. ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled
  4366.                                         =1: PCIE Power Gating Enabled
  4367.                                   Bit[1]=0: DDR-DLL shut-down feature disabled.
  4368.                                          1: DDR-DLL shut-down feature enabled.
  4369.                                   Bit[2]=0: DDR-PLL Power down feature disabled.
  4370.                                          1: DDR-PLL Power down feature enabled.                                
  4371. ulCPUCapInfo:                     TBD
  4372. usNBP0Voltage:                    VID for voltage on NB P0 State
  4373. usNBP1Voltage:                    VID for voltage on NB P1 State  
  4374. usBootUpNBVoltage:                Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
  4375. usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
  4376. usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
  4377.                                   to indicate a range.
  4378.                                   SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
  4379.                                   SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
  4380.                                   SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
  4381.                                   SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
  4382. ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
  4383. ucUMAChannelNumber:                     System memory channel numbers.
  4384. ulCSR_M3_ARB_CNTL_DEFAULT[10]:    Arrays with values for CSR M3 arbiter for default
  4385. ulCSR_M3_ARB_CNTL_UVD[10]:        Arrays with values for CSR M3 arbiter for UVD playback.
  4386. ulCSR_M3_ARB_CNTL_FS3D[10]:       Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
  4387. sAvail_SCLK[5]:                   Arrays to provide available list of SLCK and corresponding voltage, order from low to high  
  4388. ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
  4389. ulMinimumNClk:                    Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
  4390. ulIdleNClk:                       NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
  4391. ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
  4392. ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
  4393. usPCIEClkSSPercentage:            PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
  4394. usPCIEClkSSType:                  PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
  4395. usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
  4396. usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
  4397. usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
  4398. usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
  4399. usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
  4400. usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
  4401. **********************************************************************************************************************/
  4402.  
  4403. /**************************************************************************/
  4404. // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
  4405. //Memory SS Info Table
  4406. //Define Memory Clock SS chip ID
  4407. #define ICS91719  1
  4408. #define ICS91720  2
  4409.  
  4410. //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
  4411. typedef struct _ATOM_I2C_DATA_RECORD
  4412. {
  4413.   UCHAR         ucNunberOfBytes;                                              //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
  4414.   UCHAR         ucI2CData[1];                                                 //I2C data in bytes, should be less than 16 bytes usually
  4415. }ATOM_I2C_DATA_RECORD;
  4416.  
  4417.  
  4418. //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
  4419. typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
  4420. {
  4421.   ATOM_I2C_ID_CONFIG_ACCESS       sucI2cId;               //I2C line and HW/SW assisted cap.
  4422.   UCHAR                                 ucSSChipID;             //SS chip being used
  4423.   UCHAR                                 ucSSChipSlaveAddr;      //Slave Address to set up this SS chip
  4424.   UCHAR                           ucNumOfI2CDataRecords;  //number of data block
  4425.         ATOM_I2C_DATA_RECORD asI2CData[1];
  4426. }ATOM_I2C_DEVICE_SETUP_INFO;
  4427.  
  4428. //==========================================================================================
  4429. typedef struct  _ATOM_ASIC_MVDD_INFO
  4430. {
  4431.         ATOM_COMMON_TABLE_HEADER sHeader;
  4432.         ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1];
  4433. }ATOM_ASIC_MVDD_INFO;
  4434.  
  4435. //==========================================================================================
  4436. #define ATOM_MCLK_SS_INFO         ATOM_ASIC_MVDD_INFO
  4437.  
  4438. //==========================================================================================
  4439. /**************************************************************************/
  4440.  
  4441. typedef struct _ATOM_ASIC_SS_ASSIGNMENT
  4442. {
  4443.         ULONG                                                           ulTargetClockRange;                                             //Clock Out frequence (VCO ), in unit of 10Khz
  4444.   USHORT              usSpreadSpectrumPercentage;               //in unit of 0.01%
  4445.         USHORT                                                  usSpreadRateInKhz;                                              //in unit of kHz, modulation freq
  4446.   UCHAR               ucClockIndication;                                          //Indicate which clock source needs SS
  4447.         UCHAR                                                           ucSpreadSpectrumMode;                                   //Bit1=0 Down Spread,=1 Center Spread.
  4448.         UCHAR ucReserved[2];
  4449. }ATOM_ASIC_SS_ASSIGNMENT;
  4450.  
  4451. //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type.
  4452. //SS is not required or enabled if a match is not found.
  4453. #define ASIC_INTERNAL_MEMORY_SS                 1
  4454. #define ASIC_INTERNAL_ENGINE_SS                 2
  4455. #define ASIC_INTERNAL_UVD_SS                            3
  4456. #define ASIC_INTERNAL_SS_ON_TMDS    4
  4457. #define ASIC_INTERNAL_SS_ON_HDMI    5
  4458. #define ASIC_INTERNAL_SS_ON_LVDS    6
  4459. #define ASIC_INTERNAL_SS_ON_DP      7
  4460. #define ASIC_INTERNAL_SS_ON_DCPLL   8
  4461. #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9
  4462.  
  4463. typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
  4464. {
  4465.         ULONG                                                           ulTargetClockRange;                                             //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
  4466.                                                     //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
  4467.   USHORT              usSpreadSpectrumPercentage;               //in unit of 0.01%
  4468.         USHORT                                                  usSpreadRateIn10Hz;                                             //in unit of 10Hz, modulation freq
  4469.   UCHAR               ucClockIndication;                                          //Indicate which clock source needs SS
  4470.         UCHAR                                                           ucSpreadSpectrumMode;                                   //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
  4471.         UCHAR                                                           ucReserved[2];
  4472. }ATOM_ASIC_SS_ASSIGNMENT_V2;
  4473.  
  4474. //ucSpreadSpectrumMode
  4475. //#define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
  4476. //#define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
  4477. //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
  4478. //#define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
  4479. //#define ATOM_INTERNAL_SS_MASK                  0x00000000
  4480. //#define ATOM_EXTERNAL_SS_MASK                  0x00000002
  4481.  
  4482. typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
  4483. {
  4484.         ATOM_COMMON_TABLE_HEADER sHeader;
  4485.         ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4];
  4486. }ATOM_ASIC_INTERNAL_SS_INFO;
  4487.  
  4488. typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
  4489. {
  4490.   ATOM_COMMON_TABLE_HEADER            sHeader;
  4491.   ATOM_ASIC_SS_ASSIGNMENT_V2              asSpreadSpectrum[1];      //this is point only.
  4492. }ATOM_ASIC_INTERNAL_SS_INFO_V2;
  4493.  
  4494. typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
  4495. {
  4496.         ULONG                                                           ulTargetClockRange;                                             //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
  4497.                                                     //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
  4498.   USHORT              usSpreadSpectrumPercentage;               //in unit of 0.01%
  4499.         USHORT                                                  usSpreadRateIn10Hz;                                             //in unit of 10Hz, modulation freq
  4500.   UCHAR               ucClockIndication;                                          //Indicate which clock source needs SS
  4501.         UCHAR                                                           ucSpreadSpectrumMode;                                   //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
  4502.         UCHAR                                                           ucReserved[2];
  4503. }ATOM_ASIC_SS_ASSIGNMENT_V3;
  4504.  
  4505. typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
  4506. {
  4507.   ATOM_COMMON_TABLE_HEADER            sHeader;
  4508.   ATOM_ASIC_SS_ASSIGNMENT_V3              asSpreadSpectrum[1];      //this is pointer only.
  4509. }ATOM_ASIC_INTERNAL_SS_INFO_V3;
  4510.  
  4511.  
  4512. //==============================Scratch Pad Definition Portion===============================
  4513. #define ATOM_DEVICE_CONNECT_INFO_DEF  0
  4514. #define ATOM_ROM_LOCATION_DEF         1
  4515. #define ATOM_TV_STANDARD_DEF          2
  4516. #define ATOM_ACTIVE_INFO_DEF          3
  4517. #define ATOM_LCD_INFO_DEF             4
  4518. #define ATOM_DOS_REQ_INFO_DEF         5
  4519. #define ATOM_ACC_CHANGE_INFO_DEF      6
  4520. #define ATOM_DOS_MODE_INFO_DEF        7
  4521. #define ATOM_I2C_CHANNEL_STATUS_DEF   8
  4522. #define ATOM_I2C_CHANNEL_STATUS1_DEF  9
  4523.  
  4524.  
  4525. // BIOS_0_SCRATCH Definition
  4526. #define ATOM_S0_CRT1_MONO               0x00000001L
  4527. #define ATOM_S0_CRT1_COLOR              0x00000002L
  4528. #define ATOM_S0_CRT1_MASK               (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
  4529.  
  4530. #define ATOM_S0_TV1_COMPOSITE_A         0x00000004L
  4531. #define ATOM_S0_TV1_SVIDEO_A            0x00000008L
  4532. #define ATOM_S0_TV1_MASK_A              (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
  4533.  
  4534. #define ATOM_S0_CV_A                    0x00000010L
  4535. #define ATOM_S0_CV_DIN_A                0x00000020L
  4536. #define ATOM_S0_CV_MASK_A               (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
  4537.  
  4538.  
  4539. #define ATOM_S0_CRT2_MONO               0x00000100L
  4540. #define ATOM_S0_CRT2_COLOR              0x00000200L
  4541. #define ATOM_S0_CRT2_MASK               (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
  4542.  
  4543. #define ATOM_S0_TV1_COMPOSITE           0x00000400L
  4544. #define ATOM_S0_TV1_SVIDEO              0x00000800L
  4545. #define ATOM_S0_TV1_SCART               0x00004000L
  4546. #define ATOM_S0_TV1_MASK                (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
  4547.  
  4548. #define ATOM_S0_CV                      0x00001000L
  4549. #define ATOM_S0_CV_DIN                  0x00002000L
  4550. #define ATOM_S0_CV_MASK                 (ATOM_S0_CV+ATOM_S0_CV_DIN)
  4551.  
  4552. #define ATOM_S0_DFP1                    0x00010000L
  4553. #define ATOM_S0_DFP2                    0x00020000L
  4554. #define ATOM_S0_LCD1                    0x00040000L
  4555. #define ATOM_S0_LCD2                    0x00080000L
  4556. #define ATOM_S0_DFP6                    0x00100000L
  4557. #define ATOM_S0_DFP3                    0x00200000L
  4558. #define ATOM_S0_DFP4                    0x00400000L
  4559. #define ATOM_S0_DFP5                    0x00800000L
  4560.  
  4561. #define ATOM_S0_DFP_MASK                ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
  4562.  
  4563. #define ATOM_S0_FAD_REGISTER_BUG        0x02000000L // If set, indicates we are running a PCIE asic with
  4564.                                                     // the FAD/HDP reg access bug.  Bit is read by DAL, this is obsolete from RV5xx
  4565.  
  4566. #define ATOM_S0_THERMAL_STATE_MASK      0x1C000000L
  4567. #define ATOM_S0_THERMAL_STATE_SHIFT     26
  4568.  
  4569. #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
  4570. #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
  4571.  
  4572. #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC     1
  4573. #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC     2
  4574. #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
  4575. #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
  4576.  
  4577. //Byte aligned definition for BIOS usage
  4578. #define ATOM_S0_CRT1_MONOb0             0x01
  4579. #define ATOM_S0_CRT1_COLORb0            0x02
  4580. #define ATOM_S0_CRT1_MASKb0             (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
  4581.  
  4582. #define ATOM_S0_TV1_COMPOSITEb0         0x04
  4583. #define ATOM_S0_TV1_SVIDEOb0            0x08
  4584. #define ATOM_S0_TV1_MASKb0              (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
  4585.  
  4586. #define ATOM_S0_CVb0                    0x10
  4587. #define ATOM_S0_CV_DINb0                0x20
  4588. #define ATOM_S0_CV_MASKb0               (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
  4589.  
  4590. #define ATOM_S0_CRT2_MONOb1             0x01
  4591. #define ATOM_S0_CRT2_COLORb1            0x02
  4592. #define ATOM_S0_CRT2_MASKb1             (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
  4593.  
  4594. #define ATOM_S0_TV1_COMPOSITEb1         0x04
  4595. #define ATOM_S0_TV1_SVIDEOb1            0x08
  4596. #define ATOM_S0_TV1_SCARTb1             0x40
  4597. #define ATOM_S0_TV1_MASKb1              (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
  4598.  
  4599. #define ATOM_S0_CVb1                    0x10
  4600. #define ATOM_S0_CV_DINb1                0x20
  4601. #define ATOM_S0_CV_MASKb1               (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
  4602.  
  4603. #define ATOM_S0_DFP1b2                  0x01
  4604. #define ATOM_S0_DFP2b2                  0x02
  4605. #define ATOM_S0_LCD1b2                  0x04
  4606. #define ATOM_S0_LCD2b2                  0x08
  4607. #define ATOM_S0_DFP6b2                  0x10
  4608. #define ATOM_S0_DFP3b2                                                                  0x20
  4609. #define ATOM_S0_DFP4b2                  0x40
  4610. #define ATOM_S0_DFP5b2                  0x80
  4611.  
  4612.  
  4613. #define ATOM_S0_THERMAL_STATE_MASKb3    0x1C
  4614. #define ATOM_S0_THERMAL_STATE_SHIFTb3   2
  4615.  
  4616. #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
  4617. #define ATOM_S0_LCD1_SHIFT              18
  4618.  
  4619. // BIOS_1_SCRATCH Definition
  4620. #define ATOM_S1_ROM_LOCATION_MASK       0x0000FFFFL
  4621. #define ATOM_S1_PCI_BUS_DEV_MASK        0xFFFF0000L
  4622.  
  4623. //      BIOS_2_SCRATCH Definition
  4624. #define ATOM_S2_TV1_STANDARD_MASK       0x0000000FL
  4625. #define ATOM_S2_CURRENT_BL_LEVEL_MASK   0x0000FF00L
  4626. #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT  8
  4627.  
  4628. #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK       0x0C000000L
  4629. #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
  4630. #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE     0x10000000L
  4631.  
  4632. #define ATOM_S2_DEVICE_DPMS_STATE       0x00010000L
  4633. #define ATOM_S2_VRI_BRIGHT_ENABLE       0x20000000L
  4634.  
  4635. #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE     0x0
  4636. #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE    0x1
  4637. #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE   0x2
  4638. #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE   0x3
  4639. #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
  4640. #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK   0xC0000000L
  4641.  
  4642.  
  4643. //Byte aligned definition for BIOS usage
  4644. #define ATOM_S2_TV1_STANDARD_MASKb0     0x0F
  4645. #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
  4646. #define ATOM_S2_DEVICE_DPMS_STATEb2     0x01
  4647.  
  4648. #define ATOM_S2_DEVICE_DPMS_MASKw1      0x3FF
  4649. #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3     0x0C
  4650. #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3   0x10
  4651. #define ATOM_S2_VRI_BRIGHT_ENABLEb3     0x20
  4652. #define ATOM_S2_ROTATION_STATE_MASKb3   0xC0
  4653.  
  4654.  
  4655. // BIOS_3_SCRATCH Definition
  4656. #define ATOM_S3_CRT1_ACTIVE             0x00000001L
  4657. #define ATOM_S3_LCD1_ACTIVE             0x00000002L
  4658. #define ATOM_S3_TV1_ACTIVE              0x00000004L
  4659. #define ATOM_S3_DFP1_ACTIVE             0x00000008L
  4660. #define ATOM_S3_CRT2_ACTIVE             0x00000010L
  4661. #define ATOM_S3_LCD2_ACTIVE             0x00000020L
  4662. #define ATOM_S3_DFP6_ACTIVE             0x00000040L
  4663. #define ATOM_S3_DFP2_ACTIVE             0x00000080L
  4664. #define ATOM_S3_CV_ACTIVE               0x00000100L
  4665. #define ATOM_S3_DFP3_ACTIVE                                                     0x00000200L
  4666. #define ATOM_S3_DFP4_ACTIVE                                                     0x00000400L
  4667. #define ATOM_S3_DFP5_ACTIVE                                                     0x00000800L
  4668.  
  4669. #define ATOM_S3_DEVICE_ACTIVE_MASK      0x00000FFFL
  4670.  
  4671. #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE         0x00001000L
  4672. #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
  4673.  
  4674. #define ATOM_S3_CRT1_CRTC_ACTIVE        0x00010000L
  4675. #define ATOM_S3_LCD1_CRTC_ACTIVE        0x00020000L
  4676. #define ATOM_S3_TV1_CRTC_ACTIVE         0x00040000L
  4677. #define ATOM_S3_DFP1_CRTC_ACTIVE        0x00080000L
  4678. #define ATOM_S3_CRT2_CRTC_ACTIVE        0x00100000L
  4679. #define ATOM_S3_LCD2_CRTC_ACTIVE        0x00200000L
  4680. #define ATOM_S3_DFP6_CRTC_ACTIVE        0x00400000L
  4681. #define ATOM_S3_DFP2_CRTC_ACTIVE        0x00800000L
  4682. #define ATOM_S3_CV_CRTC_ACTIVE          0x01000000L
  4683. #define ATOM_S3_DFP3_CRTC_ACTIVE                                0x02000000L
  4684. #define ATOM_S3_DFP4_CRTC_ACTIVE                                0x04000000L
  4685. #define ATOM_S3_DFP5_CRTC_ACTIVE                                0x08000000L
  4686.  
  4687. #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
  4688. #define ATOM_S3_ASIC_GUI_ENGINE_HUNG    0x20000000L
  4689. //Below two definitions are not supported in pplib, but in the old powerplay in DAL
  4690. #define ATOM_S3_ALLOW_FAST_PWR_SWITCH   0x40000000L
  4691. #define ATOM_S3_RQST_GPU_USE_MIN_PWR    0x80000000L
  4692.  
  4693. //Byte aligned definition for BIOS usage
  4694. #define ATOM_S3_CRT1_ACTIVEb0           0x01
  4695. #define ATOM_S3_LCD1_ACTIVEb0           0x02
  4696. #define ATOM_S3_TV1_ACTIVEb0            0x04
  4697. #define ATOM_S3_DFP1_ACTIVEb0           0x08
  4698. #define ATOM_S3_CRT2_ACTIVEb0           0x10
  4699. #define ATOM_S3_LCD2_ACTIVEb0           0x20
  4700. #define ATOM_S3_DFP6_ACTIVEb0           0x40
  4701. #define ATOM_S3_DFP2_ACTIVEb0           0x80
  4702. #define ATOM_S3_CV_ACTIVEb1             0x01
  4703. #define ATOM_S3_DFP3_ACTIVEb1                                           0x02
  4704. #define ATOM_S3_DFP4_ACTIVEb1                                           0x04
  4705. #define ATOM_S3_DFP5_ACTIVEb1                                           0x08
  4706.  
  4707. #define ATOM_S3_ACTIVE_CRTC1w0          0xFFF
  4708.  
  4709. #define ATOM_S3_CRT1_CRTC_ACTIVEb2      0x01
  4710. #define ATOM_S3_LCD1_CRTC_ACTIVEb2      0x02
  4711. #define ATOM_S3_TV1_CRTC_ACTIVEb2       0x04
  4712. #define ATOM_S3_DFP1_CRTC_ACTIVEb2      0x08
  4713. #define ATOM_S3_CRT2_CRTC_ACTIVEb2      0x10
  4714. #define ATOM_S3_LCD2_CRTC_ACTIVEb2      0x20
  4715. #define ATOM_S3_DFP6_CRTC_ACTIVEb2      0x40
  4716. #define ATOM_S3_DFP2_CRTC_ACTIVEb2      0x80
  4717. #define ATOM_S3_CV_CRTC_ACTIVEb3        0x01
  4718. #define ATOM_S3_DFP3_CRTC_ACTIVEb3                      0x02
  4719. #define ATOM_S3_DFP4_CRTC_ACTIVEb3                      0x04
  4720. #define ATOM_S3_DFP5_CRTC_ACTIVEb3                      0x08
  4721.  
  4722. #define ATOM_S3_ACTIVE_CRTC2w1          0xFFF
  4723.  
  4724. // BIOS_4_SCRATCH Definition
  4725. #define ATOM_S4_LCD1_PANEL_ID_MASK      0x000000FFL
  4726. #define ATOM_S4_LCD1_REFRESH_MASK       0x0000FF00L
  4727. #define ATOM_S4_LCD1_REFRESH_SHIFT      8
  4728.  
  4729. //Byte aligned definition for BIOS usage
  4730. #define ATOM_S4_LCD1_PANEL_ID_MASKb0      0x0FF
  4731. #define ATOM_S4_LCD1_REFRESH_MASKb1               ATOM_S4_LCD1_PANEL_ID_MASKb0
  4732. #define ATOM_S4_VRAM_INFO_MASKb2        ATOM_S4_LCD1_PANEL_ID_MASKb0
  4733.  
  4734. // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
  4735. #define ATOM_S5_DOS_REQ_CRT1b0          0x01
  4736. #define ATOM_S5_DOS_REQ_LCD1b0          0x02
  4737. #define ATOM_S5_DOS_REQ_TV1b0           0x04
  4738. #define ATOM_S5_DOS_REQ_DFP1b0          0x08
  4739. #define ATOM_S5_DOS_REQ_CRT2b0          0x10
  4740. #define ATOM_S5_DOS_REQ_LCD2b0          0x20
  4741. #define ATOM_S5_DOS_REQ_DFP6b0          0x40
  4742. #define ATOM_S5_DOS_REQ_DFP2b0          0x80
  4743. #define ATOM_S5_DOS_REQ_CVb1            0x01
  4744. #define ATOM_S5_DOS_REQ_DFP3b1                                  0x02
  4745. #define ATOM_S5_DOS_REQ_DFP4b1                                  0x04
  4746. #define ATOM_S5_DOS_REQ_DFP5b1                                  0x08
  4747.  
  4748. #define ATOM_S5_DOS_REQ_DEVICEw0        0x0FFF
  4749.  
  4750. #define ATOM_S5_DOS_REQ_CRT1            0x0001
  4751. #define ATOM_S5_DOS_REQ_LCD1            0x0002
  4752. #define ATOM_S5_DOS_REQ_TV1             0x0004
  4753. #define ATOM_S5_DOS_REQ_DFP1            0x0008
  4754. #define ATOM_S5_DOS_REQ_CRT2            0x0010
  4755. #define ATOM_S5_DOS_REQ_LCD2            0x0020
  4756. #define ATOM_S5_DOS_REQ_DFP6            0x0040
  4757. #define ATOM_S5_DOS_REQ_DFP2            0x0080
  4758. #define ATOM_S5_DOS_REQ_CV              0x0100
  4759. #define ATOM_S5_DOS_REQ_DFP3                                            0x0200
  4760. #define ATOM_S5_DOS_REQ_DFP4                                            0x0400
  4761. #define ATOM_S5_DOS_REQ_DFP5                                            0x0800
  4762.  
  4763. #define ATOM_S5_DOS_FORCE_CRT1b2        ATOM_S5_DOS_REQ_CRT1b0
  4764. #define ATOM_S5_DOS_FORCE_TV1b2         ATOM_S5_DOS_REQ_TV1b0
  4765. #define ATOM_S5_DOS_FORCE_CRT2b2        ATOM_S5_DOS_REQ_CRT2b0
  4766. #define ATOM_S5_DOS_FORCE_CVb3          ATOM_S5_DOS_REQ_CVb1
  4767. #define ATOM_S5_DOS_FORCE_DEVICEw1      (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
  4768.                                         (ATOM_S5_DOS_FORCE_CVb3<<8))
  4769.  
  4770. // BIOS_6_SCRATCH Definition
  4771. #define ATOM_S6_DEVICE_CHANGE           0x00000001L
  4772. #define ATOM_S6_SCALER_CHANGE           0x00000002L
  4773. #define ATOM_S6_LID_CHANGE              0x00000004L
  4774. #define ATOM_S6_DOCKING_CHANGE          0x00000008L
  4775. #define ATOM_S6_ACC_MODE                0x00000010L
  4776. #define ATOM_S6_EXT_DESKTOP_MODE        0x00000020L
  4777. #define ATOM_S6_LID_STATE               0x00000040L
  4778. #define ATOM_S6_DOCK_STATE              0x00000080L
  4779. #define ATOM_S6_CRITICAL_STATE          0x00000100L
  4780. #define ATOM_S6_HW_I2C_BUSY_STATE       0x00000200L
  4781. #define ATOM_S6_THERMAL_STATE_CHANGE    0x00000400L
  4782. #define ATOM_S6_INTERRUPT_SET_BY_BIOS   0x00000800L
  4783. #define ATOM_S6_REQ_LCD_EXPANSION_FULL         0x00001000L //Normal expansion Request bit for LCD
  4784. #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO  0x00002000L //Aspect ratio expansion Request bit for LCD
  4785.  
  4786. #define ATOM_S6_DISPLAY_STATE_CHANGE    0x00004000L        //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
  4787. #define ATOM_S6_I2C_STATE_CHANGE        0x00008000L        //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
  4788.  
  4789. #define ATOM_S6_ACC_REQ_CRT1            0x00010000L
  4790. #define ATOM_S6_ACC_REQ_LCD1            0x00020000L
  4791. #define ATOM_S6_ACC_REQ_TV1             0x00040000L
  4792. #define ATOM_S6_ACC_REQ_DFP1            0x00080000L
  4793. #define ATOM_S6_ACC_REQ_CRT2            0x00100000L
  4794. #define ATOM_S6_ACC_REQ_LCD2            0x00200000L
  4795. #define ATOM_S6_ACC_REQ_DFP6            0x00400000L
  4796. #define ATOM_S6_ACC_REQ_DFP2            0x00800000L
  4797. #define ATOM_S6_ACC_REQ_CV              0x01000000L
  4798. #define ATOM_S6_ACC_REQ_DFP3                                            0x02000000L
  4799. #define ATOM_S6_ACC_REQ_DFP4                                            0x04000000L
  4800. #define ATOM_S6_ACC_REQ_DFP5                                            0x08000000L
  4801.  
  4802. #define ATOM_S6_ACC_REQ_MASK                0x0FFF0000L
  4803. #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE    0x10000000L
  4804. #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH    0x20000000L
  4805. #define ATOM_S6_VRI_BRIGHTNESS_CHANGE       0x40000000L
  4806. #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK  0x80000000L
  4807.  
  4808. //Byte aligned definition for BIOS usage
  4809. #define ATOM_S6_DEVICE_CHANGEb0         0x01
  4810. #define ATOM_S6_SCALER_CHANGEb0         0x02
  4811. #define ATOM_S6_LID_CHANGEb0            0x04
  4812. #define ATOM_S6_DOCKING_CHANGEb0        0x08
  4813. #define ATOM_S6_ACC_MODEb0              0x10
  4814. #define ATOM_S6_EXT_DESKTOP_MODEb0      0x20
  4815. #define ATOM_S6_LID_STATEb0             0x40
  4816. #define ATOM_S6_DOCK_STATEb0            0x80
  4817. #define ATOM_S6_CRITICAL_STATEb1        0x01
  4818. #define ATOM_S6_HW_I2C_BUSY_STATEb1     0x02
  4819. #define ATOM_S6_THERMAL_STATE_CHANGEb1  0x04
  4820. #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
  4821. #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1        0x10
  4822. #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
  4823.  
  4824. #define ATOM_S6_ACC_REQ_CRT1b2          0x01
  4825. #define ATOM_S6_ACC_REQ_LCD1b2          0x02
  4826. #define ATOM_S6_ACC_REQ_TV1b2           0x04
  4827. #define ATOM_S6_ACC_REQ_DFP1b2          0x08
  4828. #define ATOM_S6_ACC_REQ_CRT2b2          0x10
  4829. #define ATOM_S6_ACC_REQ_LCD2b2          0x20
  4830. #define ATOM_S6_ACC_REQ_DFP6b2          0x40
  4831. #define ATOM_S6_ACC_REQ_DFP2b2          0x80
  4832. #define ATOM_S6_ACC_REQ_CVb3            0x01
  4833. #define ATOM_S6_ACC_REQ_DFP3b3                                  0x02
  4834. #define ATOM_S6_ACC_REQ_DFP4b3                                  0x04
  4835. #define ATOM_S6_ACC_REQ_DFP5b3                                  0x08
  4836.  
  4837. #define ATOM_S6_ACC_REQ_DEVICEw1        ATOM_S5_DOS_REQ_DEVICEw0
  4838. #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
  4839. #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
  4840. #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3    0x40
  4841. #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3    0x80
  4842.  
  4843. #define ATOM_S6_DEVICE_CHANGE_SHIFT             0
  4844. #define ATOM_S6_SCALER_CHANGE_SHIFT             1
  4845. #define ATOM_S6_LID_CHANGE_SHIFT                2
  4846. #define ATOM_S6_DOCKING_CHANGE_SHIFT            3
  4847. #define ATOM_S6_ACC_MODE_SHIFT                  4
  4848. #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT          5
  4849. #define ATOM_S6_LID_STATE_SHIFT                 6
  4850. #define ATOM_S6_DOCK_STATE_SHIFT                7
  4851. #define ATOM_S6_CRITICAL_STATE_SHIFT            8
  4852. #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT         9
  4853. #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT      10
  4854. #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT     11
  4855. #define ATOM_S6_REQ_SCALER_SHIFT                12
  4856. #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT         13
  4857. #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT      14
  4858. #define ATOM_S6_I2C_STATE_CHANGE_SHIFT          15
  4859. #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT  28
  4860. #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT  29
  4861. #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT     30
  4862. #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT     31
  4863.  
  4864. // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
  4865. #define ATOM_S7_DOS_MODE_TYPEb0             0x03
  4866. #define ATOM_S7_DOS_MODE_VGAb0              0x00
  4867. #define ATOM_S7_DOS_MODE_VESAb0             0x01
  4868. #define ATOM_S7_DOS_MODE_EXTb0              0x02
  4869. #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0      0x0C
  4870. #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0     0xF0
  4871. #define ATOM_S7_DOS_8BIT_DAC_ENb1           0x01
  4872. #define ATOM_S7_DOS_MODE_NUMBERw1           0x0FFFF
  4873.  
  4874. #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT       8
  4875.  
  4876. // BIOS_8_SCRATCH Definition
  4877. #define ATOM_S8_I2C_CHANNEL_BUSY_MASK       0x00000FFFF
  4878. #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK     0x0FFFF0000
  4879.  
  4880. #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT      0
  4881. #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT       16
  4882.  
  4883. // BIOS_9_SCRATCH Definition
  4884. #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
  4885. #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK  0x0000FFFF
  4886. #endif
  4887. #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
  4888. #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK    0xFFFF0000
  4889. #endif
  4890. #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
  4891. #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
  4892. #endif
  4893. #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
  4894. #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT   16
  4895. #endif
  4896.  
  4897.  
  4898. #define ATOM_FLAG_SET                         0x20
  4899. #define ATOM_FLAG_CLEAR                       0
  4900. #define CLEAR_ATOM_S6_ACC_MODE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
  4901. #define SET_ATOM_S6_DEVICE_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
  4902. #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
  4903. #define SET_ATOM_S6_SCALER_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
  4904. #define SET_ATOM_S6_LID_CHANGE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
  4905.  
  4906. #define SET_ATOM_S6_LID_STATE                 ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
  4907. #define CLEAR_ATOM_S6_LID_STATE               ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
  4908.  
  4909. #define SET_ATOM_S6_DOCK_CHANGE                           ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
  4910. #define SET_ATOM_S6_DOCK_STATE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
  4911. #define CLEAR_ATOM_S6_DOCK_STATE              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
  4912.  
  4913. #define SET_ATOM_S6_THERMAL_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
  4914. #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE  ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
  4915. #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
  4916.  
  4917. #define SET_ATOM_S6_CRITICAL_STATE            ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
  4918. #define CLEAR_ATOM_S6_CRITICAL_STATE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
  4919.  
  4920. #define SET_ATOM_S6_REQ_SCALER                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)  
  4921. #define CLEAR_ATOM_S6_REQ_SCALER              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
  4922.  
  4923. #define SET_ATOM_S6_REQ_SCALER_ARATIO         ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
  4924. #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO       ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
  4925.  
  4926. #define SET_ATOM_S6_I2C_STATE_CHANGE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
  4927.  
  4928. #define SET_ATOM_S6_DISPLAY_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
  4929.  
  4930. #define SET_ATOM_S6_DEVICE_RECONFIG           ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
  4931. #define CLEAR_ATOM_S0_LCD1                    ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )|  ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
  4932. #define SET_ATOM_S7_DOS_8BIT_DAC_EN           ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
  4933. #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN         ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
  4934.  
  4935. /****************************************************************************/
  4936. //Portion II: Definitinos only used in Driver
  4937. /****************************************************************************/
  4938.  
  4939. // Macros used by driver
  4940. #ifdef __cplusplus
  4941. #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
  4942.  
  4943. #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
  4944. #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
  4945. #else // not __cplusplus
  4946. #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
  4947.  
  4948. #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
  4949. #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
  4950. #endif // __cplusplus
  4951.  
  4952. #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
  4953. #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
  4954.  
  4955. /****************************************************************************/
  4956. //Portion III: Definitinos only used in VBIOS
  4957. /****************************************************************************/
  4958. #define ATOM_DAC_SRC                                    0x80
  4959. #define ATOM_SRC_DAC1                                   0
  4960. #define ATOM_SRC_DAC2                                   0x80
  4961.  
  4962. typedef struct _MEMORY_PLLINIT_PARAMETERS
  4963. {
  4964.   ULONG ulTargetMemoryClock; //In 10Khz unit
  4965.   UCHAR   ucAction;                                      //not define yet
  4966.   UCHAR   ucFbDiv_Hi;                            //Fbdiv Hi byte
  4967.   UCHAR   ucFbDiv;                                       //FB value
  4968.   UCHAR   ucPostDiv;                             //Post div
  4969. }MEMORY_PLLINIT_PARAMETERS;
  4970.  
  4971. #define MEMORY_PLLINIT_PS_ALLOCATION  MEMORY_PLLINIT_PARAMETERS
  4972.  
  4973.  
  4974. #define GPIO_PIN_WRITE                                                                                                  0x01
  4975. #define GPIO_PIN_READ                                                                                                           0x00
  4976.  
  4977. typedef struct  _GPIO_PIN_CONTROL_PARAMETERS
  4978. {
  4979.   UCHAR ucGPIO_ID;           //return value, read from GPIO pins
  4980.   UCHAR ucGPIOBitShift;      //define which bit in uGPIOBitVal need to be update
  4981.         UCHAR ucGPIOBitVal;                  //Set/Reset corresponding bit defined in ucGPIOBitMask
  4982.   UCHAR ucAction;                                    //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
  4983. }GPIO_PIN_CONTROL_PARAMETERS;
  4984.  
  4985. typedef struct _ENABLE_SCALER_PARAMETERS
  4986. {
  4987.   UCHAR ucScaler;            // ATOM_SCALER1, ATOM_SCALER2
  4988.   UCHAR ucEnable;            // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
  4989.   UCHAR ucTVStandard;        //
  4990.         UCHAR ucPadding[1];
  4991. }ENABLE_SCALER_PARAMETERS;
  4992. #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
  4993.  
  4994. //ucEnable:
  4995. #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION    0
  4996. #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION  1
  4997. #define SCALER_ENABLE_2TAP_ALPHA_MODE               2
  4998. #define SCALER_ENABLE_MULTITAP_MODE                 3
  4999.  
  5000. typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
  5001. {
  5002.   ULONG  usHWIconHorzVertPosn;        // Hardware Icon Vertical position
  5003.   UCHAR  ucHWIconVertOffset;          // Hardware Icon Vertical offset
  5004.   UCHAR  ucHWIconHorzOffset;          // Hardware Icon Horizontal offset
  5005.   UCHAR  ucSelection;                 // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
  5006.   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
  5007. }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
  5008.  
  5009. typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
  5010. {
  5011.         ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon;
  5012.         ENABLE_CRTC_PARAMETERS sReserved;
  5013. }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
  5014.  
  5015. typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
  5016. {
  5017.   USHORT usHight;                     // Image Hight
  5018.   USHORT usWidth;                     // Image Width
  5019.   UCHAR  ucSurface;                   // Surface 1 or 2
  5020.         UCHAR ucPadding[3];
  5021. }ENABLE_GRAPH_SURFACE_PARAMETERS;
  5022.  
  5023. typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
  5024. {
  5025.   USHORT usHight;                     // Image Hight
  5026.   USHORT usWidth;                     // Image Width
  5027.   UCHAR  ucSurface;                   // Surface 1 or 2
  5028.   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
  5029.         UCHAR ucPadding[2];
  5030. }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
  5031.  
  5032. typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
  5033. {
  5034.   USHORT usHight;                     // Image Hight
  5035.   USHORT usWidth;                     // Image Width
  5036.   UCHAR  ucSurface;                   // Surface 1 or 2
  5037.   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
  5038.   USHORT usDeviceId;                  // Active Device Id for this surface. If no device, set to 0.
  5039. }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
  5040.  
  5041. typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
  5042. {
  5043.         ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
  5044.   ENABLE_YUV_PS_ALLOCATION        sReserved; // Don't set this one
  5045. }ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
  5046.  
  5047. typedef struct _MEMORY_CLEAN_UP_PARAMETERS
  5048. {
  5049.   USHORT  usMemoryStart;                //in 8Kb boundary, offset from memory base address
  5050.   USHORT  usMemorySize;                 //8Kb blocks aligned
  5051. }MEMORY_CLEAN_UP_PARAMETERS;
  5052. #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
  5053.  
  5054. typedef struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
  5055. {
  5056.   USHORT  usX_Size;                     //When use as input parameter, usX_Size indicates which CRTC                
  5057.         USHORT usY_Size;
  5058. }GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
  5059.  
  5060. typedef struct _INDIRECT_IO_ACCESS
  5061. {
  5062.         ATOM_COMMON_TABLE_HEADER sHeader;
  5063.         UCHAR IOAccessSequence[256];
  5064. } INDIRECT_IO_ACCESS;
  5065.  
  5066. #define INDIRECT_READ              0x00
  5067. #define INDIRECT_WRITE             0x80
  5068.  
  5069. #define INDIRECT_IO_MM             0
  5070. #define INDIRECT_IO_PLL            1
  5071. #define INDIRECT_IO_MC             2
  5072. #define INDIRECT_IO_PCIE           3
  5073. #define INDIRECT_IO_PCIEP          4
  5074. #define INDIRECT_IO_NBMISC         5
  5075.  
  5076. #define INDIRECT_IO_PLL_READ       INDIRECT_IO_PLL   | INDIRECT_READ
  5077. #define INDIRECT_IO_PLL_WRITE      INDIRECT_IO_PLL   | INDIRECT_WRITE
  5078. #define INDIRECT_IO_MC_READ        INDIRECT_IO_MC    | INDIRECT_READ
  5079. #define INDIRECT_IO_MC_WRITE       INDIRECT_IO_MC    | INDIRECT_WRITE
  5080. #define INDIRECT_IO_PCIE_READ      INDIRECT_IO_PCIE  | INDIRECT_READ
  5081. #define INDIRECT_IO_PCIE_WRITE     INDIRECT_IO_PCIE  | INDIRECT_WRITE
  5082. #define INDIRECT_IO_PCIEP_READ     INDIRECT_IO_PCIEP | INDIRECT_READ
  5083. #define INDIRECT_IO_PCIEP_WRITE    INDIRECT_IO_PCIEP | INDIRECT_WRITE
  5084. #define INDIRECT_IO_NBMISC_READ    INDIRECT_IO_NBMISC | INDIRECT_READ
  5085. #define INDIRECT_IO_NBMISC_WRITE   INDIRECT_IO_NBMISC | INDIRECT_WRITE
  5086.  
  5087. typedef struct _ATOM_OEM_INFO
  5088. {
  5089.         ATOM_COMMON_TABLE_HEADER sHeader;
  5090.         ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
  5091. }ATOM_OEM_INFO;
  5092.  
  5093. typedef struct _ATOM_TV_MODE
  5094. {
  5095.    UCHAR        ucVMode_Num;                      //Video mode number
  5096.    UCHAR        ucTV_Mode_Num;                  //Internal TV mode number
  5097. }ATOM_TV_MODE;
  5098.  
  5099. typedef struct _ATOM_BIOS_INT_TVSTD_MODE
  5100. {
  5101.   ATOM_COMMON_TABLE_HEADER sHeader;  
  5102.    USHORT       usTV_Mode_LUT_Offset;   // Pointer to standard to internal number conversion table
  5103.    USHORT       usTV_FIFO_Offset;                 // Pointer to FIFO entry table
  5104.    USHORT       usNTSC_Tbl_Offset;              // Pointer to SDTV_Mode_NTSC table
  5105.    USHORT       usPAL_Tbl_Offset;                 // Pointer to SDTV_Mode_PAL table
  5106.    USHORT       usCV_Tbl_Offset;                  // Pointer to SDTV_Mode_PAL table
  5107. }ATOM_BIOS_INT_TVSTD_MODE;
  5108.  
  5109.  
  5110. typedef struct _ATOM_TV_MODE_SCALER_PTR
  5111. {
  5112.    USHORT       ucFilter0_Offset;               //Pointer to filter format 0 coefficients
  5113.    USHORT       usFilter1_Offset;               //Pointer to filter format 0 coefficients
  5114.         UCHAR ucTV_Mode_Num;
  5115. }ATOM_TV_MODE_SCALER_PTR;
  5116.  
  5117. typedef struct _ATOM_STANDARD_VESA_TIMING
  5118. {
  5119.         ATOM_COMMON_TABLE_HEADER sHeader;
  5120.   ATOM_DTD_FORMAT                                aModeTimings[16];      // 16 is not the real array number, just for initial allocation
  5121. }ATOM_STANDARD_VESA_TIMING;
  5122.  
  5123.  
  5124. typedef struct _ATOM_STD_FORMAT
  5125. {
  5126.         USHORT usSTD_HDisp;
  5127.         USHORT usSTD_VDisp;
  5128.         USHORT usSTD_RefreshRate;
  5129.         USHORT usReserved;
  5130. }ATOM_STD_FORMAT;
  5131.  
  5132. typedef struct _ATOM_VESA_TO_EXTENDED_MODE
  5133. {
  5134.         USHORT usVESA_ModeNumber;
  5135.         USHORT usExtendedModeNumber;
  5136. }ATOM_VESA_TO_EXTENDED_MODE;
  5137.  
  5138. typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
  5139. {
  5140.         ATOM_COMMON_TABLE_HEADER sHeader;
  5141.         ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
  5142. }ATOM_VESA_TO_INTENAL_MODE_LUT;
  5143.  
  5144. /*************** ATOM Memory Related Data Structure ***********************/
  5145. typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
  5146.         UCHAR ucMemoryType;
  5147.         UCHAR ucMemoryVendor;
  5148.         UCHAR ucAdjMCId;
  5149.         UCHAR ucDynClkId;
  5150.         ULONG ulDllResetClkRange;
  5151. }ATOM_MEMORY_VENDOR_BLOCK;
  5152.  
  5153.  
  5154. typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
  5155. #if ATOM_BIG_ENDIAN
  5156.         ULONG ucMemBlkId:8;
  5157.         ULONG ulMemClockRange:24;
  5158. #else
  5159.         ULONG ulMemClockRange:24;
  5160.         ULONG ucMemBlkId:8;
  5161. #endif
  5162. }ATOM_MEMORY_SETTING_ID_CONFIG;
  5163.  
  5164. typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
  5165. {
  5166.         ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
  5167.         ULONG ulAccess;
  5168. }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
  5169.  
  5170.  
  5171. typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
  5172.         ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID;
  5173.         ULONG aulMemData[1];
  5174. }ATOM_MEMORY_SETTING_DATA_BLOCK;
  5175.  
  5176.  
  5177. typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
  5178.          USHORT                                                                                 usRegIndex;                                     // MC register index
  5179.          UCHAR                                                                                  ucPreRegDataLength;                             // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
  5180. }ATOM_INIT_REG_INDEX_FORMAT;
  5181.  
  5182.  
  5183. typedef struct _ATOM_INIT_REG_BLOCK{
  5184.         USHORT                                                                                                  usRegIndexTblSize;                                                                                                      //size of asRegIndexBuf
  5185.         USHORT                                                                                                  usRegDataBlkSize;                                                                                                               //size of ATOM_MEMORY_SETTING_DATA_BLOCK
  5186.         ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1];
  5187.         ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1];
  5188. }ATOM_INIT_REG_BLOCK;
  5189.  
  5190. #define END_OF_REG_INDEX_BLOCK  0x0ffff
  5191. #define END_OF_REG_DATA_BLOCK   0x00000000
  5192. #define ATOM_INIT_REG_MASK_FLAG 0x80
  5193. #define CLOCK_RANGE_HIGHEST                     0x00ffffff
  5194.  
  5195. #define VALUE_DWORD             SIZEOF ULONG
  5196. #define VALUE_SAME_AS_ABOVE     0
  5197. #define VALUE_MASK_DWORD        0x84
  5198.  
  5199. #define INDEX_ACCESS_RANGE_BEGIN            (VALUE_DWORD + 1)
  5200. #define INDEX_ACCESS_RANGE_END              (INDEX_ACCESS_RANGE_BEGIN + 1)
  5201. #define VALUE_INDEX_ACCESS_SINGLE           (INDEX_ACCESS_RANGE_END + 1)
  5202. //#define ACCESS_MCIODEBUGIND            0x40       //defined in BIOS code
  5203. #define ACCESS_PLACEHOLDER             0x80
  5204.  
  5205. typedef struct _ATOM_MC_INIT_PARAM_TABLE
  5206. {
  5207.         ATOM_COMMON_TABLE_HEADER sHeader;
  5208.         USHORT usAdjustARB_SEQDataOffset;
  5209.         USHORT usMCInitMemTypeTblOffset;
  5210.         USHORT usMCInitCommonTblOffset;
  5211.         USHORT usMCInitPowerDownTblOffset;
  5212.         ULONG ulARB_SEQDataBuf[32];
  5213.         ATOM_INIT_REG_BLOCK asMCInitMemType;
  5214.         ATOM_INIT_REG_BLOCK asMCInitCommon;
  5215. }ATOM_MC_INIT_PARAM_TABLE;
  5216.  
  5217.  
  5218. #define _4Mx16              0x2
  5219. #define _4Mx32              0x3
  5220. #define _8Mx16              0x12
  5221. #define _8Mx32              0x13
  5222. #define _16Mx16             0x22
  5223. #define _16Mx32             0x23
  5224. #define _32Mx16             0x32
  5225. #define _32Mx32             0x33
  5226. #define _64Mx8              0x41
  5227. #define _64Mx16             0x42
  5228. #define _64Mx32             0x43
  5229. #define _128Mx8             0x51
  5230. #define _128Mx16            0x52
  5231. #define _256Mx8             0x61
  5232.  
  5233. #define SAMSUNG             0x1
  5234. #define INFINEON            0x2
  5235. #define ELPIDA              0x3
  5236. #define ETRON               0x4
  5237. #define NANYA               0x5
  5238. #define HYNIX               0x6
  5239. #define MOSEL               0x7
  5240. #define WINBOND             0x8
  5241. #define ESMT                0x9
  5242. #define MICRON              0xF
  5243.  
  5244. #define QIMONDA             INFINEON
  5245. #define PROMOS              MOSEL
  5246. #define KRETON              INFINEON
  5247. #define ELIXIR              NANYA
  5248.  
  5249. /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
  5250.  
  5251. #define UCODE_ROM_START_ADDRESS         0x1b800
  5252. #define UCODE_SIGNATURE                 0x4375434d // 'MCuC' - MC uCode
  5253.  
  5254. //uCode block header for reference
  5255.  
  5256. typedef struct _MCuCodeHeader
  5257. {
  5258.         ULONG ulSignature;
  5259.         UCHAR ucRevision;
  5260.         UCHAR ucChecksum;
  5261.         UCHAR ucReserved1;
  5262.         UCHAR ucReserved2;
  5263.         USHORT usParametersLength;
  5264.         USHORT usUCodeLength;
  5265.         USHORT usReserved1;
  5266.         USHORT usReserved2;
  5267. } MCuCodeHeader;
  5268.  
  5269. //////////////////////////////////////////////////////////////////////////////////
  5270.  
  5271. #define ATOM_MAX_NUMBER_OF_VRAM_MODULE  16
  5272.  
  5273. #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK  0xF
  5274. typedef struct _ATOM_VRAM_MODULE_V1
  5275. {
  5276.         ULONG ulReserved;
  5277.         USHORT usEMRSValue;
  5278.         USHORT usMRSValue;
  5279.         USHORT usReserved;
  5280.   UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  5281.   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
  5282.   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender
  5283.   UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
  5284.   UCHAR                      ucRow;             // Number of Row,in power of 2;
  5285.   UCHAR                      ucColumn;          // Number of Column,in power of 2;
  5286.   UCHAR                      ucBank;            // Nunber of Bank;
  5287.   UCHAR                      ucRank;            // Number of Rank, in power of 2
  5288.   UCHAR                      ucChannelNum;      // Number of channel;
  5289.   UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
  5290.   UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
  5291.   UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
  5292.         UCHAR ucReserved[2];
  5293. }ATOM_VRAM_MODULE_V1;
  5294.  
  5295.  
  5296. typedef struct _ATOM_VRAM_MODULE_V2
  5297. {
  5298.         ULONG ulReserved;
  5299.   ULONG                      ulFlags;                           // To enable/disable functionalities based on memory type
  5300.   ULONG                      ulEngineClock;     // Override of default engine clock for particular memory type
  5301.   ULONG                      ulMemoryClock;     // Override of default memory clock for particular memory type
  5302.   USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  5303.   USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  5304.         USHORT usEMRSValue;
  5305.         USHORT usMRSValue;
  5306.         USHORT usReserved;
  5307.   UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  5308.   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
  5309.   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
  5310.   UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
  5311.   UCHAR                      ucRow;             // Number of Row,in power of 2;
  5312.   UCHAR                      ucColumn;          // Number of Column,in power of 2;
  5313.   UCHAR                      ucBank;            // Nunber of Bank;
  5314.   UCHAR                      ucRank;            // Number of Rank, in power of 2
  5315.   UCHAR                      ucChannelNum;      // Number of channel;
  5316.   UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
  5317.   UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
  5318.   UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
  5319.         UCHAR ucRefreshRateFactor;
  5320.         UCHAR ucReserved[3];
  5321. }ATOM_VRAM_MODULE_V2;
  5322.  
  5323.  
  5324. typedef struct _ATOM_MEMORY_TIMING_FORMAT
  5325. {
  5326.         ULONG                                                                                    ulClkRange;                            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing    
  5327.   union{
  5328.           USHORT                                                                                 usMRS;                                                 // mode register                                               
  5329.                 USHORT usDDR3_MR0;
  5330.         };
  5331.   union{
  5332.           USHORT                                                                                 usEMRS;                                                // extended mode register
  5333.                 USHORT usDDR3_MR1;
  5334.         };
  5335.         UCHAR                                                                                    ucCL;                                                  // CAS latency
  5336.         UCHAR                                                                                    ucWL;                                                  // WRITE Latency                               
  5337.         UCHAR                                                                                    uctRAS;                                                // tRAS
  5338.         UCHAR                                                                                    uctRC;                                                 // tRC 
  5339.         UCHAR                                                                                    uctRFC;                                                // tRFC
  5340.         UCHAR                                                                                    uctRCDR;                                               // tRCDR       
  5341.         UCHAR                                                                                    uctRCDW;                                               // tRCDW
  5342.         UCHAR                                                                                    uctRP;                                                 // tRP
  5343.         UCHAR                                                                                    uctRRD;                                                // tRRD
  5344.         UCHAR                                                                                    uctWR;                                                 // tWR
  5345.         UCHAR                                                                                    uctWTR;                                                // tWTR
  5346.         UCHAR                                                                                    uctPDIX;                                               // tPDIX
  5347.         UCHAR                                                                                    uctFAW;                                                // tFAW
  5348.         UCHAR                                                                                    uctAOND;                                               // tAOND
  5349.   union
  5350.   {
  5351.                 struct {
  5352.             UCHAR                                                                                        ucflag;                                                // flag to control memory timing calculation. bit0= control EMRS2 Infineon
  5353.                         UCHAR ucReserved;
  5354.                 };
  5355.                 USHORT usDDR3_MR2;
  5356.         };
  5357. }ATOM_MEMORY_TIMING_FORMAT;
  5358.  
  5359.  
  5360. typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1
  5361. {
  5362.         ULONG                                                                                    ulClkRange;                            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing    
  5363.         USHORT                                                                           usMRS;                                                 // mode register                                               
  5364.         USHORT                                                                           usEMRS;                                                // extended mode register
  5365.         UCHAR                                                                                    ucCL;                                                  // CAS latency
  5366.         UCHAR                                                                                    ucWL;                                                  // WRITE Latency                               
  5367.         UCHAR                                                                                    uctRAS;                                                // tRAS
  5368.         UCHAR                                                                                    uctRC;                                                 // tRC 
  5369.         UCHAR                                                                                    uctRFC;                                                // tRFC
  5370.         UCHAR                                                                                    uctRCDR;                                               // tRCDR       
  5371.         UCHAR                                                                                    uctRCDW;                                               // tRCDW
  5372.         UCHAR                                                                                    uctRP;                                                 // tRP
  5373.         UCHAR                                                                                    uctRRD;                                                // tRRD
  5374.         UCHAR                                                                                    uctWR;                                                 // tWR
  5375.         UCHAR                                                                                    uctWTR;                                                // tWTR
  5376.         UCHAR                                                                                    uctPDIX;                                               // tPDIX
  5377.         UCHAR                                                                                    uctFAW;                                                // tFAW
  5378.         UCHAR                                                                                    uctAOND;                                               // tAOND
  5379.         UCHAR                                                                                    ucflag;                                                // flag to control memory timing calculation. bit0= control EMRS2 Infineon
  5380. ////////////////////////////////////GDDR parameters///////////////////////////////////
  5381.         UCHAR                                                                                    uctCCDL;                                               //
  5382.         UCHAR                                                                                    uctCRCRL;                                              //
  5383.         UCHAR                                                                                    uctCRCWL;                                              //
  5384.         UCHAR                                                                                    uctCKE;                                                //
  5385.         UCHAR                                                                                    uctCKRSE;                                              //
  5386.         UCHAR                                                                                    uctCKRSX;                                              //
  5387.         UCHAR                                                                                    uctFAW32;                                              //
  5388.         UCHAR                                                                                    ucMR5lo;                                       //
  5389.         UCHAR                                                                                    ucMR5hi;                                       //
  5390.         UCHAR                                                                                    ucTerminator;
  5391. }ATOM_MEMORY_TIMING_FORMAT_V1;
  5392.  
  5393. typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2
  5394. {
  5395.         ULONG                                                                                    ulClkRange;                            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing    
  5396.         USHORT                                                                           usMRS;                                                 // mode register                                               
  5397.         USHORT                                                                           usEMRS;                                                // extended mode register
  5398.         UCHAR                                                                                    ucCL;                                                  // CAS latency
  5399.         UCHAR                                                                                    ucWL;                                                  // WRITE Latency                               
  5400.         UCHAR                                                                                    uctRAS;                                                // tRAS
  5401.         UCHAR                                                                                    uctRC;                                                 // tRC 
  5402.         UCHAR                                                                                    uctRFC;                                                // tRFC
  5403.         UCHAR                                                                                    uctRCDR;                                               // tRCDR       
  5404.         UCHAR                                                                                    uctRCDW;                                               // tRCDW
  5405.         UCHAR                                                                                    uctRP;                                                 // tRP
  5406.         UCHAR                                                                                    uctRRD;                                                // tRRD
  5407.         UCHAR                                                                                    uctWR;                                                 // tWR
  5408.         UCHAR                                                                                    uctWTR;                                                // tWTR
  5409.         UCHAR                                                                                    uctPDIX;                                               // tPDIX
  5410.         UCHAR                                                                                    uctFAW;                                                // tFAW
  5411.         UCHAR                                                                                    uctAOND;                                               // tAOND
  5412.         UCHAR                                                                                    ucflag;                                                // flag to control memory timing calculation. bit0= control EMRS2 Infineon
  5413. ////////////////////////////////////GDDR parameters///////////////////////////////////
  5414.         UCHAR                                                                                    uctCCDL;                                               //
  5415.         UCHAR                                                                                    uctCRCRL;                                              //
  5416.         UCHAR                                                                                    uctCRCWL;                                              //
  5417.         UCHAR                                                                                    uctCKE;                                                //
  5418.         UCHAR                                                                                    uctCKRSE;                                              //
  5419.         UCHAR                                                                                    uctCKRSX;                                              //
  5420.         UCHAR                                                                                    uctFAW32;                                              //
  5421.         UCHAR                                                                                    ucMR4lo;                                       //
  5422.         UCHAR                                                                                    ucMR4hi;                                       //
  5423.         UCHAR                                                                                    ucMR5lo;                                       //
  5424.         UCHAR                                                                                    ucMR5hi;                                       //
  5425.         UCHAR ucTerminator;
  5426.         UCHAR                                                                                    ucReserved;   
  5427. }ATOM_MEMORY_TIMING_FORMAT_V2;
  5428.  
  5429. typedef struct _ATOM_MEMORY_FORMAT
  5430. {
  5431.         ULONG                                                                                    ulDllDisClock;                 // memory DLL will be disable when target memory clock is below this clock
  5432.   union{
  5433.     USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  5434.     USHORT                     usDDR3_Reserved;   // Not used for DDR3 memory
  5435.         };
  5436.   union{
  5437.     USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  5438.     USHORT                     usDDR3_MR3;        // Used for DDR3 memory
  5439.         };
  5440.   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
  5441.   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
  5442.   UCHAR                      ucRow;             // Number of Row,in power of 2;
  5443.   UCHAR                      ucColumn;          // Number of Column,in power of 2;
  5444.   UCHAR                      ucBank;            // Nunber of Bank;
  5445.   UCHAR                      ucRank;            // Number of Rank, in power of 2
  5446.         UCHAR                                                                                    ucBurstSize;                           // burst size, 0= burst size=4  1= burst size=8
  5447.   UCHAR                      ucDllDisBit;                               // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
  5448.   UCHAR                      ucRefreshRateFactor;       // memory refresh rate in unit of ms   
  5449.         UCHAR                                                                                    ucDensity;                                     // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  5450.         UCHAR                                                                                    ucPreamble;                            //[7:4] Write Preamble, [3:0] Read Preamble
  5451.   UCHAR                                                                                  ucMemAttrib;                           // Memory Device Addribute, like RDBI/WDBI etc
  5452.         ATOM_MEMORY_TIMING_FORMAT        asMemTiming[5];                //Memory Timing block sort from lower clock to higher clock
  5453. }ATOM_MEMORY_FORMAT;
  5454.  
  5455.  
  5456. typedef struct _ATOM_VRAM_MODULE_V3
  5457. {
  5458.         ULONG                                                                                    ulChannelMapCfg;               // board dependent paramenter:Channel combination
  5459.         USHORT                                                                           usSize;                                                // size of ATOM_VRAM_MODULE_V3
  5460.   USHORT                     usDefaultMVDDQ;            // board dependent parameter:Default Memory Core Voltage
  5461.   USHORT                     usDefaultMVDDC;            // board dependent parameter:Default Memory IO Voltage
  5462.         UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  5463.   UCHAR                      ucChannelNum;      // board dependent parameter:Number of channel;
  5464.         UCHAR                                                                                    ucChannelSize;                 // board dependent parameter:32bit or 64bit    
  5465.         UCHAR                                                                                    ucVREFI;                                               // board dependnt parameter: EXT or INT +160mv to -140mv
  5466.         UCHAR                                                                                    ucNPL_RT;                                      // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
  5467.         UCHAR                                                                                    ucFlag;                                                // To enable/disable functionalities based on memory type
  5468.         ATOM_MEMORY_FORMAT                               asMemory;                                      // describ all of video memory parameters from memory spec
  5469. }ATOM_VRAM_MODULE_V3;
  5470.  
  5471.  
  5472. //ATOM_VRAM_MODULE_V3.ucNPL_RT
  5473. #define NPL_RT_MASK                                                                                                                     0x0f
  5474. #define BATTERY_ODT_MASK                                                                                                0xc0
  5475.  
  5476. #define ATOM_VRAM_MODULE                 ATOM_VRAM_MODULE_V3
  5477.  
  5478. typedef struct _ATOM_VRAM_MODULE_V4
  5479. {
  5480.   ULONG   ulChannelMapCfg;                      // board dependent parameter: Channel combination
  5481.   USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
  5482.   USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  5483.                                             // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
  5484.         USHORT usReserved;
  5485.   UCHAR   ucExtMemoryID;                            // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  5486.   UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
  5487.   UCHAR   ucChannelNum;                     // Number of channels present in this module config
  5488.   UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
  5489.         UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  5490.         UCHAR     ucFlag;                                                               // To enable/disable functionalities based on memory type
  5491.         UCHAR     ucMisc;                                                               // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
  5492.   UCHAR         ucVREFI;                          // board dependent parameter
  5493.   UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
  5494.   UCHAR         ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
  5495.   UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  5496.                                             // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
  5497.         UCHAR ucReserved[3];
  5498.  
  5499. //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
  5500.   union{
  5501.     USHORT      usEMRS2Value;                   // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  5502.                 USHORT usDDR3_Reserved;
  5503.         };
  5504.   union{
  5505.     USHORT      usEMRS3Value;                   // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  5506.     USHORT  usDDR3_MR3;                     // Used for DDR3 memory
  5507.         };
  5508.   UCHAR   ucMemoryVenderID;                         // Predefined, If not predefined, vendor detection table gets executed
  5509.   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
  5510.         UCHAR ucReserved2[2];
  5511.   ATOM_MEMORY_TIMING_FORMAT  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
  5512. }ATOM_VRAM_MODULE_V4;
  5513.  
  5514. #define VRAM_MODULE_V4_MISC_RANK_MASK       0x3
  5515. #define VRAM_MODULE_V4_MISC_DUAL_RANK       0x1
  5516. #define VRAM_MODULE_V4_MISC_BL_MASK         0x4
  5517. #define VRAM_MODULE_V4_MISC_BL8             0x4
  5518. #define VRAM_MODULE_V4_MISC_DUAL_CS         0x10
  5519.  
  5520. typedef struct _ATOM_VRAM_MODULE_V5
  5521. {
  5522.   ULONG   ulChannelMapCfg;                      // board dependent parameter: Channel combination
  5523.   USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
  5524.   USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  5525.                                             // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
  5526.   USHORT  usReserved;
  5527.   UCHAR   ucExtMemoryID;                            // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  5528.   UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
  5529.   UCHAR   ucChannelNum;                     // Number of channels present in this module config
  5530.   UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
  5531.         UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  5532.         UCHAR     ucFlag;                                                               // To enable/disable functionalities based on memory type
  5533.         UCHAR     ucMisc;                                                               // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
  5534.   UCHAR         ucVREFI;                          // board dependent parameter
  5535.   UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
  5536.   UCHAR         ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
  5537.   UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  5538.                                             // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
  5539.   UCHAR   ucReserved[3];
  5540.  
  5541. //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
  5542.   USHORT        usEMRS2Value;                               // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  5543.   USHORT        usEMRS3Value;                               // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  5544.   UCHAR   ucMemoryVenderID;                         // Predefined, If not predefined, vendor detection table gets executed
  5545.   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
  5546.   UCHAR   ucFIFODepth;                                  // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
  5547.   UCHAR   ucCDR_Bandwidth;                 // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
  5548.   ATOM_MEMORY_TIMING_FORMAT_V1  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
  5549. }ATOM_VRAM_MODULE_V5;
  5550.  
  5551. typedef struct _ATOM_VRAM_MODULE_V6
  5552. {
  5553.   ULONG   ulChannelMapCfg;                      // board dependent parameter: Channel combination
  5554.   USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
  5555.   USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  5556.                                             // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
  5557.         USHORT usReserved;
  5558.   UCHAR   ucExtMemoryID;                            // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
  5559.   UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
  5560.   UCHAR   ucChannelNum;                     // Number of channels present in this module config
  5561.   UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
  5562.         UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  5563.         UCHAR     ucFlag;                                                               // To enable/disable functionalities based on memory type
  5564.         UCHAR     ucMisc;                                                               // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
  5565.   UCHAR         ucVREFI;                          // board dependent parameter
  5566.   UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
  5567.   UCHAR         ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
  5568.   UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
  5569.                                             // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
  5570.         UCHAR ucReserved[3];
  5571.  
  5572. //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
  5573.   USHORT        usEMRS2Value;                               // EMRS2 Value is used for GDDR2 and GDDR4 memory type
  5574.   USHORT        usEMRS3Value;                               // EMRS3 Value is used for GDDR2 and GDDR4 memory type
  5575.   UCHAR   ucMemoryVenderID;                         // Predefined, If not predefined, vendor detection table gets executed
  5576.   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
  5577.   UCHAR   ucFIFODepth;                                  // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
  5578.   UCHAR   ucCDR_Bandwidth;                 // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
  5579.   ATOM_MEMORY_TIMING_FORMAT_V2  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
  5580. }ATOM_VRAM_MODULE_V6;
  5581.  
  5582. typedef struct _ATOM_VRAM_MODULE_V7
  5583. {
  5584. // Design Specific Values
  5585.   ULONG   ulChannelMapCfg;                      // mmMC_SHARED_CHREMAP
  5586.   USHORT  usModuleSize;                     // Size of ATOM_VRAM_MODULE_V7
  5587.   USHORT  usPrivateReserved;                // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
  5588.   USHORT  usReserved;
  5589.   UCHAR   ucExtMemoryID;                    // Current memory module ID
  5590.   UCHAR   ucMemoryType;                     // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
  5591.   UCHAR   ucChannelNum;                     // Number of mem. channels supported in this module
  5592.   UCHAR   ucChannelWidth;                   // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
  5593.   UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
  5594.   UCHAR   ucReserve;                        // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now.
  5595.   UCHAR   ucMisc;                           // RANK_OF_THISMEMORY etc.
  5596.   UCHAR   ucVREFI;                          // Not used.
  5597.   UCHAR   ucNPL_RT;                         // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
  5598.   UCHAR   ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
  5599.   UCHAR   ucMemorySize;                     // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
  5600.   UCHAR   ucReserved[3];
  5601. // Memory Module specific values
  5602.   USHORT  usEMRS2Value;                     // EMRS2/MR2 Value.
  5603.   USHORT  usEMRS3Value;                     // EMRS3/MR3 Value.
  5604.   UCHAR   ucMemoryVenderID;                 // [7:4] Revision, [3:0] Vendor code
  5605.   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
  5606.   UCHAR   ucFIFODepth;                      // FIFO depth can be detected during vendor detection, here is hardcoded per memory
  5607.   UCHAR   ucCDR_Bandwidth;                  // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
  5608.   char    strMemPNString[20];               // part number end with '0'.
  5609. }ATOM_VRAM_MODULE_V7;
  5610.  
  5611. typedef struct _ATOM_VRAM_INFO_V2
  5612. {
  5613.         ATOM_COMMON_TABLE_HEADER sHeader;
  5614.         UCHAR ucNumOfVRAMModule;
  5615.   ATOM_VRAM_MODULE           aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
  5616. }ATOM_VRAM_INFO_V2;
  5617.  
  5618. typedef struct _ATOM_VRAM_INFO_V3
  5619. {
  5620.         ATOM_COMMON_TABLE_HEADER sHeader;
  5621.         USHORT                                                                           usMemAdjustTblOffset;                                                                                                   // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
  5622.         USHORT                                                                           usMemClkPatchTblOffset;                                                                                                 //     offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
  5623.         USHORT usRerseved;
  5624.         UCHAR                            aVID_PinsShift[9];                                                                                                                      // 8 bit strap maximum+terminator
  5625.         UCHAR ucNumOfVRAMModule;
  5626.   ATOM_VRAM_MODULE                     aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
  5627.         ATOM_INIT_REG_BLOCK                              asMemPatch;                                                                                                                                             // for allocation
  5628.                                                                                                                                                                                                                                                                                                                  //     ATOM_INIT_REG_BLOCK                              aMemAdjust;
  5629. }ATOM_VRAM_INFO_V3;
  5630.  
  5631. #define ATOM_VRAM_INFO_LAST          ATOM_VRAM_INFO_V3
  5632.  
  5633. typedef struct _ATOM_VRAM_INFO_V4
  5634. {
  5635.         ATOM_COMMON_TABLE_HEADER sHeader;
  5636.         USHORT                                                                           usMemAdjustTblOffset;                                                                                                   // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
  5637.         USHORT                                                                           usMemClkPatchTblOffset;                                                                                                 //     offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
  5638.         USHORT usRerseved;
  5639.         UCHAR                            ucMemDQ7_0ByteRemap;                                                                                                      // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
  5640.   ULONG                      ulMemDQ7_0BitRemap;                             // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
  5641.         UCHAR ucReservde[4];
  5642.         UCHAR ucNumOfVRAMModule;
  5643.   ATOM_VRAM_MODULE_V4                aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
  5644.         ATOM_INIT_REG_BLOCK                              asMemPatch;                                                                                                                                             // for allocation
  5645.                                                                                                                                                                                                                                                                                                                  //     ATOM_INIT_REG_BLOCK                              aMemAdjust;
  5646. }ATOM_VRAM_INFO_V4;
  5647.  
  5648. typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
  5649. {
  5650.   ATOM_COMMON_TABLE_HEADER   sHeader;
  5651.         USHORT                                                                           usMemAdjustTblOffset;                                                                                                   // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
  5652.         USHORT                                                                           usMemClkPatchTblOffset;                                                                                                 //     offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
  5653.         USHORT                                                                           usReserved[4];
  5654.   UCHAR                      ucNumOfVRAMModule;                              // indicate number of VRAM module
  5655.   UCHAR                      ucMemoryClkPatchTblVer;                         // version of memory AC timing register list
  5656.   UCHAR                      ucVramModuleVer;                                // indicate ATOM_VRAM_MODUE version
  5657.   UCHAR                      ucReserved;
  5658.   ATOM_VRAM_MODULE_V7                aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
  5659. }ATOM_VRAM_INFO_HEADER_V2_1;
  5660.  
  5661.  
  5662. typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
  5663. {
  5664.         ATOM_COMMON_TABLE_HEADER sHeader;
  5665.   UCHAR                          aVID_PinsShift[9];   //8 bit strap maximum+terminator
  5666. }ATOM_VRAM_GPIO_DETECTION_INFO;
  5667.  
  5668.  
  5669. typedef struct _ATOM_MEMORY_TRAINING_INFO
  5670. {
  5671.         ATOM_COMMON_TABLE_HEADER sHeader;
  5672.         UCHAR ucTrainingLoop;
  5673.         UCHAR ucReserved[3];
  5674.         ATOM_INIT_REG_BLOCK asMemTrainingSetting;
  5675. }ATOM_MEMORY_TRAINING_INFO;
  5676.  
  5677.  
  5678. typedef struct SW_I2C_CNTL_DATA_PARAMETERS
  5679. {
  5680.         UCHAR ucControl;
  5681.         UCHAR ucData;
  5682.         UCHAR ucSatus;
  5683.         UCHAR ucTemp;
  5684. } SW_I2C_CNTL_DATA_PARAMETERS;
  5685.  
  5686. #define SW_I2C_CNTL_DATA_PS_ALLOCATION  SW_I2C_CNTL_DATA_PARAMETERS
  5687.  
  5688. typedef struct _SW_I2C_IO_DATA_PARAMETERS
  5689. {                              
  5690.         USHORT GPIO_Info;
  5691.         UCHAR ucAct;
  5692.         UCHAR ucData;
  5693.  } SW_I2C_IO_DATA_PARAMETERS;
  5694.  
  5695. #define SW_I2C_IO_DATA_PS_ALLOCATION  SW_I2C_IO_DATA_PARAMETERS
  5696.  
  5697. /****************************SW I2C CNTL DEFINITIONS**********************/
  5698. #define SW_I2C_IO_RESET       0
  5699. #define SW_I2C_IO_GET         1
  5700. #define SW_I2C_IO_DRIVE       2
  5701. #define SW_I2C_IO_SET         3
  5702. #define SW_I2C_IO_START       4
  5703.  
  5704. #define SW_I2C_IO_CLOCK       0
  5705. #define SW_I2C_IO_DATA        0x80
  5706.  
  5707. #define SW_I2C_IO_ZERO        0
  5708. #define SW_I2C_IO_ONE         0x100
  5709.  
  5710. #define SW_I2C_CNTL_READ      0
  5711. #define SW_I2C_CNTL_WRITE     1
  5712. #define SW_I2C_CNTL_START     2
  5713. #define SW_I2C_CNTL_STOP      3
  5714. #define SW_I2C_CNTL_OPEN      4
  5715. #define SW_I2C_CNTL_CLOSE     5
  5716. #define SW_I2C_CNTL_WRITE1BIT 6
  5717.  
  5718. //==============================VESA definition Portion===============================
  5719. #define VESA_OEM_PRODUCT_REV                                "01.00"
  5720. #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT             0xBB       //refer to VBE spec p.32, no TTY support
  5721. #define VESA_MODE_WIN_ATTRIBUTE                                              7
  5722. #define VESA_WIN_SIZE                                                                                        64
  5723.  
  5724. typedef struct _PTR_32_BIT_STRUCTURE
  5725. {
  5726.         USHORT Offset16;
  5727.         USHORT Segment16;
  5728. } PTR_32_BIT_STRUCTURE;
  5729.  
  5730. typedef union _PTR_32_BIT_UNION
  5731. {
  5732.         PTR_32_BIT_STRUCTURE SegmentOffset;
  5733.         ULONG Ptr32_Bit;
  5734. } PTR_32_BIT_UNION;
  5735.  
  5736. typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
  5737. {
  5738.         UCHAR VbeSignature[4];
  5739.         USHORT VbeVersion;
  5740.         PTR_32_BIT_UNION OemStringPtr;
  5741.         UCHAR Capabilities[4];
  5742.         PTR_32_BIT_UNION VideoModePtr;
  5743.         USHORT TotalMemory;
  5744. } VBE_1_2_INFO_BLOCK_UPDATABLE;
  5745.  
  5746.  
  5747. typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
  5748. {
  5749.         VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock;
  5750.         USHORT OemSoftRev;
  5751.         PTR_32_BIT_UNION OemVendorNamePtr;
  5752.         PTR_32_BIT_UNION OemProductNamePtr;
  5753.         PTR_32_BIT_UNION OemProductRevPtr;
  5754. } VBE_2_0_INFO_BLOCK_UPDATABLE;
  5755.  
  5756. typedef union _VBE_VERSION_UNION
  5757. {
  5758.         VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock;
  5759.         VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock;
  5760. } VBE_VERSION_UNION;
  5761.  
  5762. typedef struct _VBE_INFO_BLOCK
  5763. {
  5764.         VBE_VERSION_UNION UpdatableVBE_Info;
  5765.         UCHAR Reserved[222];
  5766.         UCHAR OemData[256];
  5767. } VBE_INFO_BLOCK;
  5768.  
  5769. typedef struct _VBE_FP_INFO
  5770. {
  5771.         USHORT HSize;
  5772.         USHORT VSize;
  5773.         USHORT FPType;
  5774.         UCHAR RedBPP;
  5775.         UCHAR GreenBPP;
  5776.         UCHAR BlueBPP;
  5777.         UCHAR ReservedBPP;
  5778.         ULONG RsvdOffScrnMemSize;
  5779.         ULONG RsvdOffScrnMEmPtr;
  5780.         UCHAR Reserved[14];
  5781. } VBE_FP_INFO;
  5782.  
  5783. typedef struct _VESA_MODE_INFO_BLOCK
  5784. {
  5785. // Mandatory information for all VBE revisions
  5786.   USHORT    ModeAttributes;  //                 dw      ?       ; mode attributes
  5787.         UCHAR     WinAAttributes;  //                   db      ?       ; window A attributes
  5788.         UCHAR     WinBAttributes;  //                   db      ?       ; window B attributes
  5789.         USHORT    WinGranularity;  //                   dw      ?       ; window granularity
  5790.         USHORT    WinSize;         //                   dw      ?       ; window size
  5791.         USHORT    WinASegment;     //                   dw      ?       ; window A start segment
  5792.         USHORT    WinBSegment;     //                   dw      ?       ; window B start segment
  5793.         ULONG     WinFuncPtr;      //                   dd      ?       ; real mode pointer to window function
  5794.         USHORT    BytesPerScanLine;//                   dw      ?       ; bytes per scan line
  5795.  
  5796. //; Mandatory information for VBE 1.2 and above
  5797.   USHORT    XResolution;      //                        dw      ?       ; horizontal resolution in pixels or characters
  5798.         USHORT    YResolution;      //                  dw      ?       ; vertical resolution in pixels or characters
  5799.         UCHAR     XCharSize;        //                  db      ?       ; character cell width in pixels
  5800.         UCHAR     YCharSize;        //                  db      ?       ; character cell height in pixels
  5801.         UCHAR     NumberOfPlanes;   //                  db      ?       ; number of memory planes
  5802.         UCHAR     BitsPerPixel;     //                  db      ?       ; bits per pixel
  5803.         UCHAR     NumberOfBanks;    //                  db      ?       ; number of banks
  5804.         UCHAR     MemoryModel;      //                  db      ?       ; memory model type
  5805.         UCHAR     BankSize;         //                  db      ?       ; bank size in KB
  5806.         UCHAR     NumberOfImagePages;//           db    ?       ; number of images
  5807.         UCHAR     ReservedForPageFunction;//db  1       ; reserved for page function
  5808.  
  5809. //; Direct Color fields(required for direct/6 and YUV/7 memory models)
  5810.         UCHAR                   RedMaskSize;        //          db      ?       ; size of direct color red mask in bits
  5811.         UCHAR                   RedFieldPosition;   //          db      ?       ; bit position of lsb of red mask
  5812.         UCHAR                   GreenMaskSize;      //          db      ?       ; size of direct color green mask in bits
  5813.         UCHAR                   GreenFieldPosition; //          db      ?       ; bit position of lsb of green mask
  5814.         UCHAR                   BlueMaskSize;       //          db      ?       ; size of direct color blue mask in bits
  5815.         UCHAR                   BlueFieldPosition;  //          db      ?       ; bit position of lsb of blue mask
  5816.         UCHAR                   RsvdMaskSize;       //          db      ?       ; size of direct color reserved mask in bits
  5817.         UCHAR                   RsvdFieldPosition;  //          db      ?       ; bit position of lsb of reserved mask
  5818.         UCHAR                   DirectColorModeInfo;//          db      ?       ; direct color mode attributes
  5819.  
  5820. //; Mandatory information for VBE 2.0 and above
  5821.         ULONG                   PhysBasePtr;        //          dd      ?       ; physical address for flat memory frame buffer
  5822.         ULONG                   Reserved_1;         //          dd      0       ; reserved - always set to 0
  5823.         USHORT          Reserved_2;         //    dw    0       ; reserved - always set to 0
  5824.  
  5825. //; Mandatory information for VBE 3.0 and above
  5826.         USHORT          LinBytesPerScanLine;  //        dw      ?       ; bytes per scan line for linear modes
  5827.         UCHAR                   BnkNumberOfImagePages;//        db      ?       ; number of images for banked modes
  5828.         UCHAR                   LinNumberOfImagPages; //        db      ?       ; number of images for linear modes
  5829.         UCHAR                   LinRedMaskSize;       //        db      ?       ; size of direct color red mask(linear modes)
  5830.         UCHAR                   LinRedFieldPosition;  //        db      ?       ; bit position of lsb of red mask(linear modes)
  5831.         UCHAR                   LinGreenMaskSize;     //        db      ?       ; size of direct color green mask(linear modes)
  5832.         UCHAR                   LinGreenFieldPosition;//        db      ?       ; bit position of lsb of green mask(linear modes)
  5833.         UCHAR                   LinBlueMaskSize;      //        db      ?       ; size of direct color blue mask(linear modes)
  5834.         UCHAR                   LinBlueFieldPosition; //        db      ?       ; bit position of lsb of blue mask(linear modes)
  5835.         UCHAR                   LinRsvdMaskSize;      //        db      ?       ; size of direct color reserved mask(linear modes)
  5836.         UCHAR                   LinRsvdFieldPosition; //        db      ?       ; bit position of lsb of reserved mask(linear modes)
  5837.         ULONG                   MaxPixelClock;        //        dd      ?       ; maximum pixel clock(in Hz) for graphics mode
  5838.         UCHAR                   Reserved;             //        db      190 dup (0)
  5839. } VESA_MODE_INFO_BLOCK;
  5840.  
  5841. // BIOS function CALLS
  5842. #define ATOM_BIOS_EXTENDED_FUNCTION_CODE        0xA0            // ATI Extended Function code
  5843. #define ATOM_BIOS_FUNCTION_COP_MODE             0x00
  5844. #define ATOM_BIOS_FUNCTION_SHORT_QUERY1         0x04
  5845. #define ATOM_BIOS_FUNCTION_SHORT_QUERY2         0x05
  5846. #define ATOM_BIOS_FUNCTION_SHORT_QUERY3         0x06
  5847. #define ATOM_BIOS_FUNCTION_GET_DDC              0x0B
  5848. #define ATOM_BIOS_FUNCTION_ASIC_DSTATE          0x0E
  5849. #define ATOM_BIOS_FUNCTION_DEBUG_PLAY           0x0F
  5850. #define ATOM_BIOS_FUNCTION_STV_STD              0x16
  5851. #define ATOM_BIOS_FUNCTION_DEVICE_DET           0x17
  5852. #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH        0x18
  5853.  
  5854. #define ATOM_BIOS_FUNCTION_PANEL_CONTROL        0x82
  5855. #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET       0x83
  5856. #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH    0x84
  5857. #define ATOM_BIOS_FUNCTION_HW_ICON              0x8A
  5858. #define ATOM_BIOS_FUNCTION_SET_CMOS             0x8B
  5859. #define SUB_FUNCTION_UPDATE_DISPLAY_INFO        0x8000          // Sub function 80
  5860. #define SUB_FUNCTION_UPDATE_EXPANSION_INFO      0x8100          // Sub function 80
  5861.  
  5862. #define ATOM_BIOS_FUNCTION_DISPLAY_INFO         0x8D
  5863. #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF        0x8E
  5864. #define ATOM_BIOS_FUNCTION_VIDEO_STATE          0x8F
  5865. #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE    0x0300          // Sub function 03  
  5866. #define ATOM_SUB_FUNCTION_GET_LIDSTATE          0x0700          // Sub function 7
  5867. #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE  0x1400          // Notify caller the current thermal state
  5868. #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300          // Notify caller the current critical state
  5869. #define ATOM_SUB_FUNCTION_SET_LIDSTATE          0x8500          // Sub function 85
  5870. #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
  5871. #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT    0x9400          // Notify caller that ADC is supported
  5872.      
  5873.  
  5874. #define ATOM_BIOS_FUNCTION_VESA_DPMS            0x4F10          // Set DPMS
  5875. #define ATOM_SUB_FUNCTION_SET_DPMS              0x0001          // BL: Sub function 01
  5876. #define ATOM_SUB_FUNCTION_GET_DPMS              0x0002          // BL: Sub function 02
  5877. #define ATOM_PARAMETER_VESA_DPMS_ON             0x0000          // BH Parameter for DPMS ON.  
  5878. #define ATOM_PARAMETER_VESA_DPMS_STANDBY        0x0100          // BH Parameter for DPMS STANDBY  
  5879. #define ATOM_PARAMETER_VESA_DPMS_SUSPEND        0x0200          // BH Parameter for DPMS SUSPEND
  5880. #define ATOM_PARAMETER_VESA_DPMS_OFF            0x0400          // BH Parameter for DPMS OFF
  5881. #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON      0x0800          // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
  5882.  
  5883. #define ATOM_BIOS_RETURN_CODE_MASK              0x0000FF00L
  5884. #define ATOM_BIOS_REG_HIGH_MASK                 0x0000FF00L
  5885. #define ATOM_BIOS_REG_LOW_MASK                  0x000000FFL
  5886.  
  5887. // structure used for VBIOS only
  5888.  
  5889. //DispOutInfoTable
  5890. typedef struct _ASIC_TRANSMITTER_INFO
  5891. {
  5892.         USHORT usTransmitterObjId;
  5893.         USHORT usSupportDevice;
  5894.         UCHAR ucTransmitterCmdTblId;
  5895.         UCHAR ucConfig;
  5896.         UCHAR  ucEncoderID;                                      //available 1st encoder ( default )
  5897.         UCHAR  ucOptionEncoderID;    //available 2nd encoder ( optional )
  5898.         UCHAR uc2ndEncoderID;
  5899.         UCHAR ucReserved;
  5900. }ASIC_TRANSMITTER_INFO;
  5901.  
  5902. #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE          0x01
  5903. #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE         0x02
  5904. #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK    0xc4
  5905. #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A             0x00
  5906. #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B             0x04
  5907. #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C             0x40
  5908. #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D             0x44
  5909. #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E             0x80
  5910. #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F             0x84
  5911.  
  5912. typedef struct _ASIC_ENCODER_INFO
  5913. {
  5914.         UCHAR ucEncoderID;
  5915.         UCHAR ucEncoderConfig;
  5916.         USHORT usEncoderCmdTblId;
  5917. }ASIC_ENCODER_INFO;
  5918.  
  5919. typedef struct _ATOM_DISP_OUT_INFO
  5920. {
  5921.   ATOM_COMMON_TABLE_HEADER sHeader;  
  5922.         USHORT ptrTransmitterInfo;
  5923.         USHORT ptrEncoderInfo;
  5924.         ASIC_TRANSMITTER_INFO  asTransmitterInfo[1];
  5925.         ASIC_ENCODER_INFO      asEncoderInfo[1];
  5926. }ATOM_DISP_OUT_INFO;
  5927.  
  5928. typedef struct _ATOM_DISP_OUT_INFO_V2
  5929. {
  5930.         ATOM_COMMON_TABLE_HEADER sHeader;
  5931.         USHORT ptrTransmitterInfo;
  5932.         USHORT ptrEncoderInfo;
  5933.   USHORT ptrMainCallParserFar;                  // direct address of main parser call in VBIOS binary.
  5934.         ASIC_TRANSMITTER_INFO asTransmitterInfo[1];
  5935.         ASIC_ENCODER_INFO asEncoderInfo[1];
  5936. }ATOM_DISP_OUT_INFO_V2;
  5937.  
  5938. // DispDevicePriorityInfo
  5939. typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
  5940. {
  5941.         ATOM_COMMON_TABLE_HEADER sHeader;
  5942.         USHORT asDevicePriority[16];
  5943. }ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
  5944.  
  5945. //ProcessAuxChannelTransactionTable
  5946. typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
  5947. {
  5948.         USHORT lpAuxRequest;
  5949.         USHORT lpDataOut;
  5950.         UCHAR ucChannelID;
  5951.         union
  5952.         {
  5953.                 UCHAR ucReplyStatus;
  5954.                 UCHAR ucDelay;
  5955.         };
  5956.         UCHAR ucDataOutLen;
  5957.         UCHAR ucReserved;
  5958. }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
  5959.  
  5960. //ProcessAuxChannelTransactionTable
  5961. typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
  5962. {
  5963.         USHORT  lpAuxRequest;
  5964.         USHORT  lpDataOut;
  5965.         UCHAR           ucChannelID;
  5966.         union
  5967.         {
  5968.   UCHAR   ucReplyStatus;
  5969.         UCHAR   ucDelay;
  5970.         };
  5971.   UCHAR   ucDataOutLen;
  5972.         UCHAR   ucHPD_ID;                                       //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
  5973. }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
  5974.  
  5975. #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION                   PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
  5976.  
  5977. //GetSinkType
  5978.  
  5979. typedef struct _DP_ENCODER_SERVICE_PARAMETERS
  5980. {
  5981.         USHORT ucLinkClock;
  5982.         union
  5983.         {
  5984.         UCHAR ucConfig;                         // for DP training command
  5985.         UCHAR ucI2cId;                          // use for GET_SINK_TYPE command
  5986.         };
  5987.         UCHAR ucAction;
  5988.         UCHAR ucStatus;
  5989.         UCHAR ucLaneNum;
  5990.         UCHAR ucReserved[2];
  5991. }DP_ENCODER_SERVICE_PARAMETERS;
  5992.  
  5993. // ucAction
  5994. #define ATOM_DP_ACTION_GET_SINK_TYPE                                                    0x01
  5995. /* obselete */
  5996. #define ATOM_DP_ACTION_TRAINING_START                                                   0x02
  5997. #define ATOM_DP_ACTION_TRAINING_COMPLETE                                        0x03
  5998. #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL                             0x04
  5999. #define ATOM_DP_ACTION_SET_VSWING_PREEMP                                        0x05
  6000. #define ATOM_DP_ACTION_GET_VSWING_PREEMP                                        0x06
  6001. #define ATOM_DP_ACTION_BLANKING                   0x07
  6002.  
  6003. // ucConfig
  6004. #define ATOM_DP_CONFIG_ENCODER_SEL_MASK                                         0x03
  6005. #define ATOM_DP_CONFIG_DIG1_ENCODER                                                             0x00
  6006. #define ATOM_DP_CONFIG_DIG2_ENCODER                                                             0x01
  6007. #define ATOM_DP_CONFIG_EXTERNAL_ENCODER                                         0x02
  6008. #define ATOM_DP_CONFIG_LINK_SEL_MASK                                                    0x04
  6009. #define ATOM_DP_CONFIG_LINK_A                                                                                   0x00
  6010. #define ATOM_DP_CONFIG_LINK_B                                                                                   0x04
  6011. /* /obselete */
  6012. #define DP_ENCODER_SERVICE_PS_ALLOCATION                                WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
  6013.  
  6014.  
  6015. typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2
  6016. {
  6017.         USHORT usExtEncoderObjId;   // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
  6018.   UCHAR  ucAuxId;
  6019.   UCHAR  ucAction;
  6020.   UCHAR  ucSinkType;          // Iput and Output parameters.
  6021.   UCHAR  ucHPDId;             // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
  6022.         UCHAR  ucReserved[2];
  6023. }DP_ENCODER_SERVICE_PARAMETERS_V2;
  6024.  
  6025. typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
  6026. {
  6027.   DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;
  6028.   PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;
  6029. }DP_ENCODER_SERVICE_PS_ALLOCATION_V2;
  6030.  
  6031. // ucAction
  6032. #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE                                                      0x01
  6033. #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION                     0x02
  6034.  
  6035.  
  6036. // DP_TRAINING_TABLE
  6037. #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR                             ATOM_DP_TRAINING_TBL_ADDR
  6038. #define DPCD_SET_SS_CNTL_TBL_ADDR                                                                                                       (ATOM_DP_TRAINING_TBL_ADDR + 8 )
  6039. #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR                                                    (ATOM_DP_TRAINING_TBL_ADDR + 16 )
  6040. #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 24 )
  6041. #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 32)
  6042. #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR                                                   (ATOM_DP_TRAINING_TBL_ADDR + 40)
  6043. #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR                                                    (ATOM_DP_TRAINING_TBL_ADDR + 48)
  6044. #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR                                                             (ATOM_DP_TRAINING_TBL_ADDR + 60)
  6045. #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR                                                                                   (ATOM_DP_TRAINING_TBL_ADDR + 64)
  6046. #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR                                                              (ATOM_DP_TRAINING_TBL_ADDR + 72)
  6047. #define DP_I2C_AUX_DDC_READ_TBL_ADDR                                                                                    (ATOM_DP_TRAINING_TBL_ADDR + 76)
  6048. #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR                 (ATOM_DP_TRAINING_TBL_ADDR + 80)
  6049. #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR                                                                        (ATOM_DP_TRAINING_TBL_ADDR + 84)
  6050.  
  6051. typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
  6052. {
  6053.         UCHAR ucI2CSpeed;
  6054.         union
  6055.         {
  6056.                 UCHAR ucRegIndex;
  6057.                 UCHAR ucStatus;
  6058.         };
  6059.         USHORT lpI2CDataOut;
  6060.         UCHAR ucFlag;
  6061.         UCHAR ucTransBytes;
  6062.         UCHAR ucSlaveAddr;
  6063.         UCHAR ucLineNumber;
  6064. }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
  6065.  
  6066. #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION       PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
  6067.  
  6068. //ucFlag
  6069. #define HW_I2C_WRITE        1
  6070. #define HW_I2C_READ         0
  6071. #define I2C_2BYTE_ADDR      0x02
  6072.  
  6073. typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
  6074. {
  6075.    UCHAR ucHWBlkInst;                // HW block instance, 0, 1, 2, ...
  6076.    UCHAR ucReserved[3];
  6077. }SET_HWBLOCK_INSTANCE_PARAMETER_V2;
  6078.  
  6079. #define HWBLKINST_INSTANCE_MASK       0x07
  6080. #define HWBLKINST_HWBLK_MASK          0xF0
  6081. #define HWBLKINST_HWBLK_SHIFT         0x04
  6082.  
  6083. //ucHWBlock
  6084. #define SELECT_DISP_ENGINE            0
  6085. #define SELECT_DISP_PLL               1
  6086. #define SELECT_DCIO_UNIPHY_LINK0      2
  6087. #define SELECT_DCIO_UNIPHY_LINK1      3
  6088. #define SELECT_DCIO_IMPCAL            4
  6089. #define SELECT_DCIO_DIG               6
  6090. #define SELECT_CRTC_PIXEL_RATE        7
  6091. #define SELECT_VGA_BLK                8
  6092.  
  6093. /****************************************************************************/ 
  6094. //Portion VI: Definitinos for vbios MC scratch registers that driver used
  6095. /****************************************************************************/
  6096.  
  6097. #define MC_MISC0__MEMORY_TYPE_MASK    0xF0000000
  6098. #define MC_MISC0__MEMORY_TYPE__GDDR1  0x10000000
  6099. #define MC_MISC0__MEMORY_TYPE__DDR2   0x20000000
  6100. #define MC_MISC0__MEMORY_TYPE__GDDR3  0x30000000
  6101. #define MC_MISC0__MEMORY_TYPE__GDDR4  0x40000000
  6102. #define MC_MISC0__MEMORY_TYPE__GDDR5  0x50000000
  6103. #define MC_MISC0__MEMORY_TYPE__DDR3   0xB0000000
  6104.  
  6105. /****************************************************************************/
  6106. //Portion VI: Definitinos being oboselete
  6107. /****************************************************************************/
  6108.  
  6109. //==========================================================================================
  6110. //Remove the definitions below when driver is ready!
  6111. typedef struct _ATOM_DAC_INFO
  6112. {
  6113.         ATOM_COMMON_TABLE_HEADER sHeader;
  6114.   USHORT                   usMaxFrequency;      // in 10kHz unit
  6115.         USHORT usReserved;
  6116. }ATOM_DAC_INFO;
  6117.  
  6118.  
  6119. typedef struct  _COMPASSIONATE_DATA          
  6120. {
  6121.         ATOM_COMMON_TABLE_HEADER sHeader;
  6122.  
  6123.   //==============================  DAC1 portion
  6124.         UCHAR ucDAC1_BG_Adjustment;
  6125.         UCHAR ucDAC1_DAC_Adjustment;
  6126.         USHORT usDAC1_FORCE_Data;
  6127.   //==============================  DAC2 portion
  6128.         UCHAR ucDAC2_CRT2_BG_Adjustment;
  6129.         UCHAR ucDAC2_CRT2_DAC_Adjustment;
  6130.         USHORT usDAC2_CRT2_FORCE_Data;
  6131.         USHORT usDAC2_CRT2_MUX_RegisterIndex;
  6132.   UCHAR   ucDAC2_CRT2_MUX_RegisterInfo;     //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
  6133.         UCHAR ucDAC2_NTSC_BG_Adjustment;
  6134.         UCHAR ucDAC2_NTSC_DAC_Adjustment;
  6135.         USHORT usDAC2_TV1_FORCE_Data;
  6136.         USHORT usDAC2_TV1_MUX_RegisterIndex;
  6137.   UCHAR   ucDAC2_TV1_MUX_RegisterInfo;      //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
  6138.         UCHAR ucDAC2_CV_BG_Adjustment;
  6139.         UCHAR ucDAC2_CV_DAC_Adjustment;
  6140.         USHORT usDAC2_CV_FORCE_Data;
  6141.         USHORT usDAC2_CV_MUX_RegisterIndex;
  6142.   UCHAR   ucDAC2_CV_MUX_RegisterInfo;       //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
  6143.         UCHAR ucDAC2_PAL_BG_Adjustment;
  6144.         UCHAR ucDAC2_PAL_DAC_Adjustment;
  6145.         USHORT usDAC2_TV2_FORCE_Data;
  6146. }COMPASSIONATE_DATA;
  6147.  
  6148. /****************************Supported Device Info Table Definitions**********************/
  6149. //  ucConnectInfo:
  6150. //    [7:4] - connector type
  6151. //      = 1   - VGA connector  
  6152. //      = 2   - DVI-I
  6153. //      = 3   - DVI-D
  6154. //      = 4   - DVI-A
  6155. //      = 5   - SVIDEO
  6156. //      = 6   - COMPOSITE
  6157. //      = 7   - LVDS
  6158. //      = 8   - DIGITAL LINK
  6159. //      = 9   - SCART
  6160. //      = 0xA - HDMI_type A
  6161. //      = 0xB - HDMI_type B
  6162. //      = 0xE - Special case1 (DVI+DIN)
  6163. //      Others=TBD
  6164. //    [3:0] - DAC Associated
  6165. //      = 0   - no DAC
  6166. //      = 1   - DACA
  6167. //      = 2   - DACB
  6168. //      = 3   - External DAC
  6169. //      Others=TBD
  6170. //    
  6171.  
  6172. typedef struct _ATOM_CONNECTOR_INFO
  6173. {
  6174. #if ATOM_BIG_ENDIAN
  6175.         UCHAR bfConnectorType:4;
  6176.         UCHAR bfAssociatedDAC:4;
  6177. #else
  6178.         UCHAR bfAssociatedDAC:4;
  6179.         UCHAR bfConnectorType:4;
  6180. #endif
  6181. }ATOM_CONNECTOR_INFO;
  6182.  
  6183. typedef union _ATOM_CONNECTOR_INFO_ACCESS
  6184. {
  6185.         ATOM_CONNECTOR_INFO sbfAccess;
  6186.         UCHAR ucAccess;
  6187. }ATOM_CONNECTOR_INFO_ACCESS;
  6188.  
  6189. typedef struct _ATOM_CONNECTOR_INFO_I2C
  6190. {
  6191.         ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
  6192.         ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
  6193. }ATOM_CONNECTOR_INFO_I2C;
  6194.  
  6195.  
  6196. typedef struct _ATOM_SUPPORTED_DEVICES_INFO
  6197. {
  6198.         ATOM_COMMON_TABLE_HEADER sHeader;
  6199.         USHORT usDeviceSupport;
  6200.         ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
  6201. }ATOM_SUPPORTED_DEVICES_INFO;
  6202.  
  6203. #define NO_INT_SRC_MAPPED       0xFF
  6204.  
  6205. typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
  6206. {
  6207.         UCHAR ucIntSrcBitmap;
  6208. }ATOM_CONNECTOR_INC_SRC_BITMAP;
  6209.  
  6210. typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
  6211. {
  6212.         ATOM_COMMON_TABLE_HEADER sHeader;
  6213.         USHORT usDeviceSupport;
  6214.         ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
  6215.   ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
  6216. }ATOM_SUPPORTED_DEVICES_INFO_2;
  6217.  
  6218. typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
  6219. {
  6220.         ATOM_COMMON_TABLE_HEADER sHeader;
  6221.         USHORT usDeviceSupport;
  6222.         ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
  6223.         ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
  6224. }ATOM_SUPPORTED_DEVICES_INFO_2d1;
  6225.  
  6226. #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
  6227.  
  6228.  
  6229.  
  6230. typedef struct _ATOM_MISC_CONTROL_INFO
  6231. {
  6232.         USHORT usFrequency;
  6233.    UCHAR  ucPLL_ChargePump;                                             // PLL charge-pump gain control
  6234.    UCHAR  ucPLL_DutyCycle;                                              // PLL duty cycle control
  6235.    UCHAR  ucPLL_VCO_Gain;                                                 // PLL VCO gain control
  6236.    UCHAR  ucPLL_VoltageSwing;                                   // PLL driver voltage swing control
  6237. }ATOM_MISC_CONTROL_INFO;  
  6238.  
  6239.  
  6240. #define ATOM_MAX_MISC_INFO       4
  6241.  
  6242. typedef struct _ATOM_TMDS_INFO
  6243. {
  6244.         ATOM_COMMON_TABLE_HEADER sHeader;
  6245.   USHORT                                                        usMaxFrequency;             // in 10Khz
  6246.         ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO];
  6247. }ATOM_TMDS_INFO;
  6248.  
  6249.  
  6250. typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
  6251. {
  6252.   UCHAR ucTVStandard;     //Same as TV standards defined above,
  6253.         UCHAR ucPadding[1];
  6254. }ATOM_ENCODER_ANALOG_ATTRIBUTE;
  6255.  
  6256. typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
  6257. {
  6258.   UCHAR ucAttribute;      //Same as other digital encoder attributes defined above
  6259.         UCHAR ucPadding[1];
  6260. }ATOM_ENCODER_DIGITAL_ATTRIBUTE;
  6261.  
  6262. typedef union _ATOM_ENCODER_ATTRIBUTE
  6263. {
  6264.         ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
  6265.         ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
  6266. }ATOM_ENCODER_ATTRIBUTE;
  6267.  
  6268.  
  6269. typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
  6270. {
  6271.         USHORT usPixelClock;
  6272.         USHORT usEncoderID;
  6273.   UCHAR  ucDeviceType;                                                                                          //Use ATOM_DEVICE_xxx1_Index to indicate device type only.     
  6274.   UCHAR  ucAction;                                                                                                              //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
  6275.         ATOM_ENCODER_ATTRIBUTE usDevAttr;
  6276. }DVO_ENCODER_CONTROL_PARAMETERS;
  6277.  
  6278. typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
  6279. {                              
  6280.         DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder;
  6281.   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
  6282. }DVO_ENCODER_CONTROL_PS_ALLOCATION;
  6283.  
  6284.  
  6285. #define ATOM_XTMDS_ASIC_SI164_ID        1
  6286. #define ATOM_XTMDS_ASIC_SI178_ID        2
  6287. #define ATOM_XTMDS_ASIC_TFP513_ID       3
  6288. #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
  6289. #define ATOM_XTMDS_SUPPORTED_DUALLINK   0x00000002
  6290. #define ATOM_XTMDS_MVPU_FPGA            0x00000004
  6291.  
  6292.                            
  6293. typedef struct _ATOM_XTMDS_INFO
  6294. {
  6295.         ATOM_COMMON_TABLE_HEADER sHeader;
  6296.         USHORT usSingleLinkMaxFrequency;
  6297.   ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;           //Point the ID on which I2C is used to control external chip
  6298.         UCHAR ucXtransimitterID;
  6299.   UCHAR                      ucSupportedLink;    // Bit field, bit0=1, single link supported;bit1=1,dual link supported
  6300.   UCHAR                      ucSequnceAlterID;   // Even with the same external TMDS asic, it's possible that the program seqence alters
  6301.                                                  // due to design. This ID is used to alert driver that the sequence is not "standard"!              
  6302.   UCHAR                      ucMasterAddress;    // Address to control Master xTMDS Chip
  6303.   UCHAR                      ucSlaveAddress;     // Address to control Slave xTMDS Chip
  6304. }ATOM_XTMDS_INFO;
  6305.  
  6306. typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
  6307. {  
  6308.   UCHAR ucEnable;                     // ATOM_ENABLE=On or ATOM_DISABLE=Off
  6309.   UCHAR ucDevice;                     // ATOM_DEVICE_DFP1_INDEX....
  6310.         UCHAR ucPadding[2];
  6311. }DFP_DPMS_STATUS_CHANGE_PARAMETERS;
  6312.  
  6313. /****************************Legacy Power Play Table Definitions **********************/
  6314.  
  6315. //Definitions for ulPowerPlayMiscInfo
  6316. #define ATOM_PM_MISCINFO_SPLIT_CLOCK                     0x00000000L
  6317. #define ATOM_PM_MISCINFO_USING_MCLK_SRC                  0x00000001L
  6318. #define ATOM_PM_MISCINFO_USING_SCLK_SRC                  0x00000002L
  6319.  
  6320. #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT            0x00000004L
  6321. #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH        0x00000008L
  6322.  
  6323. #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN             0x00000010L
  6324.  
  6325. #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN          0x00000020L
  6326. #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN          0x00000040L
  6327. #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE                 0x00000080L  //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program  
  6328.  
  6329. #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN      0x00000100L
  6330. #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN         0x00000200L
  6331. #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN              0x00000400L
  6332. #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN                 0x00000800L
  6333. #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE     0x00001000L
  6334. #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
  6335. #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE            0x00004000L
  6336.  
  6337. #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE             0x00008000L
  6338. #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE                 0x00010000L
  6339. #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE                 0x00020000L
  6340. #define ATOM_PM_MISCINFO_POWER_SAVING_MODE               0x00040000L
  6341. #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE              0x00080000L
  6342.  
  6343. #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK           0x00300000L  //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
  6344. #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT          20
  6345.  
  6346. #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE                 0x00400000L
  6347. #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2      0x00800000L
  6348. #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4      0x01000000L
  6349. #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN            0x02000000L  //When set, Dynamic
  6350. #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN        0x04000000L  //When set, Dynamic
  6351. #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN              0x08000000L  //When set, This mode is for acceleated 3D mode
  6352.  
  6353. #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK   0x70000000L  //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
  6354. #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT  28
  6355. #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS                0x80000000L
  6356.  
  6357. #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE            0x00000001L
  6358. #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT          0x00000002L
  6359. #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN           0x00000004L
  6360. #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO            0x00000008L
  6361. #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE              0x00000010L
  6362. #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN       0x00000020L
  6363. #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE         0x00000040L  //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
  6364.                                                                       //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
  6365. #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC                0x00000080L
  6366. #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN                0x00000100L
  6367. #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE               0x00000200L
  6368.  
  6369. //ucTableFormatRevision=1
  6370. //ucTableContentRevision=1
  6371. typedef struct  _ATOM_POWERMODE_INFO
  6372. {
  6373.   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
  6374.   ULONG     ulReserved1;                // must set to 0
  6375.   ULONG     ulReserved2;                // must set to 0
  6376.         USHORT usEngineClock;
  6377.         USHORT usMemoryClock;
  6378.   UCHAR     ucVoltageDropIndex;         // index to GPIO table
  6379.   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
  6380.         UCHAR ucMinTemperature;
  6381.         UCHAR ucMaxTemperature;
  6382.   UCHAR     ucNumPciELanes;             // number of PCIE lanes
  6383. }ATOM_POWERMODE_INFO;
  6384.  
  6385. //ucTableFormatRevision=2
  6386. //ucTableContentRevision=1
  6387. typedef struct  _ATOM_POWERMODE_INFO_V2
  6388. {
  6389.   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
  6390.         ULONG ulMiscInfo2;
  6391.         ULONG ulEngineClock;
  6392.         ULONG ulMemoryClock;
  6393.   UCHAR     ucVoltageDropIndex;         // index to GPIO table
  6394.   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
  6395.         UCHAR ucMinTemperature;
  6396.         UCHAR ucMaxTemperature;
  6397.   UCHAR     ucNumPciELanes;             // number of PCIE lanes
  6398. }ATOM_POWERMODE_INFO_V2;
  6399.  
  6400. //ucTableFormatRevision=2
  6401. //ucTableContentRevision=2
  6402. typedef struct  _ATOM_POWERMODE_INFO_V3
  6403. {
  6404.   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
  6405.         ULONG ulMiscInfo2;
  6406.         ULONG ulEngineClock;
  6407.         ULONG ulMemoryClock;
  6408.   UCHAR     ucVoltageDropIndex;         // index to Core (VDDC) votage table
  6409.   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
  6410.         UCHAR ucMinTemperature;
  6411.         UCHAR ucMaxTemperature;
  6412.   UCHAR     ucNumPciELanes;             // number of PCIE lanes
  6413.   UCHAR     ucVDDCI_VoltageDropIndex;   // index to VDDCI votage table
  6414. }ATOM_POWERMODE_INFO_V3;
  6415.  
  6416.  
  6417. #define ATOM_MAX_NUMBEROF_POWER_BLOCK  8
  6418.  
  6419. #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN            0x01
  6420. #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE         0x02
  6421.  
  6422. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63      0x01
  6423. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032   0x02
  6424. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030   0x03
  6425. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649   0x04
  6426. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64      0x05
  6427. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375    0x06
  6428. #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512   0x07      // Andigilog
  6429.  
  6430.  
  6431. typedef struct  _ATOM_POWERPLAY_INFO
  6432. {
  6433.         ATOM_COMMON_TABLE_HEADER sHeader;
  6434.         UCHAR ucOverdriveThermalController;
  6435.         UCHAR ucOverdriveI2cLine;
  6436.         UCHAR ucOverdriveIntBitmap;
  6437.         UCHAR ucOverdriveControllerAddress;
  6438.         UCHAR ucSizeOfPowerModeEntry;
  6439.         UCHAR ucNumOfPowerModeEntries;
  6440.         ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
  6441. }ATOM_POWERPLAY_INFO;
  6442.  
  6443. typedef struct  _ATOM_POWERPLAY_INFO_V2
  6444. {
  6445.         ATOM_COMMON_TABLE_HEADER sHeader;
  6446.         UCHAR ucOverdriveThermalController;
  6447.         UCHAR ucOverdriveI2cLine;
  6448.         UCHAR ucOverdriveIntBitmap;
  6449.         UCHAR ucOverdriveControllerAddress;
  6450.         UCHAR ucSizeOfPowerModeEntry;
  6451.         UCHAR ucNumOfPowerModeEntries;
  6452.         ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
  6453. }ATOM_POWERPLAY_INFO_V2;
  6454.  
  6455. typedef struct  _ATOM_POWERPLAY_INFO_V3
  6456. {
  6457.         ATOM_COMMON_TABLE_HEADER sHeader;
  6458.         UCHAR ucOverdriveThermalController;
  6459.         UCHAR ucOverdriveI2cLine;
  6460.         UCHAR ucOverdriveIntBitmap;
  6461.         UCHAR ucOverdriveControllerAddress;
  6462.         UCHAR ucSizeOfPowerModeEntry;
  6463.         UCHAR ucNumOfPowerModeEntries;
  6464.         ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
  6465. }ATOM_POWERPLAY_INFO_V3;
  6466.  
  6467. /* New PPlib */
  6468. /**************************************************************************/
  6469. typedef struct _ATOM_PPLIB_THERMALCONTROLLER
  6470.  
  6471. {
  6472.     UCHAR ucType;           // one of ATOM_PP_THERMALCONTROLLER_*
  6473.     UCHAR ucI2cLine;        // as interpreted by DAL I2C
  6474.     UCHAR ucI2cAddress;
  6475.     UCHAR ucFanParameters;  // Fan Control Parameters.
  6476.     UCHAR ucFanMinRPM;      // Fan Minimum RPM (hundreds) -- for display purposes only.
  6477.     UCHAR ucFanMaxRPM;      // Fan Maximum RPM (hundreds) -- for display purposes only.
  6478.     UCHAR ucReserved;       // ----
  6479.     UCHAR ucFlags;          // to be defined
  6480. } ATOM_PPLIB_THERMALCONTROLLER;
  6481.  
  6482. #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f
  6483. #define ATOM_PP_FANPARAMETERS_NOFAN                                 0x80    // No fan is connected to this controller.
  6484.  
  6485. #define ATOM_PP_THERMALCONTROLLER_NONE      0
  6486. #define ATOM_PP_THERMALCONTROLLER_LM63      1  // Not used by PPLib
  6487. #define ATOM_PP_THERMALCONTROLLER_ADM1032   2  // Not used by PPLib
  6488. #define ATOM_PP_THERMALCONTROLLER_ADM1030   3  // Not used by PPLib
  6489. #define ATOM_PP_THERMALCONTROLLER_MUA6649   4  // Not used by PPLib
  6490. #define ATOM_PP_THERMALCONTROLLER_LM64      5
  6491. #define ATOM_PP_THERMALCONTROLLER_F75375    6  // Not used by PPLib
  6492. #define ATOM_PP_THERMALCONTROLLER_RV6xx     7
  6493. #define ATOM_PP_THERMALCONTROLLER_RV770     8
  6494. #define ATOM_PP_THERMALCONTROLLER_ADT7473   9
  6495. #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO     11
  6496. #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12
  6497. #define ATOM_PP_THERMALCONTROLLER_EMC2103   13  /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen.
  6498. #define ATOM_PP_THERMALCONTROLLER_SUMO      14  /* 0x0E */ // Sumo type, used internally
  6499. #define ATOM_PP_THERMALCONTROLLER_NISLANDS  15
  6500.  
  6501. // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal.
  6502. // We probably should reserve the bit 0x80 for this use.
  6503. // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here).
  6504. // The driver can pick the correct internal controller based on the ASIC.
  6505.  
  6506. #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL   0x89    // ADT7473 Fan Control + Internal Thermal Controller
  6507. #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL   0x8D    // EMC2103 Fan Control + Internal Thermal Controller
  6508.  
  6509. typedef struct _ATOM_PPLIB_STATE
  6510. {
  6511.     UCHAR ucNonClockStateIndex;
  6512.     UCHAR ucClockStateIndices[1]; // variable-sized
  6513. } ATOM_PPLIB_STATE;
  6514.  
  6515. typedef struct _ATOM_PPLIB_FANTABLE
  6516. {
  6517.     UCHAR   ucFanTableFormat;                // Change this if the table format changes or version changes so that the other fields are not the same.
  6518.     UCHAR   ucTHyst;                         // Temperature hysteresis. Integer.
  6519.     USHORT  usTMin;                          // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM.
  6520.     USHORT  usTMed;                          // The middle temperature where we change slopes.
  6521.     USHORT  usTHigh;                         // The high point above TMed for adjusting the second slope.
  6522.     USHORT  usPWMMin;                        // The minimum PWM value in percent (0.01% increments).
  6523.     USHORT  usPWMMed;                        // The PWM value (in percent) at TMed.
  6524.     USHORT  usPWMHigh;                       // The PWM value at THigh.
  6525. } ATOM_PPLIB_FANTABLE;
  6526.  
  6527. typedef struct _ATOM_PPLIB_EXTENDEDHEADER
  6528. {
  6529.     USHORT  usSize;
  6530.     ULONG   ulMaxEngineClock;   // For Overdrive.
  6531.     ULONG   ulMaxMemoryClock;   // For Overdrive.
  6532.     // Add extra system parameters here, always adjust size to include all fields.
  6533. } ATOM_PPLIB_EXTENDEDHEADER;
  6534.  
  6535. //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
  6536. #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1
  6537. #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2
  6538. #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4
  6539. #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8
  6540. #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16
  6541. #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32
  6542. #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64
  6543. #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128
  6544. #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256
  6545. #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512
  6546. #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024
  6547. #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048
  6548. #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096
  6549. #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000              // Go to boot state on alerts, e.g. on an AC->DC transition.
  6550. #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000   // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition).
  6551. #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000                   // Does the driver control VDDCI independently from VDDC.
  6552. #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000               // Enable the 'regulator hot' feature.
  6553. #define ATOM_PP_PLATFORM_CAP_BACO          0x00020000               // Does the driver supports BACO state.
  6554.  
  6555. typedef struct _ATOM_PPLIB_POWERPLAYTABLE
  6556. {
  6557.       ATOM_COMMON_TABLE_HEADER sHeader;
  6558.  
  6559.       UCHAR ucDataRevision;
  6560.  
  6561.       UCHAR ucNumStates;
  6562.       UCHAR ucStateEntrySize;
  6563.       UCHAR ucClockInfoSize;
  6564.       UCHAR ucNonClockSize;
  6565.  
  6566.       // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures
  6567.       USHORT usStateArrayOffset;
  6568.  
  6569.       // offset from start of this table to array of ASIC-specific structures,
  6570.       // currently ATOM_PPLIB_CLOCK_INFO.
  6571.       USHORT usClockInfoArrayOffset;
  6572.  
  6573.       // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO
  6574.       USHORT usNonClockInfoArrayOffset;
  6575.  
  6576.       USHORT usBackbiasTime;    // in microseconds
  6577.       USHORT usVoltageTime;     // in microseconds
  6578.       USHORT usTableSize;       //the size of this structure, or the extended structure
  6579.  
  6580.       ULONG ulPlatformCaps;            // See ATOM_PPLIB_CAPS_*
  6581.  
  6582.       ATOM_PPLIB_THERMALCONTROLLER    sThermalController;
  6583.  
  6584.       USHORT usBootClockInfoOffset;
  6585.       USHORT usBootNonClockInfoOffset;
  6586.  
  6587. } ATOM_PPLIB_POWERPLAYTABLE;
  6588.  
  6589. typedef struct _ATOM_PPLIB_POWERPLAYTABLE2
  6590. {
  6591.     ATOM_PPLIB_POWERPLAYTABLE basicTable;
  6592.     UCHAR   ucNumCustomThermalPolicy;
  6593.     USHORT  usCustomThermalPolicyArrayOffset;
  6594. }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2;
  6595.  
  6596. typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
  6597. {
  6598.     ATOM_PPLIB_POWERPLAYTABLE2 basicTable2;
  6599.     USHORT                     usFormatID;                      // To be used ONLY by PPGen.
  6600.     USHORT                     usFanTableOffset;
  6601.     USHORT                     usExtendendedHeaderOffset;
  6602. } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3;
  6603.  
  6604. typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
  6605. {
  6606.     ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
  6607.     ULONG                      ulGoldenPPID;                    // PPGen use only    
  6608.     ULONG                      ulGoldenRevision;                // PPGen use only
  6609.     USHORT                     usVddcDependencyOnSCLKOffset;
  6610.     USHORT                     usVddciDependencyOnMCLKOffset;
  6611.     USHORT                     usVddcDependencyOnMCLKOffset;
  6612.     USHORT                     usMaxClockVoltageOnDCOffset;
  6613.     USHORT                     usReserved[2];  
  6614. } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
  6615.  
  6616. typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
  6617. {
  6618.     ATOM_PPLIB_POWERPLAYTABLE4 basicTable4;
  6619.     ULONG                      ulTDPLimit;
  6620.     ULONG                      ulNearTDPLimit;
  6621.     ULONG                      ulSQRampingThreshold;
  6622.     USHORT                     usCACLeakageTableOffset;         // Points to ATOM_PPLIB_CAC_Leakage_Table
  6623.     ULONG                      ulCACLeakage;                    // TBD, this parameter is still under discussion.  Change to ulReserved if not needed.
  6624.     ULONG                      ulReserved;
  6625. } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5;
  6626.  
  6627. //// ATOM_PPLIB_NONCLOCK_INFO::usClassification
  6628. #define ATOM_PPLIB_CLASSIFICATION_UI_MASK          0x0007
  6629. #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT         0
  6630. #define ATOM_PPLIB_CLASSIFICATION_UI_NONE          0
  6631. #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY       1
  6632. #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED      3
  6633. #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE   5
  6634. // 2, 4, 6, 7 are reserved
  6635.  
  6636. #define ATOM_PPLIB_CLASSIFICATION_BOOT                   0x0008
  6637. #define ATOM_PPLIB_CLASSIFICATION_THERMAL                0x0010
  6638. #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE     0x0020
  6639. #define ATOM_PPLIB_CLASSIFICATION_REST                   0x0040
  6640. #define ATOM_PPLIB_CLASSIFICATION_FORCED                 0x0080
  6641. #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE          0x0100
  6642. #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE      0x0200
  6643. #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE               0x0400
  6644. #define ATOM_PPLIB_CLASSIFICATION_3DLOW                  0x0800
  6645. #define ATOM_PPLIB_CLASSIFICATION_ACPI                   0x1000
  6646. #define ATOM_PPLIB_CLASSIFICATION_HD2STATE               0x2000
  6647. #define ATOM_PPLIB_CLASSIFICATION_HDSTATE                0x4000
  6648. #define ATOM_PPLIB_CLASSIFICATION_SDSTATE                0x8000
  6649.  
  6650. //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2
  6651. #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2     0x0001
  6652. #define ATOM_PPLIB_CLASSIFICATION2_ULV                      0x0002
  6653.  
  6654. //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings
  6655. #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY           0x00000001
  6656. #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK         0x00000002
  6657.  
  6658. // 0 is 2.5Gb/s, 1 is 5Gb/s
  6659. #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK            0x00000004
  6660. #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT           2
  6661.  
  6662. // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec
  6663. #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK            0x000000F8
  6664. #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT           3
  6665.  
  6666. // lookup into reduced refresh-rate table
  6667. #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK  0x00000F00
  6668. #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8
  6669.  
  6670. #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED    0
  6671. #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ         1
  6672. // 2-15 TBD as needed.
  6673.  
  6674. #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING        0x00001000
  6675. #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS  0x00002000
  6676. #define ATOM_PPLIB_DISALLOW_ON_DC                        0x00004000
  6677. #define ATOM_PPLIB_ENABLE_VARIBRIGHT                     0x00008000
  6678.  
  6679. //memory related flags
  6680. #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF               0x000010000
  6681.  
  6682. //M3 Arb    //2bits, current 3 sets of parameters in total
  6683. #define ATOM_PPLIB_M3ARB_MASK                       0x00060000
  6684. #define ATOM_PPLIB_M3ARB_SHIFT                      17
  6685.  
  6686. #define ATOM_PPLIB_ENABLE_DRR                       0x00080000
  6687.  
  6688. // remaining 16 bits are reserved
  6689. typedef struct _ATOM_PPLIB_THERMAL_STATE
  6690. {
  6691.     UCHAR   ucMinTemperature;
  6692.     UCHAR   ucMaxTemperature;
  6693.     UCHAR   ucThermalAction;
  6694. }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE;
  6695.  
  6696. // Contained in an array starting at the offset
  6697. // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset.
  6698. // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex
  6699. #define ATOM_PPLIB_NONCLOCKINFO_VER1      12
  6700. #define ATOM_PPLIB_NONCLOCKINFO_VER2      24
  6701. typedef struct _ATOM_PPLIB_NONCLOCK_INFO
  6702. {
  6703.       USHORT usClassification;
  6704.       UCHAR  ucMinTemperature;
  6705.       UCHAR  ucMaxTemperature;
  6706.       ULONG  ulCapsAndSettings;
  6707.       UCHAR  ucRequiredPower;
  6708.       USHORT usClassification2;
  6709.       ULONG  ulVCLK;
  6710.       ULONG  ulDCLK;
  6711.       UCHAR  ucUnused[5];
  6712. } ATOM_PPLIB_NONCLOCK_INFO;
  6713.  
  6714. // Contained in an array starting at the offset
  6715. // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset.
  6716. // referenced from ATOM_PPLIB_STATE::ucClockStateIndices
  6717. typedef struct _ATOM_PPLIB_R600_CLOCK_INFO
  6718. {
  6719.       USHORT usEngineClockLow;
  6720.       UCHAR ucEngineClockHigh;
  6721.  
  6722.       USHORT usMemoryClockLow;
  6723.       UCHAR ucMemoryClockHigh;
  6724.  
  6725.       USHORT usVDDC;
  6726.       USHORT usUnused1;
  6727.       USHORT usUnused2;
  6728.  
  6729.       ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
  6730.  
  6731. } ATOM_PPLIB_R600_CLOCK_INFO;
  6732.  
  6733. // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO
  6734. #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2          1
  6735. #define ATOM_PPLIB_R600_FLAGS_UVDSAFE           2
  6736. #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE    4
  6737. #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF    8
  6738. #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF    16
  6739. #define ATOM_PPLIB_R600_FLAGS_LOWPOWER         32   // On the RV770 use 'low power' setting (sequencer S0).
  6740.  
  6741. typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
  6742. {
  6743.       USHORT usEngineClockLow;
  6744.       UCHAR  ucEngineClockHigh;
  6745.  
  6746.       USHORT usMemoryClockLow;
  6747.       UCHAR  ucMemoryClockHigh;
  6748.  
  6749.       USHORT usVDDC;
  6750.       USHORT usVDDCI;
  6751.       USHORT usUnused;
  6752.  
  6753.       ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_*
  6754.  
  6755. } ATOM_PPLIB_EVERGREEN_CLOCK_INFO;
  6756.  
  6757. typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
  6758.  
  6759. {
  6760.       USHORT usLowEngineClockLow;         // Low Engine clock in MHz (the same way as on the R600).
  6761.       UCHAR  ucLowEngineClockHigh;
  6762.       USHORT usHighEngineClockLow;        // High Engine clock in MHz.
  6763.       UCHAR  ucHighEngineClockHigh;
  6764.       USHORT usMemoryClockLow;            // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants.
  6765.       UCHAR  ucMemoryClockHigh;           // Currentyl unused.
  6766.       UCHAR  ucPadding;                   // For proper alignment and size.
  6767.       USHORT usVDDC;                      // For the 780, use: None, Low, High, Variable
  6768.       UCHAR  ucMaxHTLinkWidth;            // From SBIOS - {2, 4, 8, 16}
  6769.       UCHAR  ucMinHTLinkWidth;            // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requirement.
  6770.       USHORT usHTLinkFreq;                // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
  6771.       ULONG  ulFlags;
  6772. } ATOM_PPLIB_RS780_CLOCK_INFO;
  6773.  
  6774. #define ATOM_PPLIB_RS780_VOLTAGE_NONE       0
  6775. #define ATOM_PPLIB_RS780_VOLTAGE_LOW        1
  6776. #define ATOM_PPLIB_RS780_VOLTAGE_HIGH       2
  6777. #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE   3
  6778.  
  6779. #define ATOM_PPLIB_RS780_SPMCLK_NONE        0   // We cannot change the side port memory clock, leave it as it is.
  6780. #define ATOM_PPLIB_RS780_SPMCLK_LOW         1
  6781. #define ATOM_PPLIB_RS780_SPMCLK_HIGH        2
  6782.  
  6783. #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE       0
  6784. #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW        1
  6785. #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH       2
  6786.  
  6787. typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
  6788.       USHORT usEngineClockLow;  //clockfrequency & 0xFFFF. The unit is in 10khz
  6789.       UCHAR  ucEngineClockHigh; //clockfrequency >> 16.
  6790.       UCHAR  vddcIndex;         //2-bit vddc index;
  6791.       UCHAR  leakage;          //please use 8-bit absolute value, not the 6-bit % value
  6792.       //please initalize to 0
  6793.       UCHAR  rsv;
  6794.       //please initalize to 0
  6795.       USHORT rsv1;
  6796.       //please initialize to 0s
  6797.       ULONG rsv2[2];
  6798. }ATOM_PPLIB_SUMO_CLOCK_INFO;
  6799.  
  6800.  
  6801.  
  6802. typedef struct _ATOM_PPLIB_STATE_V2
  6803. {
  6804.       //number of valid dpm levels in this state; Driver uses it to calculate the whole
  6805.       //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
  6806.       UCHAR ucNumDPMLevels;
  6807.      
  6808.       //a index to the array of nonClockInfos
  6809.       UCHAR nonClockInfoIndex;
  6810.       /**
  6811.       * Driver will read the first ucNumDPMLevels in this array
  6812.       */
  6813.       UCHAR clockInfoIndex[1];
  6814. } ATOM_PPLIB_STATE_V2;
  6815.  
  6816. typedef struct StateArray{
  6817.     //how many states we have
  6818.     UCHAR ucNumEntries;
  6819.    
  6820.     ATOM_PPLIB_STATE_V2 states[1];
  6821. }StateArray;
  6822.  
  6823.  
  6824. typedef struct ClockInfoArray{
  6825.     //how many clock levels we have
  6826.     UCHAR ucNumEntries;
  6827.    
  6828.     //sizeof(ATOM_PPLIB_SUMO_CLOCK_INFO)
  6829.     UCHAR ucEntrySize;
  6830.    
  6831.     //this is for Sumo
  6832.     ATOM_PPLIB_SUMO_CLOCK_INFO clockInfo[1];
  6833. }ClockInfoArray;
  6834.  
  6835. typedef struct NonClockInfoArray{
  6836.  
  6837.     //how many non-clock levels we have. normally should be same as number of states
  6838.     UCHAR ucNumEntries;
  6839.     //sizeof(ATOM_PPLIB_NONCLOCK_INFO)
  6840.     UCHAR ucEntrySize;
  6841.    
  6842.     ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
  6843. }NonClockInfoArray;
  6844.  
  6845. typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
  6846. {
  6847.     USHORT usClockLow;
  6848.     UCHAR  ucClockHigh;
  6849.     USHORT usVoltage;
  6850. }ATOM_PPLIB_Clock_Voltage_Dependency_Record;
  6851.  
  6852. typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
  6853. {
  6854.     UCHAR ucNumEntries;                                                // Number of entries.
  6855.     ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1];             // Dynamically allocate entries.
  6856. }ATOM_PPLIB_Clock_Voltage_Dependency_Table;
  6857.  
  6858. typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
  6859. {
  6860.     USHORT usSclkLow;
  6861.     UCHAR  ucSclkHigh;
  6862.     USHORT usMclkLow;
  6863.     UCHAR  ucMclkHigh;
  6864.     USHORT usVddc;
  6865.     USHORT usVddci;
  6866. }ATOM_PPLIB_Clock_Voltage_Limit_Record;
  6867.  
  6868. typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
  6869. {
  6870.     UCHAR ucNumEntries;                                                // Number of entries.
  6871.     ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1];                  // Dynamically allocate entries.
  6872. }ATOM_PPLIB_Clock_Voltage_Limit_Table;
  6873.  
  6874. /**************************************************************************/
  6875.  
  6876.  
  6877. // Following definitions are for compatibility issue in different SW components.
  6878. #define ATOM_MASTER_DATA_TABLE_REVISION   0x01
  6879. #define Object_Info                                                                                             Object_Header
  6880. #define AdjustARB_SEQ                                                                                   MC_InitParameter
  6881. #define VRAM_GPIO_DetectionInfo                                         VoltageObjectInfo
  6882. #define ASIC_VDDCI_Info                   ASIC_ProfilingInfo
  6883. #define ASIC_MVDDQ_Info                                                                         MemoryTrainingInfo
  6884. #define SS_Info                           PPLL_SS_Info
  6885. #define ASIC_MVDDC_Info                   ASIC_InternalSS_Info
  6886. #define DispDevicePriorityInfo                                          SaveRestoreInfo
  6887. #define DispOutInfo                                                                                             TV_VideoMode
  6888.  
  6889.  
  6890. #define ATOM_ENCODER_OBJECT_TABLE         ATOM_OBJECT_TABLE
  6891. #define ATOM_CONNECTOR_OBJECT_TABLE       ATOM_OBJECT_TABLE
  6892.  
  6893. //New device naming, remove them when both DAL/VBIOS is ready
  6894. #define DFP2I_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
  6895. #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
  6896.  
  6897. #define DFP1X_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
  6898. #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
  6899.  
  6900. #define DFP1I_OUTPUT_CONTROL_PARAMETERS    DFP1_OUTPUT_CONTROL_PARAMETERS
  6901. #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
  6902.  
  6903. #define ATOM_DEVICE_DFP1I_SUPPORT          ATOM_DEVICE_DFP1_SUPPORT
  6904. #define ATOM_DEVICE_DFP1X_SUPPORT          ATOM_DEVICE_DFP2_SUPPORT
  6905.  
  6906. #define ATOM_DEVICE_DFP1I_INDEX            ATOM_DEVICE_DFP1_INDEX
  6907. #define ATOM_DEVICE_DFP1X_INDEX            ATOM_DEVICE_DFP2_INDEX
  6908.  
  6909. #define ATOM_DEVICE_DFP2I_INDEX            0x00000009
  6910. #define ATOM_DEVICE_DFP2I_SUPPORT          (0x1L << ATOM_DEVICE_DFP2I_INDEX)
  6911.  
  6912. #define ATOM_S0_DFP1I                      ATOM_S0_DFP1
  6913. #define ATOM_S0_DFP1X                      ATOM_S0_DFP2
  6914.  
  6915. #define ATOM_S0_DFP2I                      0x00200000L
  6916. #define ATOM_S0_DFP2Ib2                    0x20
  6917.  
  6918. #define ATOM_S2_DFP1I_DPMS_STATE           ATOM_S2_DFP1_DPMS_STATE
  6919. #define ATOM_S2_DFP1X_DPMS_STATE           ATOM_S2_DFP2_DPMS_STATE
  6920.  
  6921. #define ATOM_S2_DFP2I_DPMS_STATE           0x02000000L
  6922. #define ATOM_S2_DFP2I_DPMS_STATEb3         0x02
  6923.  
  6924. #define ATOM_S3_DFP2I_ACTIVEb1             0x02
  6925.  
  6926. #define ATOM_S3_DFP1I_ACTIVE               ATOM_S3_DFP1_ACTIVE
  6927. #define ATOM_S3_DFP1X_ACTIVE               ATOM_S3_DFP2_ACTIVE
  6928.  
  6929. #define ATOM_S3_DFP2I_ACTIVE               0x00000200L
  6930.  
  6931. #define ATOM_S3_DFP1I_CRTC_ACTIVE          ATOM_S3_DFP1_CRTC_ACTIVE
  6932. #define ATOM_S3_DFP1X_CRTC_ACTIVE          ATOM_S3_DFP2_CRTC_ACTIVE
  6933. #define ATOM_S3_DFP2I_CRTC_ACTIVE          0x02000000L
  6934.  
  6935. #define ATOM_S3_DFP2I_CRTC_ACTIVEb3        0x02
  6936. #define ATOM_S5_DOS_REQ_DFP2Ib1            0x02
  6937.  
  6938. #define ATOM_S5_DOS_REQ_DFP2I              0x0200
  6939. #define ATOM_S6_ACC_REQ_DFP1I              ATOM_S6_ACC_REQ_DFP1
  6940. #define ATOM_S6_ACC_REQ_DFP1X              ATOM_S6_ACC_REQ_DFP2
  6941.  
  6942. #define ATOM_S6_ACC_REQ_DFP2Ib3            0x02
  6943. #define ATOM_S6_ACC_REQ_DFP2I              0x02000000L
  6944.  
  6945. #define TMDS1XEncoderControl               DVOEncoderControl
  6946. #define DFP1XOutputControl                 DVOOutputControl
  6947.  
  6948. #define ExternalDFPOutputControl           DFP1XOutputControl
  6949. #define EnableExternalTMDS_Encoder         TMDS1XEncoderControl
  6950.  
  6951. #define DFP1IOutputControl                 TMDSAOutputControl
  6952. #define DFP2IOutputControl                 LVTMAOutputControl
  6953.  
  6954. #define DAC1_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
  6955. #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
  6956.  
  6957. #define DAC2_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
  6958. #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
  6959.  
  6960. #define ucDac1Standard  ucDacStandard
  6961. #define ucDac2Standard  ucDacStandard
  6962.  
  6963. #define TMDS1EncoderControl TMDSAEncoderControl
  6964. #define TMDS2EncoderControl LVTMAEncoderControl
  6965.  
  6966. #define DFP1OutputControl   TMDSAOutputControl
  6967. #define DFP2OutputControl   LVTMAOutputControl
  6968. #define CRT1OutputControl   DAC1OutputControl
  6969. #define CRT2OutputControl   DAC2OutputControl
  6970.  
  6971. //These two lines will be removed for sure in a few days, will follow up with Michael V.
  6972. #define EnableLVDS_SS   EnableSpreadSpectrumOnPPLL
  6973. #define ENABLE_LVDS_SS_PARAMETERS_V3  ENABLE_SPREAD_SPECTRUM_ON_PPLL
  6974.  
  6975. //#define ATOM_S2_CRT1_DPMS_STATE         0x00010000L
  6976. //#define ATOM_S2_LCD1_DPMS_STATE               ATOM_S2_CRT1_DPMS_STATE
  6977. //#define ATOM_S2_TV1_DPMS_STATE          ATOM_S2_CRT1_DPMS_STATE
  6978. //#define ATOM_S2_DFP1_DPMS_STATE         ATOM_S2_CRT1_DPMS_STATE
  6979. //#define ATOM_S2_CRT2_DPMS_STATE         ATOM_S2_CRT1_DPMS_STATE
  6980.  
  6981. #define ATOM_S6_ACC_REQ_TV2             0x00400000L
  6982. #define ATOM_DEVICE_TV2_INDEX           0x00000006
  6983. #define ATOM_DEVICE_TV2_SUPPORT         (0x1L << ATOM_DEVICE_TV2_INDEX)
  6984. #define ATOM_S0_TV2                     0x00100000L
  6985. #define ATOM_S3_TV2_ACTIVE              ATOM_S3_DFP6_ACTIVE
  6986. #define ATOM_S3_TV2_CRTC_ACTIVE         ATOM_S3_DFP6_CRTC_ACTIVE
  6987.  
  6988. //
  6989. #define ATOM_S2_CRT1_DPMS_STATE         0x00010000L
  6990. #define ATOM_S2_LCD1_DPMS_STATE         0x00020000L
  6991. #define ATOM_S2_TV1_DPMS_STATE          0x00040000L
  6992. #define ATOM_S2_DFP1_DPMS_STATE         0x00080000L
  6993. #define ATOM_S2_CRT2_DPMS_STATE         0x00100000L
  6994. #define ATOM_S2_LCD2_DPMS_STATE         0x00200000L
  6995. #define ATOM_S2_TV2_DPMS_STATE          0x00400000L
  6996. #define ATOM_S2_DFP2_DPMS_STATE         0x00800000L
  6997. #define ATOM_S2_CV_DPMS_STATE           0x01000000L
  6998. #define ATOM_S2_DFP3_DPMS_STATE                                 0x02000000L
  6999. #define ATOM_S2_DFP4_DPMS_STATE                                 0x04000000L
  7000. #define ATOM_S2_DFP5_DPMS_STATE                                 0x08000000L
  7001.  
  7002. #define ATOM_S2_CRT1_DPMS_STATEb2       0x01
  7003. #define ATOM_S2_LCD1_DPMS_STATEb2       0x02
  7004. #define ATOM_S2_TV1_DPMS_STATEb2        0x04
  7005. #define ATOM_S2_DFP1_DPMS_STATEb2       0x08
  7006. #define ATOM_S2_CRT2_DPMS_STATEb2       0x10
  7007. #define ATOM_S2_LCD2_DPMS_STATEb2       0x20
  7008. #define ATOM_S2_TV2_DPMS_STATEb2        0x40
  7009. #define ATOM_S2_DFP2_DPMS_STATEb2       0x80
  7010. #define ATOM_S2_CV_DPMS_STATEb3         0x01
  7011. #define ATOM_S2_DFP3_DPMS_STATEb3                               0x02
  7012. #define ATOM_S2_DFP4_DPMS_STATEb3                               0x04
  7013. #define ATOM_S2_DFP5_DPMS_STATEb3                               0x08
  7014.  
  7015. #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3  0x20
  7016. #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40
  7017. #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3  0x80
  7018.  
  7019. /*********************************************************************************/
  7020.  
  7021. #pragma pack() // BIOS data must use byte aligment
  7022.  
  7023. #endif /* _ATOMBIOS_H */
  7024.