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  1. /*
  2.  * Copyright © 2011 Intel Corporation
  3.  *
  4.  * Permission is hereby granted, free of charge, to any person obtaining a
  5.  * copy of this software and associated documentation files (the "Software"),
  6.  * to deal in the Software without restriction, including without limitation
  7.  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8.  * and/or sell copies of the Software, and to permit persons to whom the
  9.  * Software is furnished to do so, subject to the following conditions:
  10.  *
  11.  * The above copyright notice and this permission notice (including the next
  12.  * paragraph) shall be included in all copies or substantial portions of the
  13.  * Software.
  14.  *
  15.  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16.  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17.  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18.  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19.  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20.  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21.  * SOFTWARE.
  22.  *
  23.  * Authors:
  24.  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25.  *
  26.  * New plane/sprite handling.
  27.  *
  28.  * The older chips had a separate interface for programming plane related
  29.  * registers; newer ones are much simpler and we can use the new DRM plane
  30.  * support.
  31.  */
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_fourcc.h>
  35. #include <drm/drm_rect.h>
  36. #include <drm/drm_atomic.h>
  37. #include <drm/drm_plane_helper.h>
  38. #include "intel_drv.h"
  39. #include <drm/i915_drm.h>
  40. #include "i915_drv.h"
  41.  
  42. static bool
  43. format_is_yuv(uint32_t format)
  44. {
  45.         switch (format) {
  46.         case DRM_FORMAT_YUYV:
  47.         case DRM_FORMAT_UYVY:
  48.         case DRM_FORMAT_VYUY:
  49.         case DRM_FORMAT_YVYU:
  50.                 return true;
  51.         default:
  52.                 return false;
  53.         }
  54. }
  55.  
  56. static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  57.                               int usecs)
  58. {
  59.         /* paranoia */
  60.         if (!adjusted_mode->crtc_htotal)
  61.                 return 1;
  62.  
  63.         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  64.                             1000 * adjusted_mode->crtc_htotal);
  65. }
  66.  
  67. /**
  68.  * intel_pipe_update_start() - start update of a set of display registers
  69.  * @crtc: the crtc of which the registers are going to be updated
  70.  * @start_vbl_count: vblank counter return pointer used for error checking
  71.  *
  72.  * Mark the start of an update to pipe registers that should be updated
  73.  * atomically regarding vblank. If the next vblank will happens within
  74.  * the next 100 us, this function waits until the vblank passes.
  75.  *
  76.  * After a successful call to this function, interrupts will be disabled
  77.  * until a subsequent call to intel_pipe_update_end(). That is done to
  78.  * avoid random delays. The value written to @start_vbl_count should be
  79.  * supplied to intel_pipe_update_end() for error checking.
  80.  */
  81. void intel_pipe_update_start(struct intel_crtc *crtc)
  82. {
  83.         struct drm_device *dev = crtc->base.dev;
  84.         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  85.         enum pipe pipe = crtc->pipe;
  86.         long timeout = msecs_to_jiffies_timeout(1);
  87.         int scanline, min, max, vblank_start;
  88.         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  89.         DEFINE_WAIT(wait);
  90.  
  91.         vblank_start = adjusted_mode->crtc_vblank_start;
  92.         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  93.                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  94.  
  95.         /* FIXME needs to be calibrated sensibly */
  96.         min = vblank_start - usecs_to_scanlines(adjusted_mode, 100);
  97.         max = vblank_start - 1;
  98.  
  99.         local_irq_disable();
  100.  
  101.         if (min <= 0 || max <= 0)
  102.                 return;
  103.  
  104.         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
  105.                 return;
  106.  
  107.         crtc->debug.min_vbl = min;
  108.         crtc->debug.max_vbl = max;
  109.         trace_i915_pipe_update_start(crtc);
  110.  
  111.         for (;;) {
  112.                 /*
  113.                  * prepare_to_wait() has a memory barrier, which guarantees
  114.                  * other CPUs can see the task state update by the time we
  115.                  * read the scanline.
  116.                  */
  117.                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
  118.  
  119.                 scanline = intel_get_crtc_scanline(crtc);
  120.                 if (scanline < min || scanline > max)
  121.                         break;
  122.  
  123.                 if (timeout <= 0) {
  124.                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
  125.                                   pipe_name(crtc->pipe));
  126.                         break;
  127.                 }
  128.  
  129.                 local_irq_enable();
  130.                
  131.                 {
  132.                         unsigned long expire;
  133.                         expire = timeout + jiffies;
  134.                         WaitEventTimeout(wait.evnt, timeout);;
  135.                         timeout = expire - jiffies;
  136.                         timeout = timeout < 0 ? 0 : timeout;
  137.                 }
  138.                 local_irq_disable();
  139.         }
  140.  
  141.         finish_wait(wq, &wait);
  142.  
  143.         drm_crtc_vblank_put(&crtc->base);
  144.  
  145.         crtc->debug.scanline_start = scanline;
  146.         crtc->debug.start_vbl_time = ktime_get();
  147.         crtc->debug.start_vbl_count =
  148.                 dev->driver->get_vblank_counter(dev, pipe);
  149.  
  150.         trace_i915_pipe_update_vblank_evaded(crtc);
  151. }
  152.  
  153. /**
  154.  * intel_pipe_update_end() - end update of a set of display registers
  155.  * @crtc: the crtc of which the registers were updated
  156.  * @start_vbl_count: start vblank counter (used for error checking)
  157.  *
  158.  * Mark the end of an update started with intel_pipe_update_start(). This
  159.  * re-enables interrupts and verifies the update was actually completed
  160.  * before a vblank using the value of @start_vbl_count.
  161.  */
  162. void intel_pipe_update_end(struct intel_crtc *crtc)
  163. {
  164.         struct drm_device *dev = crtc->base.dev;
  165.         enum pipe pipe = crtc->pipe;
  166.         int scanline_end = intel_get_crtc_scanline(crtc);
  167.         u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
  168.         ktime_t end_vbl_time = ktime_get();
  169.  
  170.         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
  171.  
  172.         local_irq_enable();
  173.  
  174.         if (crtc->debug.start_vbl_count &&
  175.             crtc->debug.start_vbl_count != end_vbl_count) {
  176.                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
  177.                           pipe_name(pipe), crtc->debug.start_vbl_count,
  178.                           end_vbl_count,
  179.                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
  180.                           crtc->debug.min_vbl, crtc->debug.max_vbl,
  181.                           crtc->debug.scanline_start, scanline_end);
  182.         }
  183. }
  184.  
  185. static void
  186. skl_update_plane(struct drm_plane *drm_plane,
  187.                  const struct intel_crtc_state *crtc_state,
  188.                  const struct intel_plane_state *plane_state)
  189. {
  190.         struct drm_device *dev = drm_plane->dev;
  191.         struct drm_i915_private *dev_priv = dev->dev_private;
  192.         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
  193.         struct drm_framebuffer *fb = plane_state->base.fb;
  194.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  195.         const int pipe = intel_plane->pipe;
  196.         const int plane = intel_plane->plane + 1;
  197.         u32 plane_ctl, stride_div, stride;
  198.         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
  199.         u32 surf_addr;
  200.         u32 tile_height, plane_offset, plane_size;
  201.         unsigned int rotation;
  202.         int x_offset, y_offset;
  203.         int crtc_x = plane_state->dst.x1;
  204.         int crtc_y = plane_state->dst.y1;
  205.         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
  206.         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
  207.         uint32_t x = plane_state->src.x1 >> 16;
  208.         uint32_t y = plane_state->src.y1 >> 16;
  209.         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
  210.         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
  211.         const struct intel_scaler *scaler =
  212.                 &crtc_state->scaler_state.scalers[plane_state->scaler_id];
  213.  
  214.         plane_ctl = PLANE_CTL_ENABLE |
  215.                 PLANE_CTL_PIPE_GAMMA_ENABLE |
  216.                 PLANE_CTL_PIPE_CSC_ENABLE;
  217.  
  218.         plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
  219.         plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
  220.  
  221.         rotation = plane_state->base.rotation;
  222.         plane_ctl |= skl_plane_ctl_rotation(rotation);
  223.  
  224.         stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
  225.                                                fb->pixel_format);
  226.  
  227.         /* Sizes are 0 based */
  228.         src_w--;
  229.         src_h--;
  230.         crtc_w--;
  231.         crtc_h--;
  232.  
  233.         if (key->flags) {
  234.                 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
  235.                 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
  236.                 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
  237.         }
  238.  
  239.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  240.                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
  241.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  242.                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
  243.  
  244.         surf_addr = intel_plane_obj_offset(intel_plane, obj, 0);
  245.  
  246.         if (intel_rotation_90_or_270(rotation)) {
  247.                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
  248.  
  249.                 /* stride: Surface height in tiles */
  250.                 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
  251.                 stride = DIV_ROUND_UP(fb->height, tile_height);
  252.                 plane_size = (src_w << 16) | src_h;
  253.                 x_offset = stride * tile_height - y - (src_h + 1);
  254.                 y_offset = x;
  255.         } else {
  256.                 stride = fb->pitches[0] / stride_div;
  257.                 plane_size = (src_h << 16) | src_w;
  258.                 x_offset = x;
  259.                 y_offset = y;
  260.         }
  261.         plane_offset = y_offset << 16 | x_offset;
  262.  
  263.         I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset);
  264.         I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
  265.         I915_WRITE(PLANE_SIZE(pipe, plane), plane_size);
  266.  
  267.         /* program plane scaler */
  268.         if (plane_state->scaler_id >= 0) {
  269.                 uint32_t ps_ctrl = 0;
  270.                 int scaler_id = plane_state->scaler_id;
  271.  
  272.                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane,
  273.                         PS_PLANE_SEL(plane));
  274.                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode;
  275.                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
  276.                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
  277.                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
  278.                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
  279.                         ((crtc_w + 1) << 16)|(crtc_h + 1));
  280.  
  281.                 I915_WRITE(PLANE_POS(pipe, plane), 0);
  282.         } else {
  283.                 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
  284.         }
  285.  
  286.         I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
  287.         I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
  288.         POSTING_READ(PLANE_SURF(pipe, plane));
  289. }
  290.  
  291. static void
  292. skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
  293. {
  294.         struct drm_device *dev = dplane->dev;
  295.         struct drm_i915_private *dev_priv = dev->dev_private;
  296.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  297.         const int pipe = intel_plane->pipe;
  298.         const int plane = intel_plane->plane + 1;
  299.  
  300.         I915_WRITE(PLANE_CTL(pipe, plane), 0);
  301.  
  302.         I915_WRITE(PLANE_SURF(pipe, plane), 0);
  303.         POSTING_READ(PLANE_SURF(pipe, plane));
  304. }
  305.  
  306. static void
  307. chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
  308. {
  309.         struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
  310.         int plane = intel_plane->plane;
  311.  
  312.         /* Seems RGB data bypasses the CSC always */
  313.         if (!format_is_yuv(format))
  314.                 return;
  315.  
  316.         /*
  317.          * BT.601 limited range YCbCr -> full range RGB
  318.          *
  319.          * |r|   | 6537 4769     0|   |cr  |
  320.          * |g| = |-3330 4769 -1605| x |y-64|
  321.          * |b|   |    0 4769  8263|   |cb  |
  322.          *
  323.          * Cb and Cr apparently come in as signed already, so no
  324.          * need for any offset. For Y we need to remove the offset.
  325.          */
  326.         I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
  327.         I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
  328.         I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
  329.  
  330.         I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
  331.         I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
  332.         I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
  333.         I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
  334.         I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
  335.  
  336.         I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
  337.         I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
  338.         I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
  339.  
  340.         I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  341.         I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  342.         I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
  343. }
  344.  
  345. static void
  346. vlv_update_plane(struct drm_plane *dplane,
  347.                  const struct intel_crtc_state *crtc_state,
  348.                  const struct intel_plane_state *plane_state)
  349. {
  350.         struct drm_device *dev = dplane->dev;
  351.         struct drm_i915_private *dev_priv = dev->dev_private;
  352.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  353.         struct drm_framebuffer *fb = plane_state->base.fb;
  354.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  355.         int pipe = intel_plane->pipe;
  356.         int plane = intel_plane->plane;
  357.         u32 sprctl;
  358.         u32 sprsurf_offset, linear_offset;
  359.         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
  360.         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
  361.         int crtc_x = plane_state->dst.x1;
  362.         int crtc_y = plane_state->dst.y1;
  363.         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
  364.         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
  365.         uint32_t x = plane_state->src.x1 >> 16;
  366.         uint32_t y = plane_state->src.y1 >> 16;
  367.         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
  368.         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
  369.  
  370.         sprctl = SP_ENABLE;
  371.  
  372.         switch (fb->pixel_format) {
  373.         case DRM_FORMAT_YUYV:
  374.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
  375.                 break;
  376.         case DRM_FORMAT_YVYU:
  377.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
  378.                 break;
  379.         case DRM_FORMAT_UYVY:
  380.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
  381.                 break;
  382.         case DRM_FORMAT_VYUY:
  383.                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
  384.                 break;
  385.         case DRM_FORMAT_RGB565:
  386.                 sprctl |= SP_FORMAT_BGR565;
  387.                 break;
  388.         case DRM_FORMAT_XRGB8888:
  389.                 sprctl |= SP_FORMAT_BGRX8888;
  390.                 break;
  391.         case DRM_FORMAT_ARGB8888:
  392.                 sprctl |= SP_FORMAT_BGRA8888;
  393.                 break;
  394.         case DRM_FORMAT_XBGR2101010:
  395.                 sprctl |= SP_FORMAT_RGBX1010102;
  396.                 break;
  397.         case DRM_FORMAT_ABGR2101010:
  398.                 sprctl |= SP_FORMAT_RGBA1010102;
  399.                 break;
  400.         case DRM_FORMAT_XBGR8888:
  401.                 sprctl |= SP_FORMAT_RGBX8888;
  402.                 break;
  403.         case DRM_FORMAT_ABGR8888:
  404.                 sprctl |= SP_FORMAT_RGBA8888;
  405.                 break;
  406.         default:
  407.                 /*
  408.                  * If we get here one of the upper layers failed to filter
  409.                  * out the unsupported plane formats
  410.                  */
  411.                 BUG();
  412.                 break;
  413.         }
  414.  
  415.         /*
  416.          * Enable gamma to match primary/cursor plane behaviour.
  417.          * FIXME should be user controllable via propertiesa.
  418.          */
  419.         sprctl |= SP_GAMMA_ENABLE;
  420.  
  421.         if (obj->tiling_mode != I915_TILING_NONE)
  422.                 sprctl |= SP_TILED;
  423.  
  424.         /* Sizes are 0 based */
  425.         src_w--;
  426.         src_h--;
  427.         crtc_w--;
  428.         crtc_h--;
  429.  
  430.         linear_offset = y * fb->pitches[0] + x * cpp;
  431.         sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
  432.                                                    fb->modifier[0], cpp,
  433.                                                    fb->pitches[0]);
  434.         linear_offset -= sprsurf_offset;
  435.  
  436.         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
  437.                 sprctl |= SP_ROTATE_180;
  438.  
  439.                 x += src_w;
  440.                 y += src_h;
  441.                 linear_offset += src_h * fb->pitches[0] + src_w * cpp;
  442.         }
  443.  
  444.         if (key->flags) {
  445.                 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
  446.                 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
  447.                 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
  448.         }
  449.  
  450.         if (key->flags & I915_SET_COLORKEY_SOURCE)
  451.                 sprctl |= SP_SOURCE_KEY;
  452.  
  453.         if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
  454.                 chv_update_csc(intel_plane, fb->pixel_format);
  455.  
  456.         I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
  457.         I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
  458.  
  459.         if (obj->tiling_mode != I915_TILING_NONE)
  460.                 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
  461.         else
  462.                 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
  463.  
  464.         I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
  465.  
  466.         I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
  467.         I915_WRITE(SPCNTR(pipe, plane), sprctl);
  468.         I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
  469.                    sprsurf_offset);
  470.         POSTING_READ(SPSURF(pipe, plane));
  471. }
  472.  
  473. static void
  474. vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
  475. {
  476.         struct drm_device *dev = dplane->dev;
  477.         struct drm_i915_private *dev_priv = dev->dev_private;
  478.         struct intel_plane *intel_plane = to_intel_plane(dplane);
  479.         int pipe = intel_plane->pipe;
  480.         int plane = intel_plane->plane;
  481.  
  482.         I915_WRITE(SPCNTR(pipe, plane), 0);
  483.  
  484.         I915_WRITE(SPSURF(pipe, plane), 0);
  485.         POSTING_READ(SPSURF(pipe, plane));
  486. }
  487.  
  488. static void
  489. ivb_update_plane(struct drm_plane *plane,
  490.                  const struct intel_crtc_state *crtc_state,
  491.                  const struct intel_plane_state *plane_state)
  492. {
  493.         struct drm_device *dev = plane->dev;
  494.         struct drm_i915_private *dev_priv = dev->dev_private;
  495.         struct intel_plane *intel_plane = to_intel_plane(plane);
  496.         struct drm_framebuffer *fb = plane_state->base.fb;
  497.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  498.         enum pipe pipe = intel_plane->pipe;
  499.         u32 sprctl, sprscale = 0;
  500.         u32 sprsurf_offset, linear_offset;
  501.         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
  502.         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
  503.         int crtc_x = plane_state->dst.x1;
  504.         int crtc_y = plane_state->dst.y1;
  505.         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
  506.         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
  507.         uint32_t x = plane_state->src.x1 >> 16;
  508.         uint32_t y = plane_state->src.y1 >> 16;
  509.         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
  510.         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
  511.  
  512.         sprctl = SPRITE_ENABLE;
  513.  
  514.         switch (fb->pixel_format) {
  515.         case DRM_FORMAT_XBGR8888:
  516.                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
  517.                 break;
  518.         case DRM_FORMAT_XRGB8888:
  519.                 sprctl |= SPRITE_FORMAT_RGBX888;
  520.                 break;
  521.         case DRM_FORMAT_YUYV:
  522.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
  523.                 break;
  524.         case DRM_FORMAT_YVYU:
  525.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
  526.                 break;
  527.         case DRM_FORMAT_UYVY:
  528.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
  529.                 break;
  530.         case DRM_FORMAT_VYUY:
  531.                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
  532.                 break;
  533.         default:
  534.                 BUG();
  535.         }
  536.  
  537.         /*
  538.          * Enable gamma to match primary/cursor plane behaviour.
  539.          * FIXME should be user controllable via propertiesa.
  540.          */
  541.         sprctl |= SPRITE_GAMMA_ENABLE;
  542.  
  543.         if (obj->tiling_mode != I915_TILING_NONE)
  544.                 sprctl |= SPRITE_TILED;
  545.  
  546.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  547.                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
  548.         else
  549.                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
  550.  
  551.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  552.                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
  553.  
  554.         /* Sizes are 0 based */
  555.         src_w--;
  556.         src_h--;
  557.         crtc_w--;
  558.         crtc_h--;
  559.  
  560.         if (crtc_w != src_w || crtc_h != src_h)
  561.                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
  562.  
  563.         linear_offset = y * fb->pitches[0] + x * cpp;
  564.         sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
  565.                                                    fb->modifier[0], cpp,
  566.                                                    fb->pitches[0]);
  567.         linear_offset -= sprsurf_offset;
  568.  
  569.         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
  570.                 sprctl |= SPRITE_ROTATE_180;
  571.  
  572.                 /* HSW and BDW does this automagically in hardware */
  573.                 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
  574.                         x += src_w;
  575.                         y += src_h;
  576.                         linear_offset += src_h * fb->pitches[0] + src_w * cpp;
  577.                 }
  578.         }
  579.  
  580.         if (key->flags) {
  581.                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
  582.                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
  583.                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
  584.         }
  585.  
  586.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  587.                 sprctl |= SPRITE_DEST_KEY;
  588.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  589.                 sprctl |= SPRITE_SOURCE_KEY;
  590.  
  591.         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
  592.         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
  593.  
  594.         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
  595.          * register */
  596.         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
  597.                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
  598.         else if (obj->tiling_mode != I915_TILING_NONE)
  599.                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
  600.         else
  601.                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
  602.  
  603.         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
  604.         if (intel_plane->can_scale)
  605.                 I915_WRITE(SPRSCALE(pipe), sprscale);
  606.         I915_WRITE(SPRCTL(pipe), sprctl);
  607.         I915_WRITE(SPRSURF(pipe),
  608.                    i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
  609.         POSTING_READ(SPRSURF(pipe));
  610. }
  611.  
  612. static void
  613. ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
  614. {
  615.         struct drm_device *dev = plane->dev;
  616.         struct drm_i915_private *dev_priv = dev->dev_private;
  617.         struct intel_plane *intel_plane = to_intel_plane(plane);
  618.         int pipe = intel_plane->pipe;
  619.  
  620.         I915_WRITE(SPRCTL(pipe), 0);
  621.         /* Can't leave the scaler enabled... */
  622.         if (intel_plane->can_scale)
  623.                 I915_WRITE(SPRSCALE(pipe), 0);
  624.  
  625.         I915_WRITE(SPRSURF(pipe), 0);
  626.         POSTING_READ(SPRSURF(pipe));
  627. }
  628.  
  629. static void
  630. ilk_update_plane(struct drm_plane *plane,
  631.                  const struct intel_crtc_state *crtc_state,
  632.                  const struct intel_plane_state *plane_state)
  633. {
  634.         struct drm_device *dev = plane->dev;
  635.         struct drm_i915_private *dev_priv = dev->dev_private;
  636.         struct intel_plane *intel_plane = to_intel_plane(plane);
  637.         struct drm_framebuffer *fb = plane_state->base.fb;
  638.         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
  639.         int pipe = intel_plane->pipe;
  640.         u32 dvscntr, dvsscale;
  641.         u32 dvssurf_offset, linear_offset;
  642.         int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
  643.         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
  644.         int crtc_x = plane_state->dst.x1;
  645.         int crtc_y = plane_state->dst.y1;
  646.         uint32_t crtc_w = drm_rect_width(&plane_state->dst);
  647.         uint32_t crtc_h = drm_rect_height(&plane_state->dst);
  648.         uint32_t x = plane_state->src.x1 >> 16;
  649.         uint32_t y = plane_state->src.y1 >> 16;
  650.         uint32_t src_w = drm_rect_width(&plane_state->src) >> 16;
  651.         uint32_t src_h = drm_rect_height(&plane_state->src) >> 16;
  652.  
  653.         dvscntr = DVS_ENABLE;
  654.  
  655.         switch (fb->pixel_format) {
  656.         case DRM_FORMAT_XBGR8888:
  657.                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
  658.                 break;
  659.         case DRM_FORMAT_XRGB8888:
  660.                 dvscntr |= DVS_FORMAT_RGBX888;
  661.                 break;
  662.         case DRM_FORMAT_YUYV:
  663.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
  664.                 break;
  665.         case DRM_FORMAT_YVYU:
  666.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
  667.                 break;
  668.         case DRM_FORMAT_UYVY:
  669.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
  670.                 break;
  671.         case DRM_FORMAT_VYUY:
  672.                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
  673.                 break;
  674.         default:
  675.                 BUG();
  676.         }
  677.  
  678.         /*
  679.          * Enable gamma to match primary/cursor plane behaviour.
  680.          * FIXME should be user controllable via propertiesa.
  681.          */
  682.         dvscntr |= DVS_GAMMA_ENABLE;
  683.  
  684.         if (obj->tiling_mode != I915_TILING_NONE)
  685.                 dvscntr |= DVS_TILED;
  686.  
  687.         if (IS_GEN6(dev))
  688.                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
  689.  
  690.         /* Sizes are 0 based */
  691.         src_w--;
  692.         src_h--;
  693.         crtc_w--;
  694.         crtc_h--;
  695.  
  696.         dvsscale = 0;
  697.         if (crtc_w != src_w || crtc_h != src_h)
  698.                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
  699.  
  700.         linear_offset = y * fb->pitches[0] + x * cpp;
  701.         dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y,
  702.                                                    fb->modifier[0], cpp,
  703.                                                    fb->pitches[0]);
  704.         linear_offset -= dvssurf_offset;
  705.  
  706.         if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
  707.                 dvscntr |= DVS_ROTATE_180;
  708.  
  709.                 x += src_w;
  710.                 y += src_h;
  711.                 linear_offset += src_h * fb->pitches[0] + src_w * cpp;
  712.         }
  713.  
  714.         if (key->flags) {
  715.                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
  716.                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
  717.                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
  718.         }
  719.  
  720.         if (key->flags & I915_SET_COLORKEY_DESTINATION)
  721.                 dvscntr |= DVS_DEST_KEY;
  722.         else if (key->flags & I915_SET_COLORKEY_SOURCE)
  723.                 dvscntr |= DVS_SOURCE_KEY;
  724.  
  725.         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
  726.         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
  727.  
  728.         if (obj->tiling_mode != I915_TILING_NONE)
  729.                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
  730.         else
  731.                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
  732.  
  733.         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
  734.         I915_WRITE(DVSSCALE(pipe), dvsscale);
  735.         I915_WRITE(DVSCNTR(pipe), dvscntr);
  736.         I915_WRITE(DVSSURF(pipe),
  737.                    i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
  738.         POSTING_READ(DVSSURF(pipe));
  739. }
  740.  
  741. static void
  742. ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
  743. {
  744.         struct drm_device *dev = plane->dev;
  745.         struct drm_i915_private *dev_priv = dev->dev_private;
  746.         struct intel_plane *intel_plane = to_intel_plane(plane);
  747.         int pipe = intel_plane->pipe;
  748.  
  749.         I915_WRITE(DVSCNTR(pipe), 0);
  750.         /* Disable the scaler */
  751.         I915_WRITE(DVSSCALE(pipe), 0);
  752.  
  753.         I915_WRITE(DVSSURF(pipe), 0);
  754.         POSTING_READ(DVSSURF(pipe));
  755. }
  756.  
  757. static int
  758. intel_check_sprite_plane(struct drm_plane *plane,
  759.                          struct intel_crtc_state *crtc_state,
  760.                          struct intel_plane_state *state)
  761. {
  762.         struct drm_device *dev = plane->dev;
  763.         struct drm_crtc *crtc = state->base.crtc;
  764.         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  765.         struct intel_plane *intel_plane = to_intel_plane(plane);
  766.         struct drm_framebuffer *fb = state->base.fb;
  767.         int crtc_x, crtc_y;
  768.         unsigned int crtc_w, crtc_h;
  769.         uint32_t src_x, src_y, src_w, src_h;
  770.         struct drm_rect *src = &state->src;
  771.         struct drm_rect *dst = &state->dst;
  772.         const struct drm_rect *clip = &state->clip;
  773.         int hscale, vscale;
  774.         int max_scale, min_scale;
  775.         bool can_scale;
  776.  
  777.         if (!fb) {
  778.                 state->visible = false;
  779.                 return 0;
  780.         }
  781.  
  782.         /* Don't modify another pipe's plane */
  783.         if (intel_plane->pipe != intel_crtc->pipe) {
  784.                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
  785.                 return -EINVAL;
  786.         }
  787.  
  788.         /* FIXME check all gen limits */
  789.         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
  790.                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
  791.                 return -EINVAL;
  792.         }
  793.  
  794.         /* setup can_scale, min_scale, max_scale */
  795.         if (INTEL_INFO(dev)->gen >= 9) {
  796.                 /* use scaler when colorkey is not required */
  797.                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
  798.                         can_scale = 1;
  799.                         min_scale = 1;
  800.                         max_scale = skl_max_scale(intel_crtc, crtc_state);
  801.                 } else {
  802.                         can_scale = 0;
  803.                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
  804.                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
  805.                 }
  806.         } else {
  807.                 can_scale = intel_plane->can_scale;
  808.                 max_scale = intel_plane->max_downscale << 16;
  809.                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
  810.         }
  811.  
  812.         /*
  813.          * FIXME the following code does a bunch of fuzzy adjustments to the
  814.          * coordinates and sizes. We probably need some way to decide whether
  815.          * more strict checking should be done instead.
  816.          */
  817.         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
  818.                         state->base.rotation);
  819.  
  820.         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
  821.         BUG_ON(hscale < 0);
  822.  
  823.         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
  824.         BUG_ON(vscale < 0);
  825.  
  826.         state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
  827.  
  828.         crtc_x = dst->x1;
  829.         crtc_y = dst->y1;
  830.         crtc_w = drm_rect_width(dst);
  831.         crtc_h = drm_rect_height(dst);
  832.  
  833.         if (state->visible) {
  834.                 /* check again in case clipping clamped the results */
  835.                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
  836.                 if (hscale < 0) {
  837.                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
  838.                         drm_rect_debug_print("src: ", src, true);
  839.                         drm_rect_debug_print("dst: ", dst, false);
  840.  
  841.                         return hscale;
  842.                 }
  843.  
  844.                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
  845.                 if (vscale < 0) {
  846.                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
  847.                         drm_rect_debug_print("src: ", src, true);
  848.                         drm_rect_debug_print("dst: ", dst, false);
  849.  
  850.                         return vscale;
  851.                 }
  852.  
  853.                 /* Make the source viewport size an exact multiple of the scaling factors. */
  854.                 drm_rect_adjust_size(src,
  855.                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
  856.                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
  857.  
  858.                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
  859.                                     state->base.rotation);
  860.  
  861.                 /* sanity check to make sure the src viewport wasn't enlarged */
  862.                 WARN_ON(src->x1 < (int) state->base.src_x ||
  863.                         src->y1 < (int) state->base.src_y ||
  864.                         src->x2 > (int) state->base.src_x + state->base.src_w ||
  865.                         src->y2 > (int) state->base.src_y + state->base.src_h);
  866.  
  867.                 /*
  868.                  * Hardware doesn't handle subpixel coordinates.
  869.                  * Adjust to (macro)pixel boundary, but be careful not to
  870.                  * increase the source viewport size, because that could
  871.                  * push the downscaling factor out of bounds.
  872.                  */
  873.                 src_x = src->x1 >> 16;
  874.                 src_w = drm_rect_width(src) >> 16;
  875.                 src_y = src->y1 >> 16;
  876.                 src_h = drm_rect_height(src) >> 16;
  877.  
  878.                 if (format_is_yuv(fb->pixel_format)) {
  879.                         src_x &= ~1;
  880.                         src_w &= ~1;
  881.  
  882.                         /*
  883.                          * Must keep src and dst the
  884.                          * same if we can't scale.
  885.                          */
  886.                         if (!can_scale)
  887.                                 crtc_w &= ~1;
  888.  
  889.                         if (crtc_w == 0)
  890.                                 state->visible = false;
  891.                 }
  892.         }
  893.  
  894.         /* Check size restrictions when scaling */
  895.         if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
  896.                 unsigned int width_bytes;
  897.                 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
  898.  
  899.                 WARN_ON(!can_scale);
  900.  
  901.                 /* FIXME interlacing min height is 6 */
  902.  
  903.                 if (crtc_w < 3 || crtc_h < 3)
  904.                         state->visible = false;
  905.  
  906.                 if (src_w < 3 || src_h < 3)
  907.                         state->visible = false;
  908.  
  909.                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
  910.  
  911.                 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 ||
  912.                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
  913.                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
  914.                         return -EINVAL;
  915.                 }
  916.         }
  917.  
  918.         if (state->visible) {
  919.                 src->x1 = src_x << 16;
  920.                 src->x2 = (src_x + src_w) << 16;
  921.                 src->y1 = src_y << 16;
  922.                 src->y2 = (src_y + src_h) << 16;
  923.         }
  924.  
  925.         dst->x1 = crtc_x;
  926.         dst->x2 = crtc_x + crtc_w;
  927.         dst->y1 = crtc_y;
  928.         dst->y2 = crtc_y + crtc_h;
  929.  
  930.         return 0;
  931. }
  932.  
  933. int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
  934.                               struct drm_file *file_priv)
  935. {
  936.         struct drm_intel_sprite_colorkey *set = data;
  937.         struct drm_plane *plane;
  938.         struct drm_plane_state *plane_state;
  939.         struct drm_atomic_state *state;
  940.         struct drm_modeset_acquire_ctx ctx;
  941.         int ret = 0;
  942.  
  943.         /* Make sure we don't try to enable both src & dest simultaneously */
  944.         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
  945.                 return -EINVAL;
  946.  
  947.         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
  948.             set->flags & I915_SET_COLORKEY_DESTINATION)
  949.                 return -EINVAL;
  950.  
  951.         plane = drm_plane_find(dev, set->plane_id);
  952.         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
  953.                 return -ENOENT;
  954.  
  955.         drm_modeset_acquire_init(&ctx, 0);
  956.  
  957.         state = drm_atomic_state_alloc(plane->dev);
  958.         if (!state) {
  959.                 ret = -ENOMEM;
  960.                 goto out;
  961.         }
  962.         state->acquire_ctx = &ctx;
  963.  
  964.         while (1) {
  965.                 plane_state = drm_atomic_get_plane_state(state, plane);
  966.                 ret = PTR_ERR_OR_ZERO(plane_state);
  967.                 if (!ret) {
  968.                         to_intel_plane_state(plane_state)->ckey = *set;
  969.                         ret = drm_atomic_commit(state);
  970.                 }
  971.  
  972.                 if (ret != -EDEADLK)
  973.                         break;
  974.  
  975.                 drm_atomic_state_clear(state);
  976.                 drm_modeset_backoff(&ctx);
  977.         }
  978.  
  979.         if (ret)
  980.                 drm_atomic_state_free(state);
  981.  
  982. out:
  983.         drm_modeset_drop_locks(&ctx);
  984.         drm_modeset_acquire_fini(&ctx);
  985.         return ret;
  986. }
  987.  
  988. static const uint32_t ilk_plane_formats[] = {
  989.         DRM_FORMAT_XRGB8888,
  990.         DRM_FORMAT_YUYV,
  991.         DRM_FORMAT_YVYU,
  992.         DRM_FORMAT_UYVY,
  993.         DRM_FORMAT_VYUY,
  994. };
  995.  
  996. static const uint32_t snb_plane_formats[] = {
  997.         DRM_FORMAT_XBGR8888,
  998.         DRM_FORMAT_XRGB8888,
  999.         DRM_FORMAT_YUYV,
  1000.         DRM_FORMAT_YVYU,
  1001.         DRM_FORMAT_UYVY,
  1002.         DRM_FORMAT_VYUY,
  1003. };
  1004.  
  1005. static const uint32_t vlv_plane_formats[] = {
  1006.         DRM_FORMAT_RGB565,
  1007.         DRM_FORMAT_ABGR8888,
  1008.         DRM_FORMAT_ARGB8888,
  1009.         DRM_FORMAT_XBGR8888,
  1010.         DRM_FORMAT_XRGB8888,
  1011.         DRM_FORMAT_XBGR2101010,
  1012.         DRM_FORMAT_ABGR2101010,
  1013.         DRM_FORMAT_YUYV,
  1014.         DRM_FORMAT_YVYU,
  1015.         DRM_FORMAT_UYVY,
  1016.         DRM_FORMAT_VYUY,
  1017. };
  1018.  
  1019. static uint32_t skl_plane_formats[] = {
  1020.         DRM_FORMAT_RGB565,
  1021.         DRM_FORMAT_ABGR8888,
  1022.         DRM_FORMAT_ARGB8888,
  1023.         DRM_FORMAT_XBGR8888,
  1024.         DRM_FORMAT_XRGB8888,
  1025.         DRM_FORMAT_YUYV,
  1026.         DRM_FORMAT_YVYU,
  1027.         DRM_FORMAT_UYVY,
  1028.         DRM_FORMAT_VYUY,
  1029. };
  1030.  
  1031. int
  1032. intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
  1033. {
  1034.         struct intel_plane *intel_plane;
  1035.         struct intel_plane_state *state;
  1036.         unsigned long possible_crtcs;
  1037.         const uint32_t *plane_formats;
  1038.         int num_plane_formats;
  1039.         int ret;
  1040.  
  1041.         if (INTEL_INFO(dev)->gen < 5)
  1042.                 return -ENODEV;
  1043.  
  1044.         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
  1045.         if (!intel_plane)
  1046.                 return -ENOMEM;
  1047.  
  1048.         state = intel_create_plane_state(&intel_plane->base);
  1049.         if (!state) {
  1050.                 kfree(intel_plane);
  1051.                 return -ENOMEM;
  1052.         }
  1053.         intel_plane->base.state = &state->base;
  1054.  
  1055.         switch (INTEL_INFO(dev)->gen) {
  1056.         case 5:
  1057.         case 6:
  1058.                 intel_plane->can_scale = true;
  1059.                 intel_plane->max_downscale = 16;
  1060.                 intel_plane->update_plane = ilk_update_plane;
  1061.                 intel_plane->disable_plane = ilk_disable_plane;
  1062.  
  1063.                 if (IS_GEN6(dev)) {
  1064.                         plane_formats = snb_plane_formats;
  1065.                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
  1066.                 } else {
  1067.                         plane_formats = ilk_plane_formats;
  1068.                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
  1069.                 }
  1070.                 break;
  1071.  
  1072.         case 7:
  1073.         case 8:
  1074.                 if (IS_IVYBRIDGE(dev)) {
  1075.                         intel_plane->can_scale = true;
  1076.                         intel_plane->max_downscale = 2;
  1077.                 } else {
  1078.                         intel_plane->can_scale = false;
  1079.                         intel_plane->max_downscale = 1;
  1080.                 }
  1081.  
  1082.                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
  1083.                         intel_plane->update_plane = vlv_update_plane;
  1084.                         intel_plane->disable_plane = vlv_disable_plane;
  1085.  
  1086.                         plane_formats = vlv_plane_formats;
  1087.                         num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
  1088.                 } else {
  1089.                         intel_plane->update_plane = ivb_update_plane;
  1090.                         intel_plane->disable_plane = ivb_disable_plane;
  1091.  
  1092.                         plane_formats = snb_plane_formats;
  1093.                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
  1094.                 }
  1095.                 break;
  1096.         case 9:
  1097.                 intel_plane->can_scale = true;
  1098.                 intel_plane->update_plane = skl_update_plane;
  1099.                 intel_plane->disable_plane = skl_disable_plane;
  1100.                 state->scaler_id = -1;
  1101.  
  1102.                 plane_formats = skl_plane_formats;
  1103.                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
  1104.                 break;
  1105.         default:
  1106.                 kfree(intel_plane);
  1107.                 return -ENODEV;
  1108.         }
  1109.  
  1110.         intel_plane->pipe = pipe;
  1111.         intel_plane->plane = plane;
  1112.         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
  1113.         intel_plane->check_plane = intel_check_sprite_plane;
  1114.         possible_crtcs = (1 << pipe);
  1115.         ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
  1116.                                        &intel_plane_funcs,
  1117.                                        plane_formats, num_plane_formats,
  1118.                                        DRM_PLANE_TYPE_OVERLAY, NULL);
  1119.         if (ret) {
  1120.                 kfree(intel_plane);
  1121.                 goto out;
  1122.         }
  1123.  
  1124.         intel_create_rotation_property(dev, intel_plane);
  1125.  
  1126.         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
  1127.  
  1128. out:
  1129.         return ret;
  1130. }
  1131.